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G522-0319-00 (IBM Order Number)
MPC604E9QEC/D (Motorola Order Number) 3/98
Advance Information
PID9q-604e Hardware Specications
The PowerPC 604e microprocessor is an implementation of the PowerPC family of reduced instruction set computing (RISC) microprocessors. In this document, the term O604O is used as an abbreviation for OPowerPC 604 microprocessorO and the term O604eO is used as an abbreviation for OPowerPC 604e microprocessorO. The PowerPC 604e microprocessors are available from Motorola as MPC604e and from IBM as PPC604e. When ordering, note that PID9q-604e processors prior to revision 1.1 are referenced as the PID10q-604e. This document contains pertinent physical characteristics of the 604e. This document contains the following topics: Section 1.1, OOverviewO Section 1.2, OFeaturesO Section 1.3, OGeneral ParametersO Section 1.4, OElectrical and Thermal CharacteristicsO Section 1.5, OPin AssignmentsO Section 1.6, OPinout ListingsO Section 1.7, OPackage DescriptionO Section 1.8, OSystem Design InformationO Section 1.9, OOrdering Information 2 2 5 6 16 17 19 20 27
PID9q-604e Hardware Specifications Topic Page
To locate any published errata or updates for this document, refer to the website at http://www.mot.com/ SPS/PowerPC/ or at http://www.chips.ibm.com/products/ppc.
The PowerPC name is a registered trademark and the PowerPC logotype, PowerPC 604 and PowerPC 604e are trademarks of International Business Machines Corporation, used by Motorola under license from International Business Machines Corporation. FLOTHERM is a registered trademark of Flomerics Ltd., UK. This document contains information on a new product under development by Motorola and IBM. Motorola and IBM reserve the right to change or discontinue this product without notice.
(c) Motorola Inc., 1997. All rights reserved. Portions hereof (c) International Business Machines Corporation, 19911997. All rights reserved.
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PowerPC 604e RISC Microprocessor Family:
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1.1 Overview
The 604e is an implementation of the PowerPC family of reduced instruction set computing (RISC) microprocessors. The 604e implements the PowerPC architecture as it is specied for 32-bit addressing, which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits, and oatingpoint data types of 32 and 64 bits (single-precision and double-precision). For 64-bit PowerPC implementations, the PowerPC architecture provides additional 64-bit integer data types, 64-bit addressing, and related features. The 604e is a superscalar processor capable of issuing four instructions simultaneously. As many as seven instructions can nish execution in parallel. The 604e has seven execution units that can operate in parallelNa oating-point unit (FPU), a branch processing unit (BPU), a condition register unit (CRU), a load/store unit (LSU), and three integer units (IUs)Ntwo single-cycle integer units (SCIUs) and one multiple-cycle integer unit (MCIU). This parallel design, combined with the PowerPC architectureOs specication of uniform instructions that allows for rapid execution times, yields high efciency and throughput. The 604eOs rename buffers, reservation stations, dynamic branch prediction, and completion unit increase instruction throughput, guarantee in-order completion, and ensure a precise exception model. (Note that the PowerPC architecture specication refers to all exceptions as interrupts.) The 604e has separate memory management units (MMUs) and separate 32-Kbyte on-chip caches for instructions and data. The 604e implements two 128-entry, two-way set associative translation lookaside buffers (TLBs), one for instructions and one for data, and provides support for demand-paged virtual memory address translation and variable-sized block translation. The TLBs and the cache use least-recently used (LRU) replacement algorithms. The 604e has a 64-bit external data bus and a 32-bit address bus. The 604e interface protocol allows multiple masters to compete for system resources through a central external arbiter. Additionally, on-chip snooping logic maintains data cache coherency for multiprocessor applications. The 604e supports single-beat and burst data transfers for memory accesses and memory-mapped I/O accesses. The 604e uses an advanced, 1.9V CMOS process technology and is fully compatible with 3.3V TTL devices.
1.2 Features
This section summarizes features of the 604eOs implementation of the PowerPC architecture. Major features of the 604e are as follows: High-performance, superscalar microprocessor N As many as four instructions can be issued per clock N As many as seven instructions can start executing per clock (including three integer instructions) N Single-clock-cycle execution for most instructions
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Seven independent execution units and two register les N BPU featuring dynamic branch prediction Two-entry reservation station Out-of-order execution through two branches Shares dispatch bus with CRU 64-entry fully-associative branch target address cache (BTAC). In the 604e, the BTAC can be disabled and invalidated.
N Condition register logical unit Two-entry reservation station Shares dispatch bus with BPU
N Two single-cycle IUs (SCIUs) and one multiple-cycle IU (MCIU)
Instructions that execute in the SCIU take one cycle to execute; most instructions that execute in the MCIU take multiple cycles to execute. The MCIU has a single-entry reservation station and provides early exit (three cycles) for 16- x 32-bit and overow operations. N Three-stage oating-point unit (FPU) Fully IEEE 754-1985-compliant FPU for both single- and double-precision operations Fully pipelined, single-pass double-precision design Hardware support for denormalized numbers Two-entry reservation station to minimize stalls Thirty-two 64-bit FPRs for single- or double-precision operands N Load/store unit (LSU) Two-entry reservation station to minimize stalls Single-cycle, pipelined cache access Dedicated adder performs effective address (EA) calculations Performs alignment and precision conversion for oating-point data Performs alignment and sign extension for integer data Four-entry nish load queue (FLQ) provides load miss buffering Six-entry store queue Supports both big- and little-endian modes Rename buffers N Twelve GPR rename buffers N Eight FPR rename buffers N Eight condition register (CR) rename buffers Supports non-IEEE mode for time-critical operations
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Thirty-two GPRs for integer operands
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Each SCIU has a two-entry reservation station to minimize stalls
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512-entry branch history table (BHT) with two bits per entry for four levels of predictionN not-taken, strongly not-taken, taken, strongly taken
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Completion unit N The completion unit retires an instruction from the 16-entry reorder buffer when all instructions ahead of it have been completed and the instruction has nished execution. N Guarantees sequential programming model (precise exception model) N Monitors all dispatched instructions and retires them in order N Tracks unresolved branches and ushes executed, dispatched, and fetched instructions if branch is mispredicted N Retires as many as four instructions per clock N 32-Kbyte, four-way set-associative instruction and data caches N LRU replacement algorithm N 32-byte (eight-word) cache block size
N Physically indexed/physical tags. (Note that the PowerPC architecture refers to physical address space as real address space.) N Cache write-back or write-through operation programmable on a per page or per block basis N Instruction cache can provide four instructions per clock; data cache can provide two words per clock N Caches can be disabled in software N Caches can be locked
N Parity checking performed on both caches N Data cache coherency (MESI) maintained in hardware N Instruction cache coherency maintained in hardware N Data cache line-ll buffer forwarding. In the 604 only the critical double word of the cache block was made available to the requesting unit at the time it was burst into the line-ll buffer. Subsequent data was unavailable until the cache block was lled. On the 604e, subsequent data is also made available as it arrives in the line-ll buffer. Separate memory management units (MMUs) for instructions and data N Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte segment size N Both TLBs are 128-entry and two-way set associative N TLBs are hardware reloadable (that is, the page table search is performed in hardware) N Separate IBATs and DBATs (four each) also dened as SPRs N Separate instruction and data translation lookaside buffers (TLBs) N LRU replacement algorithm N 52-bit virtual address; 32-bit physical address Bus interface features include the following: N Selectable processor-to-bus clock frequency ratios (1:1, 3:2, 2:1, 5:2, 3:1, 7:2, 4:1, 9:2, 5:1, 11:2, 6:1, 13:2, and 7:1) N A 64-bit split-transaction external data bus with burst transfers N Support for address pipelining and limited out-of-order bus transactions
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N Secondary data cache support provided
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Separate on-chip instruction and data caches (Harvard architecture)
N Four burst write queuesNthree for cache copyback operations and one for snoop push operations N Two single-beat write queues N Additional signals and signal redenition for direct-store operations N Provides a data streaming mode that allows consecutive burst read data transfers to occur without intervening dead cycles. This mode also disables data retry operations. N No-DRTRY mode eliminates the DRTRY signal from the qualied bus grant and allows read operations. This improves performance on read operations for systems that do not use the DRTRY signal. No-DRTRY mode makes read data available to the processor one bus clock cycle sooner than if normal mode is used. Multiprocessing support features include the following: N Hardware enforced, four-state cache coherency protocol (MESI) for data cache. Bits are provided in the instruction cache to indicate only whether a cache block is valid or invalid. N Separate port into data cache tags for bus snooping N Load/store with reservation instruction pair for atomic memory references, semaphores, and other multiprocessor operations Power management N Operating voltage of 1.9 100 mV N NAP mode supports full shut down and snooping Performance monitor can be used to help in debugging system designs and improving software efciency, especially in multiprocessor systems. In-system testability and debugging features through JTAG boundary-scan capability
1.3 General Parameters
The following list provides a summary of the general parameters of the 604e: Technology Die size Transistor count Logic design Package Core power supply I/O power supply 0.25 m CMOS, ve-layer metal 6.97 mm x 6.75mm (47 mm2) 5.1 million Fully-static Surface mount 255-lead ceramic ball grid array (CBGA) 1.9 V 100 mV dc 3.3 V 5% V dc
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1.4 Electrical and Thermal Characteristics
This section provides both the AC and DC electrical specications and thermal characteristics for the 604e.
1.4.1 DC Electrical Characteristics
The tables in this section describe the 604e DC electrical characteristics. Table 1 provides the absolute maximum ratings.
Table 1. Absolute Maximum Ratings
Core supply voltage PLL supply voltage I/O supply voltage Input voltage Overshoot (with respect to system GND) Undershoot (with respect to system GND) Storage temperature range Notes:
IN A RY
Vdd AVdd OVdd Vin 0.3 to 3.8 0.3 to 3.3 4.0 Vovs
Characteristic
Symbol
Value
Unit V V V V V V C
0.3 to 2.80 0.3 to 2.80
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Vuns
-0.45
Tstg
55 to 150
2. Caution: Power up/down sequence must be adhered to to avoid device damage. The power-up sequence is GND, Vdd, OVdd The power-down sequence is OVdd, Vdd, GND In either case the rule OVdd Vdd 2.0V must be followed. 3. Caution: During system power-up, any 604e signal VDDcore must not exceed 2.0V 4. Caution: 604e inputs are not 5V tolerant.
Table 2 provides the recommended operating conditions for the 604e.
Table 2. Recommended Operating Conditions
Characteristic Core supply voltage PLL supply voltage I/O supply voltage Input voltage Junction temperature Vdd AVdd OVdd Vin Tj Symbol Value 1.8 to 2.0 1.8 to 2.0 3.135 to 3.465 GND to 3.3 0 to 105 Unit V V V V C
Note: These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed.
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1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device.
Table 3 provides the thermal characteristics for the 604e.
Table 3. Thermal Characteristics
Characteristic CBGA package thermal resistance, junction-to-top of die Symbol qJC Value 0.03 Rating C/W
Note: Refer to Section 1.8, OSystem Design Information,O for more details about thermal management.
Table 4 provides the DC electrical characteristics for the 604e.
Table 4. DC Electrical Specifications
Vdd = AVdd = 1.9 100 mV dc, OVdd = 3.3 5% V dc, GND = 0 V dc, 0 Tj 105 C
Characteristic Input high voltage (all inputs except SYSCLK) Input low voltage (all inputs except SYSCLK) SYSCLK input high voltage SYSCLK input low voltage Input leakage current, Vin = 3.3 V1
IN A RY
Symbol Min VIH VIL 2.0 0.0 2.4 0.0 N N 2.4 N N N CVIH CVIL Iin ITSI VOH VOL Cin Cin Zo 56 42 30
Max 3.465 0.8 3.465 0.4 10 10 N 0.4 10.0 15.0 V V V V
Unit
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A A V V pF pF
Output high voltage, IOH = 2 mA Output low voltage, IOL = 2 mA
Capacitance, Vin = 0 V, f = 1 MHz2 (excludes TS, ABB, DBB, and ARTRY) Capacitance, Vin = 0 V, f = 1 MHz2 (for TS, ABB, DBB, and ARTRY) Output impedance Normal mode (DRV_MOD[01] = 01) Strong mode (DRV_MOD[01] = 10) Herculean mode (DRV_MOD[01] = 11) Notes:
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Hi-Z (off-state) leakage current, Vin = 3.3 V1
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84 57 30
1. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK, and JTAG signals). 2. Capacitance values are guaranteed by design and characterization, and are not tested. 3. Output impedance is guaranteed by design and is not tested. Refer to IBIS simulation models for output impedance values based on Vdd and OVdd tolerances used in system.
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Table 5 provides the power consumption for the 604e.
Table 5. Power Consumption
CPU Clock: SYSCLK Full-On Mode Typical Maximum Nap Mode Typical Maximum TBD 0.78 6.0 10.6 6.8 12.0 7.5 13.4 W W Processor Core Frequency Unit 266 MHz 300 MHz 333 MHz
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TBD 0.80 TBD 0.82 300 MHz Min 266 532 38 10 1.0 Max 300 600 100 28 2.0 333 MHz Min 300 600 Max 333 666 42.9 100 10 1.0 25 2.0 ns ns
W W
Notes: 1. These values apply for all valid PLL_CFG[03] settings and do not include output driver power (OVdd) or analog supply power (AVdd). OVdd power is system dependent but is typically 10% of Vdd. Worst-case AVdd = 15 mW. 2. Typical power is an average value estimated at Vdd = AVdd = 1.9 V, OVdd = 3.3 V, Tj = 25 C in a system executing typical applications and benchmark sequences. Typical power numbers should be used in planning for proper thermal management.
4. Nap mode power consumption is estimated, and assumes no snoop activity.
1.4.2 AC Electrical Characteristics
This section provides the AC electrical characteristics for the 604e. These specications are for 266, 300, and 333 MHz processor core frequencies. The processor core frequency is determined by the bus (SYSCLK) frequency and the settings of the PLL_CFG[03] signals. All timings are specied respective to the rising edge of SYSCLK.
1.4.2.1 Clock AC Specications
Table 6 provides the clock AC timing specications as dened in Figure 1.
Table 6. Clock AC Timing Specifications
Vdd = AVdd = 1.9 100 mV dc, OVdd = 3.3 5% V dc, GND = 0 V dc, 0 Tj 105 C
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Characteristic Min Processor frequency VCO frequency SYSCLK frequency 250 500 35.7 10 1.0 Max 266 532 100 35 2.0
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3. Maximum power is estimated at Vdd = AVdd = 2.0 V, OVdd = 3.465 V,Tj = 0 C using a worst-case instruction mix. These values should be used for power supply design.
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266 MHz
Unit
Notes
MHz MHz MHz
1 1 1, 6
1 2, 3
SYSCLK cycle time SYSCLK rise and fall time
2
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Table 6. Clock AC Timing Specifications (Continued)
Vdd = AVdd = 1.9 100 mV dc, OVdd = 3.3 5% V dc, GND = 0 V dc, 0 Tj 105 C
266 MHz Num Characteristic Min 4 SYSCLK duty cycle measured at 0.9 V SYSCLK jitter 604e internal PLL relock time 40 N N Max 60 150 100
300 MHz Min 40 N N Max 60 150 100
333 MHz Unit Min 40 N N Max 60 150 100 % ps ms 3 4 3, 5 Notes
Notes: 1. Caution: The SYSCLK frequency and PLL_CFG[03] settings must be chosen such that the resulting SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[03] signal description in Section 1.8, OSystem Design Information,O for valid PLL_CFG[03] settings, and to Section 1.9, OOrdering Information,O for available frequencies and part numbers. 2. Rise and fall times for the SYSCLK input are measured from 0.4 V to 1.8 V. 3. Timing is guaranteed by design and characterization, and is not tested. 4. Cycle-to-cycle jitter, and is guaranteed by design.
Figure 1 provides the SYSCLK input timing diagram.
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6. 604e processors are tested at the maximum SYSCLK frequencies shown in the AC timing specications. It is possible to attain higher SYSCLK frequencies through proper system design.
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5. PLL-relock time is the maximum time required for PLL lock after a stable Vdd, OVdd, AVdd, and SYSCLK are reached during the power-on reset sequence. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time (100 ms) during the power-on reset sequence.
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CVih CVil
2
3
SYSCLK
VM
VM = Midpoint Voltage (0.9 V)
Figure 1. SYSCLK Input Timing Diagram
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1.4.2.2 Input AC Specications
Table 7 provides the input AC timing specications for the 604e as dened in Figure 2. These specications are for 266, 300, and 333 MHz processor core frequencies.
Table 7. Input AC Timing Specifications1
Vdd = AVdd = 1.9 100 mV dc, OVdd = 3.3 5% V dc, GND = 0 V dc, 0 Tj 105 C
266, 300, 333 MHz Num Characteristic Min 7a 7b 8 9 10 ARTRY, SHD, ABB, TS, XATS, AACK,BG, DRTRY, TA, DBG, DBB, TEA, DBDIS, and DBWO valid to SYSCLK (input setup) All other inputs valid to SYSCLK (input setup)7 SYSCLK to all inputs invalid (input hold) 3.50 Max N ns ns ns ns ns 3, 4, 5, 6 3, 4, 5, 6 2 Unit Notes
Mode select input valid to HRESET (input setup for DRTRY)
HRESET to mode select input invalid (input hold for DRTRY)
Notes: 1. Input specications are measured from the TTL level (0.8 or 2.0 V) of the signal in question to the 0.9 V of the rising edge of the input SYSCLK. Input and output timings are measured at the pin (see Figure 2). 2. All other input signals include the following signalsNall inputs except ARTRY, SHD, ABB, TS, XATS, AACK, BG, DRTRY, TA, DBG, DBB, DBWO, DBDIS, TEA, and JTAG inputs. 3. The setup and hold time is with respect to the rising edge of HRESET (see Figure 3).
5. These values are guaranteed by design, and are not tested. 6. Note this is for conguration of the fast-L2 mode and the no-DRTRY mode. 7. Setup time is extended by 0.5 ns for these signals when Hysteresis On mode is enabled.
Figure 2 provides the input timing diagram for the 604e.
SYSCLK
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4. tsysclk is the period of the external clock (SYSCLK) in nanoseconds.
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ALL INPUTS
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VM
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VM = Midpoint Voltage (0.9 V)
Figure 2. Input Timing Diagram
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2.50 0.5 8 * tsysclk 0.5
N N
N N
Figure 3 provides the mode select input timing diagram for the 604e.
HRESET
VM
9
10
VM = Midpoint Voltage (0.9 V)
Figure 3. Mode Select Input Timing Diagram
1.4.2.3 Output AC Specications
Table 8 provides the output AC timing specications for the 604e (refer to Figure 4).
Vdd = AVdd = 1.9 100 mV dc, OVdd = 3.3 5% V dc, GND = 0 V dc, 0 Tj 105 C, drive mode [11]6
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The output specications of the 604e for both driving high and driving low depend on the capacitive loading on each output and the drive capability enabled for that output. Additionally, the timing specications for outputs driving low also depend on the voltage swing required to drive to 0.4V. Table 8 provides the output AC timing specications for a 5pF, 50 W transmission line load. In order to derive the actual timing specications for a given set of conditions, it is recommended that IBIS simulation models be used. The IBIS models are currently based on device simulation data. Compatibility mode specications are provided to support PID9q-604e use in existing designs. Contact the local Motorola or IBM sales ofce for information on the availability of these models.
Table 8. Output AC Timing Specifications1
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Num
Characteristic Min Max N 3.75 4.75
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266, 300, 333 MHz 3.4 3.4
1.0* tsysclk
DRTRY
Compatibility Mode 0.75 Min 4.75 Max 5.75 Max 0.5 Min 4.4 Max
Unit Notes
11 12 13 14 15
SYSCLK to output driven (output enable time) SYSCLK to TS, XATS, ARTRY, SHD, ABB and DBB output valid SYSCLK to all other signals output valid SYSCLK to output invalid (output hold) SYSCLK to output high impedance (all signals except ARTRY, SHD, ABB, DBB, TS, and XATS) SYSCLK to output high impedance TS, XATS SYSCLK to ABB and DBB high impedance after precharge SYSCLK to ARTRY and SHD high impedance before precharge
0.75 N N 0.0 N
ns ns ns ns ns
2, 5 5 5 2, 5 5
16 17 18
N
N
4.4 Max
1.0* tsysclk Max
ns ns ns
5 4 5
N
3.4
4.4 Max
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Table 8. Output AC Timing Specifications1 (Continued)
Vdd = AVdd = 1.9 100 mV dc, OVdd = 3.3 5% V dc, GND = 0 V dc, 0 Tj 105 C, drive mode [11]6
266, 300, 333 MHz Num Characteristic Min 19 20 21 SYSCLK to ARTRY, and SHD precharge enable Maximum delay to ARTRY and SHD precharge SYSCLK to ARTRY and SHD high impedance after precharge Rise time (ARTRY, SHD, ABB, DBB, TS, and XATS) Rise time (all signals except ARTRY, SHD, ABB, DBB, TS, and XATS) Fall time (ARTRY, SHD, ABB, DBB, TS, and XATS)
0.5* tsysclk + 0.75 N
Max
Compatibility Mode
0.5* tsysclk + 0.75 Max
Unit Notes
ns ns ns ns ns ns ns
4 4 4 3 3 3 3
N N
1.5* tsysclk 2.0* tsysclk
1.5* tsysclk Max 2.0* tsysclk Max
1.0 1.0 1.0
2. All AC timing is based on a 5pF, 50 W transmission line load 3. These specications are nominal values 4. tsysclk is the period of the external bus clock (SYSCLK) in nanoseconds (ns). When the unit is given as tsysclk the numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question. 5. These specications are nominal values for Fast Out mode; refer to Section 1.8.2, OInput and Output Signal Mode SelectionO for signal conguration to enable Fast Out mode.The PID9q-604e is tested in Fast Out mode. Compatibility mode is guaranteed by design and is not tested. 6. To operate in accordance with these specications, the drive mode signals must be congured with DRVMOD0 = high, and DRVMOD1 = high.
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Notes: 1. All output specications are measured from the 0.9 V level of the rising edge of SYSCLK to the TTL level (0.5 V or 2.0 V) of the signal in question. Both input and output timings are measured at the pin (see Figure 4).
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Fall time (all signals except ARTRY, SHD, ABB, 1.0 DBB, TS, and XATS)
IN A RY
1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0
Figure 4 provides the output timing diagram for the 604e.
SYSCLK
VM
13 14 11 15
VM
VM
ALL OUTPUTS (Except TS, ABB, DBB, ARTRY, XATS, SHD)
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TS, XATS
ABB, DBB
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Characteristic TCK frequency of operation 1 2 3 4 5 6 7 TCK cycle time TCK clock pulse width measured at 0.9 V TCK rise and fall times TRST setup time to TCK rising edge TRST assert time Boundary-scan input data setup time Boundary-scan input data hold time
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ARTRY, SHD
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VM = Midpoint Voltage (0.9 V)
Figure 4. Output Timing Diagram
1.4.3 JTAG AC Timing Specications
Table 9 provides the JTAG AC timing specications.
Table 9. JTAG AC Timing Specifications (Independent of SYSCLK)
Vdd = AVdd = 1.9 100 mV dc, OVdd = 3.3 5%, GND = 0 V dc, CL = 5 pF, 0 Tj 105 C
Num
IN A RY
16 17 21 20 19
12
14
Min 0 62.5 25 0 13 40 0 27 16 N N 3 N N N N
Max
Unit MHz ns ns ns ns ns ns ns
Notes
1
2 2
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Table 9. JTAG AC Timing Specifications (Independent of SYSCLK) (Continued)
Vdd = AVdd = 1.9 100 mV dc, OVdd = 3.3 5%, GND = 0 V dc, CL = 5 pF, 0 Tj 105 C
Num 8 9 10 11 12 13
Characteristic TCK to output data valid TCK to output high impedance TMS, TDI data setup time TMS, TDI data hold time TCK to TDO data valid TCK to TDO high impedance 4 3 0 25 4
Min 25 24 N N 24
Max ns ns ns ns ns
Unit
Notes 3 3
Notes: 1. TRST is an asynchronous signal. The setup time is for test purposes only. 2. Non-test signal input timing with respect to TCK.
3. Non-test signal output timing with respect to TCK.
Figure 5 provides the JTAG clock input timing diagram.
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VM 3 5
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IN A RY
3 15
1 2 VM 2 4
ns
TCK
3
VM
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TCK TRST
VM = Midpoint Voltage (0.9 V)
Figure 5. Clock Input Timing Diagram
Figure 6 provides the TRST timing diagram.
Figure 6. TRST Timing Diagram
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Figure 7 provides the boundary-scan timing diagram.
TCK
6 7
Data Inputs
8
Input Data Valid
Data Outputs
Data Outputs
Figure 8 provides the test access port timing diagram.
TCK
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12 13 12
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Figure 7. Boundary-Scan Timing Diagram
TDI, TMS
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TDO
TDO
TDO
Figure 8. Test Access Port Timing Diagram
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9 8 10 11 Input Data Valid Output Data Valid Output Data Valid
Data Outputs
Output Data Valid
Output Data Valid
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1.5 Pin Assignments
Motorola and IBM both offer a ceramic ball grid array (CBGA) package. Both IBM and Motorola CBGA packages have identical pinouts. Figure 9 (in part A) shows the pinout of the CBGA package as viewed from the top surface. Part B shows the side prole of the CBGA package to indicate the direction of the top surface view.
Part A 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 A B C D E F G H J K L M N P
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R T Not to Scale Part B
Substrate Assembly Encapsulant View Die
Figure 9. Pinout of the CBGA Package as Viewed from the Top Surface
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1.6 Pinout Listings
Table 10 provides the pinout listing for the 604e CBGA package.
Table 10. Pinout Listing for the CBGA Package
Signal Name A[031] Pin Number C16, E04, D13, F02, D14, G01, D15, E02, D16, D04, E13, GO2, E15, H01, E16, H02, F13, J01, F14, J02, F15, H03, F16, F04, G13, K01, G15, K02, H16, M01, J15, P01 L02 K04 C01, B04, B03, B02 A04
1
Active High I/O
I/O
ABB AP[03] APE ARRAY_WR ARTRY AVDD BG BR CI CKSTP_IN CKSTP_OUT CLK_OUT CSE[01] DBB DBG DBDIS DBWO DH[031]
IN A RY
AACK
Low Low High
Input I/O I/O Output Input I/O N Input Output Output Input Output Output Output I/O Input Input Input I/O
Low Low Low N Low Low Low Low Low N
B07 J04 A10 L01 B06 E01
D08 A06
PR
D07
B01, B05 J14
EL
IM
High Low Low Low Low High
N01 H15 G04 P14, T16, R15, T15, R13, R12, P11, N11, R11,T12, T11, R10, P09, N09, T10, R09, T09, P08, N08, R08, T08, N07, R07, T07, P06, N06, R06, T06, R05, N05, T05, T04 K13, K15, K16, L16, L15, L13, L14, M16, M15, M13, N16, N15, N13, N14, P16, P15, R16, R14, T14, N10, P13, N12, T13, P03, N03, N04, R03, T01, T02, P04, T03, R04 M02, L03, N02, L04, R01, P02, M04, R02 A05 G16 D05 C03 F01
DL[031]
High
I/O
DP[07] DPE DRTRY DRVMOD03 DRVMOD13 GBL
High Low Low High High Low
I/O Output Input Input Input I/O
PID9q-604e Hardware Specifications PRELIMINARYNSUBJECT TO CHANGE WITHOUT NOTICE
17
Table 10. Pinout Listing for the CBGA Package (Continued)
Signal Name GND Pin Number C05, C12, E03, E06, E08, E09, E11, E14, F05, F07, F10, F12, G06, G08, G09, G11, H05, H07, H10, H12, J05, J07, J10, J12, K06, K08, K09, K11, L05, L07, L10, L12, M03, M06, M08, M09, M11, M14, P05, P12 B08 A07 B15 D11 D06
1
Active N N
I/O
HALTED HRESET INT L1_TSTCLK 1 L2_INT L2_TSTCLK
High Low
Output Input Input Input Input Input Input Input N Input Output Input I/O Input Input Input Input Input I/O Output Input Input Output Input Input Input I/O I/O I/O
D12 B10 C13
LSSD_MODE 1 MCP OVDD PLL_CFG[03] RSRV RUN SHD SMI SRESET SYSCLK TA TBEN TBST TC[02] TCK TDI TDO TEA TMS TRST TS TSIZ[02] TT[04]
A08, B09, A09, D09 D01 C08 H04 A16 B14
IM
C07, E05, E07, E10, E12, G03, G05, G12, G14, K03, K05, K12, K14, M05, M07, M10, M12, P07, P10
EL
PR
C09 H14 C02 A14
A02, A03, C06 C11 A11 A12 H13 B11 C10 J13 A13, D10, B12 B13, A15, B16, C14, C15
18
PID9q-604e Hardware Specifications PRELIMINARYNSUBJECT TO CHANGE WITHOUT NOTICE
IN A RY
Low Low High Low Low Low
N High Low High Low Low Low N Low High Low High High High High Low High Low Low High High
Table 10. Pinout Listing for the CBGA Package (Continued)
Signal Name WT VDD VOLTDETGND2 XATS D02 F06, F08, F09, F11, G07, G10, H06, H08, H09, H11, J06, J08, J09, J11, K07, K10, L06, L08, L09, L11 F03 J16 Low I/O Pin Number Active Low N I/O Output N
2. NC (no-connect) in the 604; internally tied to GND in the 604e CBGA package to indicate to the power supply that a low-voltage processor is present. 3. To operate in accordance with these specications, the drive mode signals must be congured with DRVMOD0 = high, and DRVMOD1 = high.
1.7 Package Description
Package outline Interconnects Pitch 21 x 21 mm
Maximum module height Ball diameter
PR
PID9q-604e Hardware Specifications PRELIMINARYNSUBJECT TO CHANGE WITHOUT NOTICE
EL
255
1.27 mm (50 mil) 3.30 mm 0.89 mm (35 mil)
IM
The package parameters for the 604e are provided in the following list. The package type is 21 mm, 256lead ceramic ball grid array (CBGA).
IN A RY
Notes: 1. These are test signals for factory use only and must be pulled up to Vdd for normal machine operation.
19
1.7.0.1 Mechanical Dimensions of the CBGA Package
Figure 10 provides the mechanical dimensions and bottom surface nomenclature of the IBM and Motorola CBGA package.
2X
0.2
A1 CORNER
D
A
C
E
E1
2X
0.2 B D1
IM
IN A RY
0.15 C A2 A1 A DIM A A1 A2 b D D1 e E E1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. TOP SIDE A1 CORNER INDEX IS A METALIZED FEATURE WITH VARIOUS SHAPES.BOTTOM SIDE A1 CORNER IS DESIGNATED WITH A BALL MISSING FROM THE ARRAY.
e/2
e
255X
Figure 10. Mechanical Dimensions and Bottom Surface Nomenclature of the CBGA Package
1.8 System Design Information
This section provides electrical and thermal design recommendations for successful application of the 604e.
1.8.1 PLL Conguration
The 604e PLL is congured by the PLL_CFG[03] signals. For a given SYSCLK (bus) frequency, the PLL conguration signals set the internal CPU and VCO frequency of operation. The PLL conguration for the 604e is shown in Table 11 for nominal frequencies.
20
PR
0.3 C A B 0.15 C
PID9q-604e Hardware Specifications PRELIMINARYNSUBJECT TO CHANGE WITHOUT NOTICE
EL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
T R P N M L K J H G F E D C B A
Millimeters MIN MAX 2.50 3.30 0.79 0.99 1.00 1.40 0.82 0.93 21.00 BSC 5.00 16.00 1.27 BSC 21.00 BSC 5.00 16.00
e/2 b
Table 11. PLL Configuration
PLL_CFG [03] CPU Frequency in MHz (VCO Frequency in MHz) VCO Multiplier Bus 25 MHz N N N N N N N N Bus 33.3 MHz N N N Bus 40 MHz N 40 (320) N Bus 50 MHz N 50 (400) N Bus 60 MHz N 60 (480) N Bus 66.6 MHz N 66 (533) N Bus 83.3 MHz N 83.3 (666) N N 208 (416) 250 (500) 292 (584) 333 (666) N N N N N N Bus 100 MHz N N N 200 (400) 250 (500) 300 (600) 350 (700) N N N N N N N
Bin
Dec
CPU/ SYSCLK Ratio
0000 0001 1100 0100 0110 1000 1110 1010 0111 1011 1001 1101 0101 0010 0011 1111
0 1 12 4 6 8 14 10 7 11 9 13 5 2 3 15
1:1 1:1 1.5:1 2:1 2.5:1 3:1 3.5:1 4:1 4.5:1 5:1
x2 x8 x2 x2 x2 x2 x2 x2
N N N N N
IM
N N N N 200 (400) 216 (433) 233 (466) N N N N N
EL
x2
PR
x2
5.5:1
x2
6:1 6.5:1 7:1
x2 x2 x2
Notes: 1. Some PLL congurations may select bus, CPU, or VCO frequencies which are not supported; see Section 1.4.2.2, OInput AC Specications,O for valid SYSCLK and VCO frequencies. 2. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set for 1:1 mode operation. This mode is intended for factory use only. Note: The AC timing specications given in this document do not apply in PLL-bypass mode.
PID9q-604e Hardware Specifications PRELIMINARYNSUBJECT TO CHANGE WITHOUT NOTICE
IN A RY
N N N N N N N N N N N N N N 200 (400) 220 (440) 240 (480) 260 (520) 280 (560) N 200 (400) 225 (450) 250 (500) 275 (550) 300 (600) 325 (650) 350 (700) 210 (420) 240 (480) 270 (540) 300 (600) 330 (660) N N N N N N N PLL bypass Clock off
200 (400) 233 (466) 266 (532) 300 (600) 333 (666)
21
1.8.2 Input and Output Signal Mode Selection
The PID9q-604eOs input buffers can be congured through the connection of the ARRAY_WR signal to provide input hysteresis and enable the CLKOUT signal. If the ARRAY_WR signal is connected to OVdd, the PID9q-604e will select the Hysteresis Off input buffer threshold mode, and the CLKOUT signal is enabled, which is the default mode for this specication. When Hysteresis OFF mode is selected the VM is 0.9V. If ARRAY_WR is connected to GND, Hysteresis On mode is selected, and the CLKOUT signal is placed in a high impedance state. When Hysteresis On mode is selected, the VM is 1.3V, and the input transition points are 1.1V for VIL and 1.5V for VIH. Hysteresis On mode provides for greater noise immunity on inputs, and the input hold time requirement for Low to High transitions is increased. When the ARRAY_WR signal is connected to the HRESET signal, Hysteresis On mode is selected, and the CLKOUT signal is enabled. If the ARRAY_WR signal is connected to an inverted HRESET signal, Hysteresis Off mode is selected, and the CLKOUT signal is placed in a high impedance state. Table 12 below shows the conguration of the ARRAY_WR signal to select input signal hysteresis and enable the CLKOUT signal.
Table 12. Input Signal Hysteresis and CLKOUT Signal Configuration
Signal ARRAY_WR
IM
Connected to
IN A RY
Mode Selected Hyteresis Off CLKOUT Enabled Hyteresis On CLKOUT Enabled
Notes 1
OVdd
EL
GND
Hyteresis On CLKOUT high impedance
PR
HRESET signal
HRESET
Hyteresis Off CLKOUT high impedance
2
Notes: 1. Default Mode 2.HRESET is the inverted state of the HRESET signal
The PID9q-604e implements a Fast Out output mode which allows increased system bus frequencies. The PID9q-604e can be congured for Fast Out mode by connecting the L2_TSTCLK signal to GND or the HRESET signal. When Fast Out mode is enabled, the output valid and output hold times are reduced. If the L2_TSTCLK signal is connected to OVdd or to an inverted HRESET, compatibility mode is selected.
22
PID9q-604e Hardware Specifications PRELIMINARYNSUBJECT TO CHANGE WITHOUT NOTICE
Table 13 describes the conguration of the L2_TSTCLK signal to select Fast Out or compatibility output modes.
Table 13. FastOut/Compatibility Output Signal Configuration
Signal L2_TSTCLK OVdd GND HRESET HRESET Notes: 1. Default Mode Connected to Mode Selected Compatibility FastOut FastOut 1 Notes
IN A RY
Compatibility
2
2.HRESET is the inverse state of the HRESET signal
1.8.3 PLL Power Supply Filtering
Vdd
EL
10 W
IM
10 F
The AVdd power signal is provided on the 604e to provide power to the clock generation phase-locked loop. To ensure stability of the internal clock, the power supplied to the AVdd input signal should be ltered using a circuit similar to the one shown in Figure 11. The circuit should be placed as close as possible to the AVdd pin to ensure it lters out as much noise as possible.
AVdd 0.1 F
(1.8 V Nom.)
PR
GND
Figure 11. PLL Power Supply Filter Circuit
1.8.4 Decoupling Recommendations
Due to the 604eOs large address and data buses, and high operating frequencies, the 604e can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the 604e system, and the 604e itself requires a clean, tightly regulated source of power. Therefore, it is strongly recommended that the system designer place at least one decoupling capacitor with a low ESR (effective series resistance) rating at each Vdd and OVdd pin of the 604e. These capacitors should range in value from 220 pF to 10 mF to provide both high- and low-frequency ltering, and should be placed as close as possible to their associated Vdd pin. Surface-mount tantalum or ceramic devices are preferred. It is also recommended that these decoupling capacitors receive their power from Vdd and GND power planes in the PCB, utilizing short traces to minimize inductance in the traces. Power and ground connections must be made to all external Vdd and GND pins of the 604e.
1.8.5 Connection Recommendations
To ensure reliable operation, it is recommended to connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to Vdd. Unused active high inputs should be connected to GND.
PID9q-604e Hardware Specifications PRELIMINARYNSUBJECT TO CHANGE WITHOUT NOTICE
23
1.8.6 Thermal Management Information
This section provides thermal management information for the ceramic ball grid array (CBGA) package for air-cooled applications. Proper thermal control design is primarily dependent upon the system-level designNthe heat sink, airow and thermal interface material. To reduce the die-junction temperature, heat sinks may be attached to the package by several methodsNadhesive, spring clip to holes in the printedcircuit board or package, and mounting clip and screw assembly; see Figure 12. This spring force should not exceed 5.5 pounds of force.
CBGA Package
Heat Sink
Heat Sink Clip
Adhesive or Thermal Interface Material
EL
IM
Printed-Circuit Board Option
Figure 12. Package Exploded Cross-Sectional View with Several Heat Sink Options
The board designer can choose between several types of heat sinks to place on the 604e. There are several commercially-available heat sinks for the 604e provided by the following vendors: Thermalloy 2021 W. Valley View Lane P.O. Box 810839 Dallas, TX 75731 214-243-4321
International Electronic Research Corporation (IERC) 135 W. Magnolia Blvd. Burbank, CA 91502 818-842-7277 Aavid Engineering One Kool Path Laconic, NH 03247-0440 Wakeeld Engineering 60 Audubon Rd. Wakeeld, MA 01880 603-528-3400
PR
Ultimately, the nal selection of an appropriate heat sink for the 604e depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost.
24
PID9q-604e Hardware Specifications PRELIMINARYNSUBJECT TO CHANGE WITHOUT NOTICE
IN A RY
617-245-5900
1.8.6.1 Internal Package Conduction Resistance
For the exposed-die packaging technology, shown in Table 14, the intrinsic conduction thermal resistance paths are as follows: The die junction-to-case thermal resistance The die junction-to-lead thermal resistance
Table 14. Package Thermal Resistance
Thermal Metric Junction-to-top of die thermal resistance CBGA
Junction-to-lead (ball) thermal resistance
Figure 13 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board.
External Resistance Radiation Convection
Heat Sink Internal Resistance
IM
Radiation
EL
PR
Printed-Circuit Board
External Resistance
(Note the internal versus external package resistance)
Figure 13. C4 Package with Heat Sink Mounted to a Printed-Circuit Board
Heat generated on the active side (ball) of the chip is conducted through the silicon, then through the heat sink attach material (or thermal interface material), and nally to the heat sink where it is removed by forced-air convection. Since the silicon thermal resistance is quite small, for a rst-order analysis, the temperature drop in the silicon may be neglected. Thus, the heat sink attach material and the heat sink conduction/convective thermal resistances are the dominant terms. The following section provides a thermal management example for the 604e using one of the commercially available heat sinks.
PID9q-604e Hardware Specifications PRELIMINARYNSUBJECT TO CHANGE WITHOUT NOTICE
IN A RY
2.2 C/W Die/Package Die Junction Package/Leads Convection
0.03 C/W
Thermal Interface Material
25
1.8.6.2 Thermal Management Example
For preliminary heat sink sizing, the die-junction temperature can be expressed as follows: Tj = Ta + Tr + (Rqjc +Ra + Rsa) * Q Where: Tj is the die-junction temperature Ta is the inlet cabinet ambient temperature Tr is the air temperature rise within the system cabinet Rqjc is the die-junction-to-top of die thermal resistance of the device Ra is the thermal resistance of the thermal interface material (thermal grease or thermal compound) Rsa is the heat sink-to-ambient thermal resistance Q is the power consumed by the device Typical die-junction temperatures (Tj) should be maintained less than 105 C. The temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air temperature rise within the computer cabinet. A computer cabinet inlet-air temperature (Ta) may range from 30 to 40 C. The air temperature rise within a cabinet (Tr) may be in the range of 5 to 10 C. The thermal resistance of the interface material (Ra) is typically about 1 C/W. Assuming a Ta of 30 C, a Tr of 5 C, and a power consumption (Q) of 7.5 watts, the following expression for Tj is obtained: Junction temperature: Tj = 30 C + 5 C + (0.03 C/W + 1.0 C/W + Rsa) * 7.5 W
8
PR
0 0.5 1 1.5
EL
For a Thermalloy heat sink #2333B, the heat sink-to-ambient thermal resistance (Rsa) versus airow velocity is shown in Figure 14.
7 Heat Sink Thermal Resistance (1/4C/W)
6
5
4
3
2
1 2 2.5 3 3.5 Approach Air Velocity (m/s)
Figure 14. Thermalloy #2328B Heat Sink-to-Ambient Thermal Resistance Versus Airflow Velocity
26
PID9q-604e Hardware Specifications PRELIMINARYNSUBJECT TO CHANGE WITHOUT NOTICE
IM
Thermalloy #2328B Pin-fin Heat Sink (25 x28 x 15 mm)
IN A RY
Assuming an air velocity of 0.5 m/s, we have an effective Rsa of 5 C/W, thus Tj = 30 C + 5 C + (0.03 C/W + 1.0 C/W + 5 C/W) * 7.5 W, resulting in a junction temperature of approximately 81 C which is just below the maximum operating temperature of the part. To ensure maximum reliability, it is desirable to operate the 604e well within its operating temperature range. Thus, to keep a 7.5 W 604e within its proper operating range, an air velocity greater than 0.5 m/s should be used with the Thermalloy #2333B pin-n heat sink. Other heat sinks offered by Thermalloy, Aavid, Wakeeld, and IERC offer different heat sink-to-ambient thermal resistances, and may or may not need air ow. It is necessary to perform an analysis as done above to select the desired heat sink. Though the junction-to-ambient and the heat sink-to-ambient thermal resistances are commonly used to compare the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat ow. The nal chip-junction operating temperature is not only a function of the component-level thermal resistance, but the system-level design and its operating conditions. In addition to the component's power consumption, a number of factors affect the nal operating die-junction temperature. These factors might include airow, board population (local heat ux of adjacent components), heat sink efciency, heat sink attach, next-level interconnect technology, system air temperature rise, etc. Due to the complexity and the many variations of system-level boundary conditions for today's microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection and conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models for the board as well as system-level designs. To expedite system-level thermal analysis, several OcompactO thermal-package models are available within FLOTHERM. These are available upon request.
This section provides the part numbering nomenclature for the 604e. Note that the individual part numbers correspond to a specic combination of 604e internal/bus frequencies, which must be observed to ensure proper operation of the device. For available frequency combinations, contact your local Motorola or IBM sales ofce. In addition to the processor frequency and bus ratio, the part numbering scheme also consists of a part modier. The part modier indicates the enhancement in the part from the original production design. Each part number also contains a revision code. This refers to the die mask revision number and is specied in the part numbering scheme for identication purposes only.
PID9q-604e Hardware Specifications PRELIMINARYNSUBJECT TO CHANGE WITHOUT NOTICE
PR
1.9 Ordering Information
EL
IM
IN A RY
27
1.9.1 Motorola Part Number Key
Figure 15 provides the Motorola part numbering nomenclature for the 604e.
MPC 604 _ XX XXX X X
Revision Level (Contact Local Motorola Sales Office) Product Code Part Identifier Part Modifier ( = Enhanced and Lower Voltage N604e) Bus Divider (Contact Local Motorola Sales Office for Available Bus Ratios)
IN A RY
Processor Frequency Package (RX = BGA)
Figure 15. Motorola Part Number Key
1.9.2 IBM Part Number Information
Contact your local IBM sales ofce for 604e part number and availability information.
28
PR
PID9q-604e Hardware Specifications PRELIMINARYNSUBJECT TO CHANGE WITHOUT NOTICE
EL
IM
Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors. There are no express or implied copyright or patent licenses granted hereunder by Motorola or IBM to design, modify the design of, or fabricate circuits based on the information in this document. The PowerPC 604e microprocessor embodies the intellectual property of Motorola and of IBM. However, neither Motorola nor IBM assumes any responsibility or liability as to any aspects of the performance, operation, or other attributes of the microprocessor as marketed by the other party or by any third party. Neither Motorola nor IBM is to be considered an agent or representative of the other party or any third party, and neither has assumed, created, or granted hereby any right or authority to the other, or to any third party, to assume or create any express or implied obligations on its behalf. Information such as errata sheets and data sheets, as well as sales terms and conditions such as prices, schedules, and support, for the product may vary as between parties selling the product. Accordingly, customers wishing to learn more information about the products as marketed by a given party should contact that party. Both Motorola and IBM reserve the right to modify this document and/or any of the products as described herein without further notice. NOTHING IN THIS DOCUMENT, NOR IN ANY OF THE ERRATA SHEETS, DATA SHEETS, AND OTHER SUPPORTING DOCUMENTATION, SHALL BE INTERPRETED AS THE CONVEYANCE BY MOTOROLA OR IBM OF AN EXPRESS WARRANTY OF ANY KIND OR IMPLIED WARRANTY, REPRESENTATION, OR GUARANTEE REGARDING THE MERCHANTABILITY OR FITNESS OF THE PRODUCTS FOR ANY PARTICULAR PURPOSE. Neither Motorola nor IBM assumes any liability or obligation for damages of any kind arising out of the application or use of these materials. Any warranty or other obligations as to the products described herein shall be undertaken solely by the marketing party to the customer, under a separate sale agreement between the marketing party and the customer. In the absence of such an agreement, no liability is assumed by Motorola, IBM, or the marketing party for any damages, actual or otherwise. OTypicalO parameters can and do vary in different applications. All operating parameters, including OTypicals,O must be validated for each customer application by customerOs technical experts. Neither Motorola nor IBM convey any license under their respective intellectual property rights nor the rights of others. Neither Motorola nor IBM makes any claim, warranty, or representation, express or implied, that the products described in this document are designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the product could create a situation where personal injury or death may occur. Should customer purchase or use the products for any such unintended or unauthorized application, customer shall indemnify and hold Motorola and IBM and their respective ofcers, employees, subsidiaries, afliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorneyOs fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola or IBM was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks and Mfax is a trademark of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Afrmative Action Employer.
IBM, the IBM logo, and IBM Microelectronics are trademarks of International Business Machines Corporation. The PowerPC name is a registered trademark and the PowerPC logotype, PowerPC 604 and PowerPC 604e are trademarks of International Business Machines Corporation, used by Motorola under license from International Business Machines Corporation. International Business Machines Corporation is an Equal Opportunity/Afrmative Action Employer. International Business Machines Corporation: IBM Microelectronics Division, 1580 Route 52, Bldg. 504, Hopewell Junction, NY 12533-6531; Tel. (800) PowerPC World Wide Web Address: http://www.chips.ibm.com/products/ppc http://www.ibm.com Motorola Literature Distribution Centers: USA/EUROPE: Motorola Literature Distribution; P.O. Box 5405; Denver, Colorado 80217; Tel.: 1-800-441-2447 or (303) 675-2140 JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan; Tel.: 81-3-3521-8315 ASIA/PACIFC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong; Tel.: 852-26629298
Technical Information: Motorola Inc. SPS Customer Support Center; (800) 521-6274; electronic mail address: crc@wmkmail.sps.mot.com. Document Comments: FAX (512) 891-2638, Attn: RISC Applications Engineering.

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