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| G522-0296-01 (IBM Order Number) MPC604E9VEC/D (Motorola Order Number) 5/97 REV 1 TM Advance Information PID9v-604e Hardware Specifications The PowerPC 604e microprocessor is an implementation of the PowerPCTM family of reduced instruction set computing (RISC) microprocessors. In this document, the term `604' is used as an abbreviation for `PowerPC 604TM microprocessor' and the term `604e' is used as an abbreviation for `PowerPC 604e microprocessor'. The PowerPC 604e microprocessors are available from Motorola as MPC604e and from IBM as PPC604e. This document contains pertinent physical characteristics of the 604e. This document contains the following topics: Topic Page PID9v-604e Hardware Specifications Section 1.1, "Overview" Section 1.2, "Features" Section 1.3, "General Parameters" Section 1.4, "Electrical and Thermal Characteristics" Section 1.5, "PowerPC 604e Microprocessor Pin Assignments" Section 1.6, "PowerPC 604e Microprocessor Pinout Listings" Section 1.7, "PowerPC 604e Microprocessor Package Description" Section 1.8, "System Design Information" Section 1.9, "Ordering Information PR EL IM PowerPC 604eTM RISC Microprocessor Family: IN A RY 2 2 5 6 17 18 20 22 29 To locate any published errata or updates for this document, refer to the website at http://www.mot.com/ PowerPC/ or at http://www.chips.ibm.com/products/ppc. The PowerPC name, the PowerPC logotype, PowerPC 604, and PowerPC 604e are trademarks of International Business Machines Corporation, used by Motorola under license from International Business Machines Corporation. This document contains information on a new product under development by Motorola and IBM. Motorola and IBM reserve the right to change or discontinue this product without notice. (c) Motorola Inc., 1997. All rights reserved. Portions hereof (c) International Business Machines Corporation, 1991-1997. All rights reserved. 1.1 Overview The 604e is an implementation of the PowerPC family of reduced instruction set computing (RISC) microprocessors. The 604e implements the PowerPC architecture as it is specified for 32-bit addressing, which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits, and floatingpoint data types of 32 and 64 bits (single-precision and double-precision). For 64-bit PowerPC implementations, the PowerPC architecture provides additional 64-bit integer data types, 64-bit addressing, and related features. The 604e is a superscalar processor capable of issuing four instructions simultaneously. As many as seven instructions can finish execution in parallel. The 604e has seven execution units that can operate in parallel--a floating-point unit (FPU), a branch processing unit (BPU), a condition register unit (CRU), a load/store unit (LSU), and three integer units (IUs)--two single-cycle integer units (SCIUs) and one multiple-cycle integer unit (MCIU). The 604e uses an advanced, 2.5-V CMOS process technology and is fully compatible with TTL devices. 1.2 Features * This section summarizes features of the 604e's implementation of the PowerPC architecture. Major features of the 604e are as follows: High-performance, superscalar microprocessor -- As many as four instructions can be issued per clock -- As many as seven instructions can start executing per clock (including three integer instructions) -- Single-clock-cycle execution for most instructions * Seven independent execution units and two register files -- BPU featuring dynamic branch prediction - Two-entry reservation station - Out-of-order execution through two branches - Shares dispatch bus with CRU 2 PR The 604e has a 64-bit external data bus and a 32-bit address bus. The 604e interface protocol allows multiple masters to compete for system resources through a central external arbiter. Additionally, on-chip snooping logic maintains data cache coherency for multiprocessor applications. The 604e supports single-beat and burst data transfers for memory accesses and memory-mapped I/O accesses. PID9v-604e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL The 604e has separate memory management units (MMUs) and separate 32-Kbyte on-chip caches for instructions and data. The 604e implements two 128-entry, two-way set associative translation lookaside buffers (TLBs), one for instructions and one for data, and provides support for demand-paged virtual memory address translation and variable-sized block translation. The TLBs and the cache use least-recently used (LRU) replacement algorithms. IM IN A This parallel design, combined with the PowerPC architecture's specification of uniform instructions that allows for rapid execution times, yields high efficiency and throughput. The 604e's rename buffers, reservation stations, dynamic branch prediction, and completion unit increase instruction throughput, guarantee in-order completion, and ensure a precise exception model. (Note that the PowerPC architecture specification refers to all exceptions as interrupts.) RY - 64-entry fully-associative branch target address cache (BTAC). In the 604e, the BTAC can be disabled and invalidated. - 512-entry branch history table (BHT) with two bits per entry for four levels of prediction-- not-taken, strongly not-taken, taken, strongly taken -- Condition register logical unit - Two-entry reservation station - Shares dispatch bus with BPU -- Two single-cycle IUs (SCIUs) and one multiple-cycle IU (MCIU) - Instructions that execute in the SCIU take one cycle to execute; most instructions that execute in the MCIU take multiple cycles to execute. - Each SCIU has a two-entry reservation station to minimize stalls - The MCIU has a single-entry reservation station and provides early exit (three cycles) for 16- x 32-bit and overflow operations. - Thirty-two GPRs for integer operands -- Three-stage floating-point unit (FPU) - Fully IEEE 754-1985-compliant FPU for both single- and double-precision operations - Fully pipelined, single-pass double-precision design - Hardware support for denormalized numbers - Thirty-two 64-bit FPRs for single- or double-precision operands -- Load/store unit (LSU) - Two-entry reservation station to minimize stalls - Single-cycle, pipelined cache access - Dedicated adder performs effective address (EA) calculations - Performs alignment and precision conversion for floating-point data - Performs alignment and sign extension for integer data - Four-entry finish load queue (FLQ) provides load miss buffering - Six-entry store queue - Supports both big- and little-endian modes * Rename buffers -- Twelve GPR rename buffers -- Eight FPR rename buffers -- Eight condition register (CR) rename buffers * Completion unit -- The completion unit retires an instruction from the 16-entry reorder buffer when all instructions ahead of it have been completed and the instruction has finished execution. -- Guarantees sequential programming model (precise exception model) -- Monitors all dispatched instructions and retires them in order PID9v-604e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE PR EL - Two-entry reservation station to minimize stalls IM - Supports non-IEEE mode for time-critical operations IN A RY 3 -- Tracks unresolved branches and flushes executed, dispatched, and fetched instructions if branch is mispredicted -- Retires as many as four instructions per clock * Separate on-chip instruction and data caches (Harvard architecture) -- 32-Kbyte, four-way set-associative instruction and data caches -- LRU replacement algorithm -- 32-byte (eight-word) cache block size -- Physically indexed/physical tags (Note that the PowerPC architecture refers to physical address space as real address space.) -- Cache write-back or write-through operation programmable on a per page or per block basis -- Instruction cache can provide four instructions per clock; data cache can provide two words per clock -- Caches can be disabled in software -- Caches can be locked -- Parity checking performed on both caches -- Data cache coherency (MESI) maintained in hardware -- Instruction cache coherency maintained in software * Separate memory management units (MMUs) for instructions and data -- Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte segment size -- Both TLBs are 128-entry and two-way set associative -- TLBs are hardware reloadable (that is, the page table search is performed in hardware) -- Separate IBATs and DBATs (four each) also defined as SPRs -- Separate instruction and data translation lookaside buffers (TLBs) -- LRU replacement algorithm -- 52-bit virtual address; 32-bit physical address * Bus interface features -- Selectable processor-to-bus clock frequency ratios of 3:2, 2:1, 5:2, 3:1, 7:2, 4:1, 5:1, and 6:1 -- A 64-bit split-transaction external data bus with burst transfers -- Support for address pipelining and limited out-of-order bus transactions -- Four burst write queues--three for cache copyback operations and one for snoop push operations -- Two single-beat write queues -- Additional signals and signal redefinition for direct-store operations -- Provides a data streaming mode that allows consecutive burst read data transfers to occur without intervening dead cycles. This mode also disables data retry operations. 4 PR PID9v-604e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL -- Data cache line-fill buffer forwarding. In the 604 only the critical double word of the cache block was made available to the requesting unit at the time it was burst into the line-fill buffer. Subsequent data was unavailable until the cache block was filled. On the 604e, subsequent data is also made available as it arrives in the line-fill buffer. IM -- Secondary data cache support provided IN A RY -- No-DRTRY mode eliminates the DRTRY signal from the qualified bus grant and allows read operations. This improves performance on read operations for systems that do not use the DRTRY signal. No-DRTRY mode makes read data available to the processor one bus clock cycle sooner than if normal mode is used. * Multiprocessing support features include the following: -- Hardware enforced, four-state cache coherency protocol (MESI) for data cache. Bits are provided in the instruction cache to indicate only whether a cache block is valid or invalid. -- Separate port into data cache tags for bus snooping -- Load/store with reservation instruction pair for atomic memory references, semaphores, and other multiprocessor operations * Power management -- DOZE mode suspends instruction execution while allowing cache snooping -- Operating voltage of 2.5 0.125 V * * Performance monitor can be used to help in debugging system designs and improving software efficiency, especially in multiprocessor systems. 1.3 General Parameters Technology Die size The following list provides a summary of the general parameters of the 604e: 0.35 m CMOS, five-layer metal 12.9 mm x 11.7 mm (148 mm2) 5.1 million Fully-static 255-lead ceramic ball grid array (CBGA) 2.5 V 5% V dc 3.3 V 5% V dc Transistor count Logic design Package Core power supply I/O power supply PID9v-604e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE PR EL IM In-system testability and debugging features through JTAG boundary-scan capability IN A -- NAP mode suspends all internal clocks except those required for decrementer, time base, and interrupt logic RY 5 1.4 Electrical and Thermal Characteristics This section provides both the AC and DC electrical specifications and thermal characteristics for the 604e. 1.4.1 DC Electrical Characteristics The tables in this section describe the 604e DC electrical characteristics. Table 1 provides the absolute maximum ratings. Table 1. Absolute Maximum Ratings Core supply voltage PLL supply voltage I/O supply voltage Input voltage Storage temperature range Notes: Vdd AVdd OVdd Vin RY -0.3 to 3.6 -0.3 to 5.5 -55 to 150 0 to 105 Characteristic Symbol Value Unit V V V V C -0.3 to 2.75 -0.3 to 2.75 2. Caution: Vin must not exceed OVdd by more than 2.5 V at all times including during power-on reset. 3. Caution: OVdd must not exceed Vdd/AVdd by more than 1.2 V at any time including during power-on reset. 4. Caution: Vdd/AVdd must not exceed OVdd by more than 0.4 V at any time including during power-on reset. PR Table 2 provides the recommended operating conditions for the 604e. Table 2. Recommended Operating Conditions Symbol Vdd AVdd OVdd Vin Tj Value 2.375 to 2.625 2.375 to 2.625 3.135 to 3.465 GND to 5.5 Unit V V V V C Characteristic Core supply voltage PLL supply voltage I/O supply voltage Input voltage Die-junction temperature Note: These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. 6 PID9v-604e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM 1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. IN A Tstg Table 3 provides the thermal characteristics for the 604e. Table 3. Thermal Characteristics Characteristic CBGA package thermal resistance, die junction-to-top-of-die (typical) CBGA package thermal resistance, die junction-to-ball (typical) Symbol JC JB Value 0.1 3.8 Rating C/W C/W Note: Refer to Section 1.8, "System Design Information," for more details about thermal management. Table 4 provides the DC electrical characteristics for the 604e. Table 4. DC Electrical Specifications Vdd = AVdd = 2.5 5% V dc, OVdd = 3.3 5% V dc, GND = 0 V dc, 0 Tj 105 C Characteristic Input high voltage (all inputs except SYSCLK) Input low voltage (all inputs except SYSCLK) SYSCLK input high voltage SYSCLK input low voltage Input leakage current, Vin = 3.465 V1 Vin = 5.5 V1 IN A Symbol VIH VIL CVIH CVIL Iin Iin ITSI ITSI VOH VOL Cin Cin RY Min 2.0 GND 2.4 GND -- -- -- -- 2.4 -- -- -- 5.5 0.8 5.5 0.4 10 245 10 245 -- 0.4 10.0 15.0 Max V V V V A A A A V V pF pF Unit Hi-Z (off-state) leakage current, Vin = 3.465 V1 Output high voltage, IOH = -9 mA Output low voltage, IOL = 9 mA Capacitance, Vin = 0 V, f = 1 MHz2 (excludes TS, ABB, DBB, and ARTRY) Capacitance, Vin = 0 V, f = 1 MHz2 (for TS, ABB, DBB, and ARTRY) Notes: 1. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK) and JTAG signals. 2. Capacitance values are guaranteed by design and characterization, and are not tested. PID9v-604e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE PR EL Vin = 5.5 V1 IM 7 Table 5 provides the power consumption for the 604e. Table 5. Power Consumption Processor Core Frequency CPU Clock: SYSCLK 166 MHz 180 MHz 200 MHz 225 MHz 233 MHz Unit Full-On Mode Typical Maximum Doze Mode Typical Maximum Nap Mode Typical Maximum 0.8 1.1 0.8 1.1 1.1 1.2 1.1 1.2 1.1 1.3 12.4 13.3 13.5 14.3 14.5 15.7 15.9 17.4 16.7 18.0 W W RY 1.1 1.3 0.9 1.1 1.2 1.3 W W IN A 0.9 1.1 0.9 1.1 W W 2. Typical power is an average value measured at Vdd = AVdd = 2.5 V, OVdd = 3.3 V, Ta = 25 C in a system executing typical applications and benchmark sequences. Typical power numbers should be used in planning for proper thermal management. 1.4.2 AC Electrical Characteristics This section provides the AC electrical characteristics for the 604e. After fabrication, parts are sorted by maximum processor core frequency as shown in Section 1.4.2.1, "Clock AC Specifications," and tested for conformance to the AC specifications for that frequency. These specifications are for 166.67, 180, 200, 225, and 233 MHz processor core frequencies. The processor core frequency is determined by the bus (SYSCLK) frequency and the settings of the PLL_CFG[0-3] signals. Parts are sold by maximum processor core frequency; see Section 1.9, "Ordering Information." 8 PR 3. Maximum power is measured at Vdd = AVdd = 2.625 V, OVdd = 3.465 V, Tj = 0 C using a worst-case instruction mix. These values should be used for power supply design. PID9v-604e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL Notes: 1. These values apply for all valid PLL_CFG[0-3] settings and do not include output driver power (OVdd) or analog supply power (AVdd). OVdd power is system dependent but is typically 10% of Vdd. Worstcase AVdd = 15 mW. IM 1.4.2.1 Clock AC Specifications Table 6 provides the clock AC timing specifications as defined in Figure 1. Table 6. Clock AC Timing Specifications Vdd = AVdd = 2.5 5% V dc, OVdd = 3.3 5% V dc, GND = 0 V dc, 0 Tj 105 C Num Characteristic 166.67 MHz Min Max Min 90 180 25 15 1.0 40 180 MHz Max 180 360 66 40 2.0 60 Min 100 200 25 15 200 MHz Max 200 400 66 40 Min 112 225 MHz Max 225 Min 116 233 MHz Max 233 466 75 40 2.0 60 Unit Notes VCO frequency SYSCLK (bus) frequency 1 2, 3 4 SYSCLK cycle time 166 25 15 33 66 40 2.0 60 RY 225 450 233 25 75 25 13 40 2.0 60 13 1.0 40 1.0 40 150 100 Processor frequency 83.3 166.7 MHz 1 MHz 1 MHz 1, 6 ns ns % 2 3 SYSCLK rise and 1.0 fall time SYSCLK duty cycle measured at 1.4 V SYSCLK jitter 604e internal PLL-relock time 40 IM -- 150 100 -- EL 150 100 IN A 1.0 40 2.0 60 -- -- 150 100 150 100 ps s 4 3, 5 -- -- 2. Rise and fall times for the SYSCLK input are measured from 0.4 V to 2.4 V. 3. Timing is guaranteed by design and characterization, and is not tested. 4. The total input jitter (short term and long term combined) must be under 150 ps to guarantee the input and output timing shown in Section 1.4.2.2, "Input AC Specifications" and Section 1.4.2.3, "Output AC Specifications." 5. PLL-relock time is the maximum time required for PLL lock after a stable Vdd, OVdd, AVdd, and SYSCLK are reached during the power-on reset sequence. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time (100 s) during the power-on reset sequence. 6. AC timing specifications are tested up to the maximum SYSCLK frequency shown here. However, it is theoretically possible to attain higher SYSCLK frequencies, if allowed for by system design or by using 604e Fast Out mode (see Table 11 for details). PID9v-604e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE PR Notes: 1. Caution: The SYSCLK frequency and PLL_CFG[0-3] settings must be chosen such that the resulting SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0-3] signal description in Section 1.8, "System Design Information," for valid PLL_CFG[0-3] settings. 9 Figure 1 provides the SYSCLK input timing diagram. 1 4 4 CVih VM CVil 2 3 SYSCLK Figure 1. SYSCLK Input Timing Diagram Table 7 provides the input AC timing specifications as defined in Figure 2 and Figure 3 for 604e processors operating at 166.67, 180, 200, 225, and 233 MHz core frequencies. Table 7. Input AC Timing Specifications, 166.67-233 MHz1 IM Vdd = AVdd = 2.5 5% V dc, OVdd = 3.3 5% V dc, GND = 0 V dc, 0 Tj 105 C IN A 166.67 MHz Min Max -- 2.25 0.5 8 * tsysclk 0 -- -- -- -- 1.4.2.2 Input AC Specifications Num Characteristic RY 180, 200, 225, and 233 MHz Min 3.25 Max -- ns 2 Unit Notes 2.0 0.5 8 * tsysclk 0 -- -- -- -- ns ns ns ns 3, 4, 5, 6 3, 4, 5, 6 2 VM = Midpoint Voltage (1.4 V) 7a 7b 8 9 10 All other inputs valid to SYSCLK (input setup) SYSCLK to all inputs invalid (input hold) Mode select input valid to HRESET (input setup for DRTRY) HRESET to mode select input invalid (input hold for DRTRY) Notes: 1. Input specifications are measured from the TTL level (0.8 or 2.0 V) of the signal in question to the 1.4 V of the rising edge of the input SYSCLK. Input and output timings are measured at the pin (see Figure 2). 2. All other input signals include the following signals--all inputs except ARTRY, SHD, ABB, TS, XATS, AACK, BG, DRTRY, TA, DBG, DBB, DBWO, DBDIS, TEA, and JTAG inputs. 3. The setup and hold time is with respect to the rising edge of HRESET (see Figure 3). 4. tsysclk is the period of the external clock (SYSCLK) in nanoseconds. 5. These values are guaranteed by design, and are not tested. 6. Note this is for configuration of the fast-L2 mode and the no-DRTRY mode. 10 PR ARTRY, SHD, ABB, TS, XATS, AACK, BG, 3.5 DRTRY, TA, DBG, DBB, TEA, DBDIS, and DBWO valid to SYSCLK (input setup) PID9v-604e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL Figure 2 provides the input timing diagram for the 604e. \ SYSCLK VM 8 7 ALL INPUTS VM = Midpoint Voltage (1.4 V) Figure 2. Input Timing Diagram HRESET IM VM = Midpoint Voltage (1.4 V) 9 DRTRY 1.4.2.3 Output AC Specifications The output specifications of the 604e for both driving high and driving low depend on the capacitive loading on each output and the drive capability enabled for that output. Additionally, the timing specifications for outputs driving low also depend on the voltage swing required to drive to 0.8 V (either 5.5 V to 0.8 V or 3.6 V to 0.8 V). Table 8 provides the output AC timing specifications for a 50 pF load. In order to derive the actual timing specifications for a given set of conditions, it is recommended that IBIS simulation models be used. Contact the local Motorola or IBM sales office for information on the availability of these models. The 604e adds a Fast Out output mode which will allow for increased system bus frequencies. Table 8 provides the output AC timing specifications for the 604e (shown in Figure 4) operating in 604 Compatibility mode and Fast Out mode. 604e Fast Out mode is selected by driving the L2_TSTCLK pin to GND during assertion of HRESET. When Fast Out mode is enabled, the output valid and output hold times are reduced. PID9v-604e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE PR EL Figure 3. Mode Select Input Timing Diagram IN A VM 10 Figure 3 provides the mode select input timing diagram for the 604e. RY 11 Table 8 provides the output AC timing specifications for 166.67, 180, 200, 225, and 233 MHz processors. Table 8. Output AC Timing Specifications1 Vdd = AVdd = 2.5 5% V dc, OVdd = 3.3 5% V dc, GND = 0 V dc, CL = 50 pF, 0 Tj 105 C, Drive mode [01]7 166.67 MHz Num Characteristic Min 11 12a SYSCLK to output driven (output enable time) 0.75 Max -- 6.75 Fast Out Min/Max -- 5.75 180, 200, 225, and 233 MHz Min 0.75 -- -- 6.5 Max Fast Out Min/Max -- 5.5 Unit Notes ns ns 2, 5 3, 5 SYSCLK to TS, XATS, -- ARTRY, SHD, ABB and DBB output valid (for 5.5 V to 0.8 V) SYSCLK to TS, XATS, -- ARTRY, SHD, ABB and DBB output valid (for 3.6 V to 0.8 V) SYSCLK to all other signals -- output valid (for 5.5 V to 0.8 V) SYSCLK to all other signals -- output valid (for 3.6 V to 0.8 V) SYSCLK to output invalid (output hold) 12b 6.25 5.25 -- RY 5.5 7.5 6.5 -- 6.25 6.25 1.0* tsysclk 6.25 -- -- 1.5* tsysclk 2.0* tsysclk 4.5 ns 5 13a 13b 14 15 7.75 7.25 -- IN A 6.75 -- 6.25 -- 0.0 0.0 -- 5.75 5.75 -- -- 5.75 -- -- 0.5* tsysclk +0.75 -- -- 1.0 1.0 6.5 5.5 0.0 5.25 ns ns ns ns 3, 5 5 2, 5 5 0.5 EL -- SYSCLK to output high -- impedance (all signals except ARTRY, SHD, ABB, DBB, TS, and XATS) IM 6.75 6.75 16 17 SYSCLK to ABB and DBB high impedance after precharge PR SYSCLK to output high impedance TS, XATS 5.25 1.0* tsysclk ns ns 5 4 -- 1.0* 1.0* tsysclk tsysclk 6.75 18 SYSCLK to ARTRY and SHD high impedance before precharge -- 5.25 ns 5 19 SYSCLK to ARTRY, and SHD 0.5* -- precharge enable tsysclk +0.75 Maximum delay to ARTRY and SHD precharge SYSCLK to ARTRY and SHD high impedance after precharge -- -- ns 4 20 21 1.5* tsysclk 1.5* tsysclk 2.0* 2.0* tsysclk tsysclk 1.5* tsysclk 2.0* tsysclk ns ns 4 4 Rise time (ARTRY, SHD, ABB, 1.0 DBB, TS, and XATS) 1.0 ns 6 12 PID9v-604e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Table 8. Output AC Timing Specifications1 (Continued) Vdd = AVdd = 2.5 5% V dc, OVdd = 3.3 5% V dc, GND = 0 V dc, CL = 50 pF, 0 Tj 105 C, Drive mode [01]7 166.67 MHz Num Characteristic Min Rise time (all signals except ARTRY, SHD, ABB, DBB, TS, and XATS) Fall time (ARTRY, SHD, ABB, DBB, TS, and XATS) Fall time (all signals except ARTRY, SHD, ABB, DBB, TS, and XATS) 1.0 Max Fast Out Min/Max 1.0 180, 200, 225, and 233 MHz Min 1.0 Max Fast Out Min/Max 1.0 Unit Notes ns 6 1.0 1.0 1.0 RY 1.0 1.0 1.0 1.0 1.0 ns ns 6 6 Notes: 1. All output specifications are measured from the 1.4 V of the rising edge of SYSCLK to the TTL level (0.8 V or 2.0 V) of the signal in question. Both input and output timings are measured at the pin (see Figure 4). 2. This minimum parameter assumes CL = 0 pF. 4. tsysclk is the period of the external bus clock (SYSCLK) in nanoseconds (ns). When the unit is given as tsysclk the numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question. 5. Fast Out mode (L2_TSTCLK = GND) improves output valid timing and reduces output hold times. The 604e powers up in Compatibility mode in a 604 system (L2_TSTCLK = OVdd). 6. These specifications are nominal values. PID9v-604e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE PR 7. These timing specifications are tested with drive mode signals configured with DRVMODE0 = low, DRVMODE1 = high. EL IM 3. SYSCLK to output valid (5.5 V to 0.8 V) includes the extra delay associated with discharging the external voltage from 5.5 V to 0.8 V instead of from 3.6 V to 0.8 V (5-V CMOS levels instead of 3.3-V CMOS levels). IN A 13 Figure 4 provides the output timing diagram for the 604e. VM 13 14 11 15 SYSCLK VM VM ALL OUTPUTS (Except TS, ABB, DBB, ARTRY, XATS, SHD) 12 12 14 TS, XATS 17 ABB, DBB IN A IM EL 20 19 18 ARTRY, SHD VM = Midpoint Voltage (1.4 V) 14 PR Figure 4. PowerPC 604e Microprocessor Output Timing Diagram PID9v-604e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE RY 16 21 1.4.3 JTAG AC Timing Specifications Table 9 provides the JTAG AC timing specifications as illustrated in Figure 5, Figure 6, Figure 7, and Figure 8. Table 9. JTAG AC Timing Specifications (Independent of SYSCLK) Vdd = AVdd = 2.5 5% V dc, OVdd = 3.3 5%, GND = 0 V dc, CL = 50 pF, 0 Tj 105 C Num Characteristic TCK frequency of operation 0 Min 16 -- Max Unit MHz ns ns Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 TCK cycle time TCK clock pulse width measured at 1.5 V TCK rise and fall times TRST setup time to TCK rising edge TRST assert time Boundary-scan input data setup time Boundary-scan input data hold time TCK to output data valid 62.5 25 0 13 IN A 40 0 27 4 3 0 25 4 3 1 2 VM RY -- 3 -- -- -- -- 25 24 -- -- 24 15 2 VM ns ns 1 ns ns ns ns ns ns ns ns ns 2 2 3 3 TMS, TDI data setup time TMS, TDI data hold time Notes: 1. TRST is an asynchronous signal. The setup time is for test purposes only. 2. Non-test signal input timing with respect to TCK. 3. Non-test signal output timing with respect to TCK. Figure 5 provides the JTAG clock input timing diagram. PR TCK to TDO data valid TCK to TDO high impedance EL TCK to output high impedance IM 3 TCK 3 VM VM = Midpoint Voltage (1.4 V) Figure 5. Clock Input Timing Diagram PID9v-604e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE 15 Figure 6 provides the TRST timing diagram. TCK 4 TRST 5 Figure 7 provides the boundary-scan timing diagram. IN A 8 TCK Data Inputs Data Outputs IM 9 Data Outputs EL 8 Output Data Valid Data Outputs Figure 8 provides the test access port timing diagram. TCK 10 11 TDI, TMS 12 PR Figure 7. Boundary-Scan Timing Diagram TDO 13 TDO 12 TDO Figure 8. Test Access Port Timing Diagram 16 PID9v-604e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE RY 6 7 Input Data Valid Output Data Valid Input Data Valid Output Data Valid Output Data Valid Figure 6. TRST Timing Diagram 1.5 PowerPC 604e Microprocessor Pin Assignments The following sections contain the pinout diagrams for the 604e. Note that the 604e is currently offered by Motorola and IBM in a ceramic ball grid array (CBGA) package. The IBM and Motorola CBGA packages have identical pinouts. Figure 9 (in part A) shows the pinout of the CBGA package as viewed from the top surface. Part B shows the side profile of the CBGA package to indicate the direction of the top surface view. Part A 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 A B C D E F G H J K L M N P PR R T Not to Scale Part B Substrate Assembly Encapsulant View Die Figure 9. Pinout of the CBGA Package as Viewed from the Top Surface PID9v-604e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL IM IN A 17 RY 1.6 PowerPC 604e Microprocessor Pinout Listings Table 10 provides the pinout listing for the 604e CBGA package. Table 10. Pinout Listing for the CBGA Package Signal Name A[0-31] Pin Number C16, E04, D13, F02, D14, G01, D15, E02, D16, D04, E13, GO2, E15, H01, E16, H02, F13, J01, F14, J02, F15, H03, F16, F04, G13, K01, G15, K02, H16, M01, J15, P01 L02 K04 C01, B04, B03, B02 A04 B07 J04 A10 L01 B06 E01 D08 A06 Active High I/O I/O ABB AP[0-3] APE ARRAY_WR 1 ARTRY AVDD BG BR CI CKSTP_IN CKSTP_OUT CLK_OUT CSE[0-1] DBB DBG DBDIS DBWO DH[0-31] RY IN A AACK Low Low High Input I/O I/O Output Input I/O -- Input Output Output Input Output Output Output I/O Input Input Input I/O Low Low Low -- Low Low Low Low Low -- PR EL D07 B01, B05 J14 IM High Low Low Low Low High N01 H15 G04 P14, T16, R15, T15, R13, R12, P11, N11, R11,T12, T11, R10, P09, N09, T10, R09, T09, P08, N08, R08, T08, N07, R07, T07, P06, N06, R06, T06, R05, N05, T05, T04 K13, K15, K16, L16, L15, L13, L14, M16, M15, M13, N16, N15, N13, N14, P16, P15, R16, R14, T14, N10, P13, N12, T13, P03, N03, N04, R03, T01, T02, P04, T03, R04 M02, L03, N02, L04, R01, P02, M04, R02 A05 G16 D05 C03 F01 DL[0-31] High I/O DP[0-7] DPE DRTRY DRVMOD0 2 DRVMOD1 2 GBL High Low Low Low High Low I/O Output Input Input Input I/O 18 PID9v-604e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE Table 10. Pinout Listing for the CBGA Package (Continued) Signal Name GND Pin Number C05, C12, E03, E06, E08, E09, E11, E14, F05, F07, F10, F12, G06, G08, G09, G11, H05, H07, H10, H12, J05, J07, J10, J12, K06, K08, K09, K11, L05, L07, L10, L12, M03, M06, M08, M09, M11, M14, P05, P12 B08 A07 B15 D11 D06 D12 B10 C13 Active -- -- I/O HALTED HRESET INT L1_TSTCLK 1 L2_INT L2_TSTCLK 1 LSSD_MODE 1 MCP OVDD PLL_CFG[0-3] RSRV RUN SHD SMI SRESET SYSCLK TA TBEN TBST TC[0-2] TCK TDI TDO TEA TMS TRST TS TSIZ[0-2] TT[0-4] High Low Output Input Input Input Input Input Input Input -- Input Output Input I/O Input Input Input Input Input I/O Output Input Input Output Input Input Input I/O I/O I/O IN A A08, B09, A09, D09 D01 C08 H04 A16 B14 IM C07, E05, E07, E10, E12, G03, G05, G12, G14, K03, K05, K12, K14, M05, M07, M10, M12, P07, P10 EL PR C09 H14 C02 A14 A02, A03, C06 C11 A11 A12 H13 B11 C10 J13 A13, D10, B12 B13, A15, B16, C14, C15 PID9v-604e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE RY Low Low High Low Low Low -- High Low High Low Low Low -- Low High Low High High High High Low High Low Low High High 19 Table 10. Pinout Listing for the CBGA Package (Continued) Signal Name WT VDD VOLTDETGND 3 XATS NC (No Connect) 3 Pin Number D02 F06, F08, F09, F11, G07, G10, H06, H08, H09, H11, J06, J08, J09, J11, K07, K10, L06, L08, L09, L11 F03 J16 C04, D03, J03 Active Low -- -- Low I/O Output -- -- I/O Notes: 1. These are test signals for factory use only and must be pulled up to OVdd for normal machine operation. 3. NC (no-connect) in the 604; internally tied to GND in the 604e CBGA package to indicate to the power supply that a low-voltage processor is present. 1.7.1 Package Parameters Package outline Interconnects Pitch PR The package parameters are as provided in the following list. The package type is 21 mm, 256-lead ceramic ball grid array (CBGA). 21 x 21 mm 255 1.27 mm (50 mil) 3.30 mm 0.89 mm (35 mil) Maximum module height Ball diameter 20 PID9v-604e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL The following sections provide the package parameters and mechanical dimensions for the common IBM and Motorola CBGA packages. IM 1.7 PowerPC 604e Microprocessor Package Description IN A 2. To operate in accordance with these specifications, the drive mode signals must be DRVMODE0 = low, DRVMODE1 = high RY 1.7.2 Mechanical Dimensions of the CBGA Package Figure 10 provides the mechanical dimensions and bottom surface nomenclature of the IBM and Motorola CBGA package. 2X 0.2 A1 CORNER D A 0.15 C E E1 2X 0.2 B D1 EL IM T R P N M L K J H G F E D C B A IN A A2 A1 A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 e/2 e 255X PR e/2 b 0.3 C A B 0.15 C Figure 10. Mechanical Dimensions and Bottom Surface Nomenclature of the CBGA Package PID9v-604e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE RY C NOTES: 1. DIMENSIONINGANDTOLERANCINGPERASMEY14.5M,1994. 2. DIMENSIONS IN MILLIMETERS. 3. TOP SIDE A1 CORNER INDEX IS A METALIZED FEATUREWITH VARIOUS SHAPES. BOTTOM SIDE A1 CORNER IS DESIGNATED WITH A BALL MISSING FROM THE ARRAY. MILLIMETERS DIM A A1 A2 b D D1 e E E1 MIN MAX 2.65 3.20 0.79 0.99 1.10 1.30 0.82 0.93 21.00 BSC 5.00 16.00 1.27 BSC 21.00 BSC 5.00 16.00 21 1.8 System Design Information This section provides electrical and thermal design recommendations for successful application of the 604e. 1.8.1 PLL Configuration The 604e PLL is configured by the PLL_CFG[0-3] signals. For a given SYSCLK (bus) frequency, the PLL configuration signals set the internal CPU and VCO frequency of operation. The PLL configuration for the 604e is shown in Table 11 for nominal frequencies. Table 11. PowerPC 604e Microprocessor PLL Configuration CPU Frequency in MHz (VCO Frequency in MHz) PLL_CFG[0-3] CPU/ SYSCLK Ratio 1.5:1 2:1 2.5:1 3:1 3.5:1 4:1 5:1 6:1 VCO Multiplier x2 x2 x2 x2 x2 Bus 25 MHz -- -- -- Bus 33.3 MHz Bus 40 MHz Bus 50 MHz Bus 60 MHz Bus 66.6 MHz 100 (200) 133 (267) 166 (333) 200 (400) 233 (466) -- -- -- Bus 75 MHz 112.5 (225) 150 (300) 187.5 (375) 225 (450) -- -- -- -- 1100 0100 0110 1000 1110 1010 1011 1101 0011 1111 IN A -- -- -- -- -- 100 (200) 120 (240) 140 (280) 160 (320) 200 (400) -- 100 (200) 116.6 (233) 133 (267) 166.5 (333) 200 (400) PLL bypass Clock off IM -- -- 100 (200) 125 (250) 150 (300) EL x2 x2 x2 PR Notes: 1. Some PLL configurations may select bus, CPU, or VCO frequencies which are not supported; see Section 1.4.2.2, "Input AC Specifications," for valid SYSCLK and VCO frequencies. 2. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set for 1:1 mode operation. This mode is intended for factory use only. Note: The AC timing specifications given in this document do not apply in PLL-bypass mode. 22 PID9v-604e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE RY -- 100 (200) 125 (250) 150 (300) 175 (350) 200 (400) -- -- -- -- -- -- 120 (240) 150 (300) 180 (360) 210 (420) 1.8.2 PLL Power Supply Filtering The AVdd power signal is provided on the 604e to provide power to the clock generation phase-locked loop. To ensure stability of the internal clock, the power supplied to the AVdd input signal should be filtered using a circuit similar to the one shown in Figure 11. The circuit should be placed as close as possible to the AVdd pin to ensure it filters out as much noise as possible. 10 Vdd (2.5 V) AVdd 10 F GND 0.1 F Figure 11. PLL Power Supply Filter Circuit 1.8.3 Decoupling Recommendations In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the Vdd and OVdd planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should also have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two vias to minimize inductance. The suggested values for these bulk capacitors are 100 F (AVX TPS tantalum) or 330 F (AVX TPS tantalum). 1.8.4 Connection Recommendations To ensure reliable operation, it is recommended to connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to Vdd. Unused active high inputs should be connected to GND. 1.8.5 Thermal Management Information This section provides thermal management information for the ceramic ball grid array (CBGA) package in air-cooled applications. Proper thermal control design is primarily dependent upon the system-level design--the heat sink, airflow and thermal interface material. To reduce the die-junction temperature, a heat sink may be attached to the package by several methods through the use of an adhesive, a spring clip to holes in the printed-circuit board, or a mounting clip and screw assembly; see Figure 12. For applications where the heat sink is attached by a spring clip, the spring force should not exceed 5.5 pounds of force. PID9v-604e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE PR These capacitors should vary in value from 220 pF to 10 F to provide both high- and low-frequency filtering, and should be placed as close as possible to their associated Vdd or OVdd pin. Suggested values for the Vdd pins--220 pF (ceramic), 0.01 F (ceramic), and 0.1 F (ceramic). Suggested values for the OVdd pins--0.01 F (ceramic), 0.1 F (ceramic), and 10 F (tantalum). Only SMT (surface mount technology) capacitors should be used to minimize lead inductance. EL IM Due to the 604e's dynamic power management feature, large address and data buses, and high operating frequencies, the 604e can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the 604e system, and the 604e itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each Vdd and OVdd pin of the 604e. It is also recommended that these decoupling capacitors receive their power from separate Vdd, OVdd, and GND power planes in the PCB, utilizing short traces to minimize inductance. IN A RY 23 Heat Sink Heat Sink Clip Adhesive or Thermal Interface Material CBGA Package Printed-Circuit Board IN A Figure 12. Package Exploded Cross-Sectional View with Several Heat Sink Options Thermalloy 2021 W. Valley View Lane P.O. Box 810839 Dallas, TX 75731 Wakefield Engineering 60 Audubon Rd. Wakefield, MA 01880 Aavid Engineering One Kool Path Laconia, NH 03247-0440 PR International Electronic Research Corporation (IERC) 135 W. Magnolia Blvd. Burbank, CA 91502 EL Chip Coolers Inc. 333 Strawberry Field Rd. Warwick, RI 02887-6979 IM The board designer can choose between several types of heat sinks to place on the 604e. There are several commercially-available heat sinks for the 604e provided by the following vendors: 800-227-0254 (USA/Canada) 401-739-7600 818-842-7277 214-243-4321 617-245-5900 603-528-3400 Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. 24 PID9v-604e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE RY Option 1.8.5.1 Internal Package Conduction Resistance For this packaging technology the intrinsic thermal conduction resistance (shown in Table 3) versus the external thermal resistance paths are shown in Figure 13 for a package with an attached heat sink mounted to a printed-circuit board. External Resistance Radiation Convection Heat Sink Internal Resistance Radiation External Resistance Figure 13. Package with Heat Sink Mounted to a Printed-Circuit Board 1.8.5.2 Adhesives and Thermal Interface Materials A thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal contact resistance. For those applications where the heat sink is attached by spring clip mechanism, Figure 14 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/ oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure. As shown, the performance of these thermal interface materials improves with increasing contact pressure. The use of thermal grease significantly reduces the interface thermal resistance. That is, the bare joint results in a thermal resistance approximately 7 times greater than the thermal grease joint. Therefore, the synthetic grease offers the best thermal performance, considering the low interface pressure. Of course, the selection of any thermal interface material depends on many factors--thermal performance requirements, manufacturability, service temperature, dielectric properties, cost, etc. PID9v-604e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE PR EL IM (Note the internal versus external package resistance) IN A Convection Printed-Circuit Board RY Die/Package Die Junction Package/Leads Thermal Interface Material 25 2 Silicone Sheet (0.006 inch) Bare Joint Floroether Oil Sheet (0.007 inch) Graphite/Oil Sheet (0.005 inch) Synthetic Grease Specific Thermal Resistance (Kin2/W) 1.5 1 0.5 0 0 10 20 IM 30 IN A 40 50 60 70 80 Contact Pressure (psi) Figure 14. Thermal Performance of Select Thermal Interface Material Dow-Corning Corporation Dow-Corning Electronic Materials P.O. Box 0997 Midland, MI 48686-0997 Chomerics, Inc. 77 Dragon Court Woburn, MA 01888-4850 Thermagon Inc. 3256 West 25th Street Cleveland, OH 44109-1668 Loctite Corporation 1001 Trout Brook Crossing Rocky Hill, CT 06067 PR The board designer can choose between several types of thermal interface. Heat sink adhesive materials should be selected based upon high conductivity, yet adequate mechanical strength to meet equipment shock/vibration requirements. There are several commercially-available thermal interfaces and adhesive materials provided by the following vendors: 517-496-4000 EL 617-935-4850 216-741-7659 860-571-5100 26 PID9v-604e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE RY AI Technology (e.g. EG7655) 1425 Lower Ferry Rd. Trent, NJ 08618 609-882-2332 The following section provides a heat sink selection example using one of the commercially available heat sinks. 1.8.5.3 Heat Sink Selection Example For preliminary heat sink sizing, the die-junction temperature can be expressed as follows: Tj = Ta + Tr + (jc + int + sa) * Pd Where: For a Thermalloy heat sink #2328B, the heat sink-to-ambient thermal resistance (sa) versus airflow velocity is shown in Figure 15. PID9v-604e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE PR Die-junction temperature: Tj = 30 C + 5 C + (2.2 C/W + 1.0 C/W + sa) * 15 W EL During operation the die-junction temperatures (Tj) should be maintained less than the value specified in Table 2. The temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air temperature rise within the electronic enclosure. An electronic cabinet inlet-air temperature (Ta) may range from 30 to 40 C. The air temperature rise within a cabinet (Tr) may be in the range of 5 to 10 C. Assuming the thermal resistance of the thermal interface material (int) is typically about 1 C/W, a Ta of 30 C, a Tr of 5 C a CBGA package jc = 0.1, and a power consumption (Pd) of 15 W the following expression for Tj is obtained: IM IN A 27 Tj is the die-junction temperature Ta is the inlet cabinet ambient temperature Tr is the air temperature rise within the electronic enclosure jc is the die junction-to-case thermal resistance int is the adhesive or interface material thermal resistance sa is the heat sink base-to-ambient thermal resistance Pd is the power consumed by the device RY 8 7 Heat Sink Thermal Resistance (C/W) Thermalloy #2328B Pin-fin Heat Sink (25 x 28 x 15 mm) 6 5 4 3 2 1 0 0.5 1 IM 1.5 IN A 2 2.5 3 3.5 Approach Air Velocity (m/s) Figure 15. Thermalloy #2328B Heat Sink-to-Ambient Thermal Resistance Versus Airflow Velocity 1. Increase the airflow velocity 2. Increase the surface area of the heat sink 3. Select a heat sink with an integrated cooling fan Heat sinks offered by Chip Coolers, IERC, Thermalloy, Wakefield Engineering, and Aavid Engineering offer different heat sink-to-ambient thermal resistances and air flow requirements. Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figureof-merit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when using only these metrics in determining thermal management because no single parameter can adequately describe three-dimensional heat flow. The final die-junction operating temperature is not only a function of the component-level thermal resistance, but the system-level design and its operating conditions. In addition to the component's power consumption, a number of factors affect the final operating die-junction temperature--airflow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink attach, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, etc. Due to the complexity and the many variations of system-level boundary conditions for today's microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection and conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models for 28 PR Assuming an air velocity of 1 m/s, we have an effective sa of 5 C/W, thus Tj = 30 C + 5 C + (0.1 C/W +1.0 C/W + 5 C/W) * 15 W, resulting in a die-junction temperature of approximately 125 C which exceeds the maximum operating temperature of the component. To reduce the die junction temperature the designer has several options: PID9v-604e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL RY the board, as well as, system-level designs. To expedite system-level thermal analysis, several "compact" thermal-package models are available within FLOTHERM(R). These are available upon request. 1.9 Ordering Information This section provides the part numbering nomenclature for the 604e. Note that the individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact your local Motorola or IBM sales office. 1.9.1 Motorola Part Number Key Figure 16 provides the Motorola part numbering nomenclature for the 604e. In addition to the processor frequency, the part numbering scheme also consists of a part modifier and application modifier. The part modifier indicates any enhancement(s) in the part from the original production design. The application modifier may specify special bus frequencies or application conditions. Each part number also contains a revision code. This refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. MPC 604 E XX XXX X X IM Product Code Part Identifier IN A RY Revision Level (Contact Local Motorola Sales Office) Application Modifier Processor Frequency Package (RX = BGA) Part Modifier (E = Enhanced and Lower Voltage --604e) PR 1.9.2 IBM Part Number Key Figure 17 provides the IBM part numbering nomenclature for the 604e. Product Code Part Identifier Part Modifier (e = Enhanced and Lower Voltage) Package (B = BGA) Processor Frequency Revision Level (Contact Local IBM Sales Office) PID9v-604e Hardware Specifications PRELIMINARY--SUBJECT TO CHANGE WITHOUT NOTICE EL Figure 16. Motorola Part Number Key PPC 604 e X X XXX Figure 17. IBM Part Number Key 29 Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors. There are no express or implied copyright or patent licenses granted hereunder by Motorola or IBM to design, modify the design of, or fabricate circuits based on the information in this document. The PowerPC 60x microprocessor embodies the intellectual property of Motorola and of IBM. However, neither Motorola nor IBM assumes any responsibility or liability as to any aspects of the performance, operation, or other attributes of the microprocessor as marketed by the other party or by any third party. Neither Motorola nor IBM is to be considered an agent or representative of the other party or any third party, and neither has assumed, created, or granted hereby any right or authority to the other, or to any third party, to assume or create any express or implied obligations on its behalf. Information such as errata sheets and data sheets, as well as sales terms and conditions such as prices, schedules, and support, for the product may vary as between parties selling the product. Accordingly, customers wishing to learn more information about the products as marketed by a given party should contact that party. Both Motorola and IBM reserve the right to modify this document and/or any of the products as described herein without further notice. NOTHING IN THIS DOCUMENT, NOR IN ANY OF THE ERRATA SHEETS, DATA SHEETS, AND OTHER SUPPORTING DOCUMENTATION, SHALL BE INTERPRETED AS THE CONVEYANCE BY MOTOROLA OR IBM OF AN EXPRESS WARRANTY OF ANY KIND OR IMPLIED WARRANTY, REPRESENTATION, OR GUARANTEE REGARDING THE MERCHANTABILITY OR FITNESS OF THE PRODUCTS FOR ANY PARTICULAR PURPOSE. Neither Motorola nor IBM assumes any liability or obligation for damages of any kind arising out of the application or use of these materials. Any warranty or other obligations as to the products described herein shall be undertaken solely by the marketing party to the customer, under a separate sale agreement between the marketing party and the customer. In the absence of such an agreement, no liability is assumed by Motorola, IBM, or the marketing party for any damages, actual or otherwise. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals," must be validated for each customer application by customer's technical experts. Neither Motorola nor IBM convey any license under their respective intellectual property rights nor the rights of others. Neither Motorola nor IBM makes any claim, warranty, or representation, express or implied, that the products described in this document are designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the product could create a situation where personal injury or death may occur. Should customer purchase or use the products for any such unintended or unauthorized application, customer shall indemnify and hold Motorola and IBM and their respective officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney's fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola or IBM was negligent regarding the design or manufacture of the part. Motorola and Employer. are registered trademarks of Motorola, Inc. Mfax is a trademark of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action IBM, the IBM logo, and IBM Microelectronics are trademarks of International Business Machines Corporation. The PowerPC name, the PowerPC logotype, PowerPC 604, and PowerPC 604e are trademarks of International Business Machines Corporation, used by Motorola under license from International Business Machines Corporation. International Business Machines Corporation is an Equal Opportunity/Affirmative Action Employer. International Business Machines Corporation: IBM Microelectronics Division, 1580 Route 52, Bldg. 504, Hopewell Junction, NY 12533-6531; Tel. (800) PowerPC World Wide Web Address: http://www.chips.ibm.com/products/ppc http://www.ibm.com Motorola Literature Distribution Centers: USA/EUROPE: Motorola Literature Distribution; P.O. Box 5405; Denver, Colorado 80217; Tel.: 1-800-441-2447 or (303) 675-2140 JAPAN: Nippon Motorola Ltd SPD, Strategic Planning Office 4-32-1, Nishi- Gotanda Shinagawa-ku, Tokyo 141, Japan Tel.: 81-3-5487-8488 ASIA/PACIFC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong; Tel.: 852-26629298 MfaxTM: RMFAX0@email.sps.mot.com; TOUCHTONE (602) 244-6609; US & Canada ONLY (800) 774-1848 INTERNET: http://motorola.com/sps Technical Information: Motorola Inc. SPS Customer Support Center; (800) 521-6274. Document Comments: FAX (512) 891-2638, Attn: RISC Applications Engineering. World Wide Web Address: http://www.mot.com/powerpc/ MPC604E9VEC/D |
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