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| SP5768 SP5768 3.0GHz Low Phase Noise Frequency Synthesiser DS5077 ISSUE 1.4 July 2001 Features * * * * * * * * * * * Complete 3.0GHz single chip system Optimised for low phase noise, with comparison frequencies up to 4 MHz No RF prescaler Selectable reference division ratio Reference frequency output Selectable charge pump current Integrated loop amplifier Four switching ports Low power replacement for SP5658 and 5668 Downwards software compatible with SP5658 ESD protection, (Normal ESD handling procedures should be observed) Ordering Information SP5768/KG/MP1S (Tubes) SP5768/KG/MP1T (Tape and Reel) SP5768/KG/QP1S (Tubes) SP5768/KG/QP1T (Tape and Reel) Description The SP5768 is a single chip frequency synthesiser designed for tuning systems up to 3.0GHz and is optimized for low phase noise with comparison frequencies up to 4 MHz. The RF programmable divider contains a front end dual modulus 16/17 functioning over the full operating range and allows for coarse tuning in the upconverter application and fine tuning in the downconverter. Comparison frequencies are obtained either from a crystal controlled on-chip oscillator or from an external source. A buffered reference frequency output is also available to drive a second SP5768. The device also contains 4 switching ports. Applications * TV, VCR and Cable tuning systems * Communications systems REF 13 BIT COUNT RF INPUT 16/17 4 BIT COUNT REFERENCE DIVIDER CRYSTAL CAP CRYSTAL CHARGE PUMP DRIVE 17 BIT LATCH 6 BIT LATCH DATA CLOCK ENABLE DATA INTERFACE 5 BIT LATCH & PORT/ TEST MODE INTERFACE PORT P0/OP PORT P1/OC PORT P2 PORT P3 Figure 1 - SP5768 block diagram 1 SP5768 16 CHARGE PUMP CRYSTAL CAP CRYSTAL ENABLE DATA CLOCK PORT P1/OC PORT P2 DRIVE V EE RF INPUT RF INPUT V CC REF PORT P0/OP PORT P3 Figure 2 - Pin Connections Diagram SPOT REF. MP16 QP16 Electrical Characteristics These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated. TAMB = -40C to 80C, VCC = +4*5V to +5*5V Characteristic Pin Min Value Typ 18 100 100 30 Max 25 3000 300 300 Units Conditions Supply current RF input frequency range RF input voltage 12 13,14 13,14 13, 14 mA MHz mV rms 100 - 200MHz mVrms See Figure 6 See Figure 3 RF input impedance Data, clock & enable input high voltage input low voltage input current hysterysis Clock rate Bus timing data set up data hold enable set up enable hold clock to enable 13,14 5,6,4 3 0 -10 0.8 6 5,6,4 300 600 300 600 300 ns ns ns ns ns Vcc 0.7 10 V V A V 500 All input conditions kHz 2 SP5768 Electrical Characteristics (continued) These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated. Tamb = -40C to 80C, Vcc = +4*5V to +5*5V Characteristic Pin Min Charge pump output current Charge pump output leakage Charge pump drive output current Crystal frequency External reference input frequency External reference drive level Buffered reference frequency output output amplitude output impedance Comparison frequency Equivalent phase noise at phase detector -148 1 Value Typ Units Max See Table 1 Vpin1 = 2V 3 10 nA Vpin1=2V, Vcc = +5.0V, Tamb = 25C Vpin 16=0.7V Conditions 1 16 0.5 mA 2,3 3 2 2 20 20 MHz MHz See Figure 5 for application Sinewave coupled through 10F blocking capacitor Sinewave coupled through 10nF blocking capacitor AC coupled, See note 1 3 0.2 0.5 Vpp 11 0.35 250 4 Vpp MHz dBc/Hz 2-20MHz At 10 kHz, SSB, with 2 MHz comparison from 4 MHz crystal reference RF division ratio Reference division ratio Output ports P0-P3 sink current leakage current 1 2 7,8,9,10 240 2 131071 320 See Table 2 See Note 2 Vport = 0.7V Vport = Vcc 2 10 mA A Reference output disabled by connecting to Vcc if not required Output ports high impedance on power up, with data, clock and enable at logic 0 3 SP5768 Absolute Maximum Ratings All voltages are referred to Vee at 0V Characteristic Supply voltage, Vcc RF input voltage RF input DC offset Port voltage Charge pump DC offset Varactor drive DC offset Crystal DC offset Buffered ref output Data, clock & enable DC offset Storage temperature Junction temperature MP16 thermal resistance, chip to ambient chip to case Power consumption at Vcc=5.5V ESD protection Pin 12 13,14 13,14 7,8,9,10 1 16 2,3 11 5,6,4 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -55 Min -0.3 Typ Max 7 2.5 V cc+0.3 V cc+0.3 V cc+0.3 V cc+0.3 V cc+0.3 V cc+0.3 V cc+0.3 +125 +150 80 20 138 2 Units V Vp-p V V V V V V V C C C/W C/W mW kV All ports off Mil-std 883B latest revision method 3015 cat.1. Differential Conditions Functional description The SP5768 contains all the elements necessary, with the exception of a frequency reference, loop filter and external high voltage transistor, to control a varicap tuned local oscillator, so forming a complete PLL frequency synthesised source. The device allows for operation with a high comparison frequency and is fabricated in high speed logic, which enables the generation of a loop with excellent phase noise performance, even with high comparison frequencies. The package and pin allocation is shown in Figure 1 and the block diagram in Figure 2. The SP5768 is controlled by a standard 3-wire bus comprising data, clock and enable inputs. The programming word contains 28 bits, four of which are used for port selection, 17 to set the programmable divider ratio, four bits to select the reference division ratio, bits RD & R0-R2, see Table 2, two bits to set charge pump current, bit C0 and C1, see Table 1, and the remaining bit to access test modes, bit T0, see Table 3. The programming format is shown in Figure 4. The clock input is disabled by an enable low signal, data is therefore only loaded into the internal shift registers during an enable high and is clocked into the controlling buffers by an enable high to low transition. This load is also synchronised with the programmable divider so giving smooth fine tuning. The RF signal is fed to an internal preamplifier, which provides gain and reverse isolation from the divider signals. The output of the preamplifier is fed to the 17 bit fully programmable counter, which is of MN+A architecture. The M counter is 13 bit and the A counter 4 The output of the programmable counter is fed to the phase comparator where it is compared in both phase and frequency domain with the comparison frequency. This frequency is derived either from the on board crystal controlled oscillator or from an external reference source. In both cases the reference frequency is divided down to the comparison frequency by the reference divider which is programmable into1 of 16 ratios as descried in Table 2. The output of the phase detector feeds the charge pump and loop amplifier section, which when used with an external high voltage transistor and loop filter integrates the current pulses into the varactor line voltage. The charge pump current setting is described in Table 1, A buffered crystal reference frequency suitable for driving further synthesisers is available from Pin 11. If not required this output can be disabled by connecting to Vcc The programmable divider output divided by 2, Fpd/2 and comparison frequency, Fcomp can be switched to ports P0 and P1 respectively by switching the device into test mode. The test modes are described in Table 3. 4 SP5768 +j1 +j0.5 +j2 +j0.2 +j5 0 1 -j0.2 S11 : Zo = 50 Normalised to 50 -j0.5 -j1 4 3 2 -j5 Frequency Markers at 500MHz, 1GHz, 1.5GHz and 2.4GHz -j2 Figure 3 - RF input impedance CLOCK ENABLE DATA 227 P3 226 P2 225 P1 224 P0 223 T0 222 C1 221 C0 220 R2 219 R1 218 R0 217 RD 216 MSB 20 LSB Frequency data 2^16 to 2^0 R2,R1,R0 RD P3, P2, P1,P0 C1,C0 T0 : : : : : : Programmable divider ratio control bits Reference divider control bits Reference divider mode select Port control bits Charge pump current select Test mode enable Figure 4 - Data format C1 0 0 1 1 C0 0 1 0 1 Current (in A) 230 1000 115 500 Table 1 - Charge pump current 5 SP5768 2 18pF 39pF 3 SP5768 Figure 5 - Crystal oscillator application RD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 R1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Table 2 - Reference division ratio R0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 RATIO 2 4 8 16 32 64 128 256 3 5 10 20 40 80 160 320 P1 X 0 0 1 1 X = don't care P0 X 0 1 0 1 T0 0 1 1 1 1 FUNCTIONAL DESCRIPTION Normal operation Charge pump sink Charge pump source Charge pump disable Port P1 = Fcomp, P0 = Fpd/2 Table 3 - Test modes 6 SP5768 300 VIN (mV RMS INTO 50) 100 30 10 OPERATING WINDOW 100 200 1000 FREQUENCY (MHz) 3000 Figure 6 - Typical input sensitivity 50 - 900MHz 1.6GHz 38.9MHz 1650-2700MHz 1650 -2400MHz 2 3 SP5768 SP5748 SP5768 SP5748 VCO VCO 3 10 11 10nF Figure 7 - Example of double conversion from VHF/UHF frequencies to TV IF 18pF 2 39pF 3 4MHz +30V 68pF 2n2 13k3 BCW31 22k +5V +12V 1k OR 4n7 Optional application utilising on-board crystal controlled oscillator 1 2 16 15 REFERENCE CONTROL MICRO ENABLE DATA CLOCK P1 P2 1n 1n OSCILLATOR OUTPUT 10n P0 P3 TUNER SP5768 3 4 5 6 7 8 14 13 12 11 10 9 Figure 8 - Typical application SP5768 7 SP5768 Application Notes A generic set of application notes AN168 for designing withsynthesisers such as the SP5768 has been written. This covers aspects such as loop filter design and decoupling. This application note is also featured in the Media Data Book, or refer to the Zarlink Semiconductor Internet Site http://www.zarlink.com. Loop Bandwidth The majority of applications for which the SP5768 is intended require a loop filter bandwidth of between 2kHz and10kHz. Typically the VCO phase noise will be specified at both 1kHz and10kHz offset. It is common practice to arrange the loop filter bandwidth such that the 1kHz figure lies within the loop bandwidth. Thus the phase noise depends on the synthesiser comparator noise floor, rather than the VCO. The 10kHz offset figure should depend on the VCO providing the loop is designed correctly, and is not underdamped. Reference Source The SP5768 offers optimal LO phase noise performance when operated with a large step size. This is due to the fact that the LO phase noise within the loop bandwidth is: phase comparator LO frequency noise floor + 20 log 10 phase comparator frequency ( ) Assuming the phase comparator noise floor is flat irrespective of sampling frequency, this means that the best performance will be achieved when the overall LO to phase comparator division ratio is a minimum. There are two ways of achieving a higher phase comparator sampling frequency:- A) Reduce the division ratio between the reference source and the phase comparator B) use a higher reference source frequency. Approach B) may be preferred for best performance since it is possible that the noise floor of the reference oscillator may degrade the phase comparator performance if the reference division ratio is very small. 8 SP5768 VREF VCC 500 500 CHARGE PUMP RF INPUTS 200 DRIVE RF inputs Loop amplifier VCC PORT 25K INPUT BIAS Disable, Enable, Data and Clock inputs Output Ports VCC VCC CRYSTAL REF CRYSTAL CAP 1.2mA Reference oscillator Reference output Figure 9 - Input/Output interface circuits 9 For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request. Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in an I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2002, Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE |
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