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TC9444F
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC9444F
Single-Chip karaoke IC II
The TC9444F is a karaoke chip for such applications as equipment for CD/LD players, mini component stereo sets, radio-cassette players, and VTRs. With its internal AD/DA converter system, the TC9444F can offer such karaoke functions as echo, vocal canceling, and key control on a single chip in addition to such digital signal processing (DSP) features as sound field control and bass/treble control. Because the program and coefficients are stored on internal ROM, the IC can be controlled by simple settings.
Features
* THD: -65dB * S/N ratio: 80dB (typ.)
Weight: 1.08 g (typ.)
Incorporates an AD converter (three channels) with 2 times oversampling. built-in pre-filter op-amp Incorporates a 1-bit -type DA converter (two channels). THD: -86dB S/N ratio: 93dB (typ.) built-in tertiary analog post filter
* * * *
Supports one port for digital input and one for digital output. Incorporates 64 Kbits of delay RAM Microcontroller interface: I2C bus mode as well as Toshiba's original three-lead mode Built-in boot ROM initializes coefficients at reset or via a boot command.
[Compatible Software]
* * * * * * * * * * * Microphone echo: Variable delay time/level Vocal cancellation: Attenuates only vocals from standard source Vocal change: Vocals fade in/out depending on whether there is input from microphone Vocal key control: For chorus and duet functions Supports multi-sound sources: Various modes Pseudo stereo: Monaural sources enhanced by sense of spaciousness Key control: 14-step (max 1 octave) stereo key control Compressor or bass boost: Compression ratio selectable in range 6 to 36dB. Compression effect (amount of boost) can be varied smoothly. Sound field control: Uses delay RAM to simulate such acoustic environments as churches, halls, sports stadiums, and discos. Equalizer: Characteristics switchable by coefficient or I/F bit settings 3D sound field: Offers 3-D sound.
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EXTC EXTB EXTA EXT9 EXT8 EXT7 GNDD2 TEST EMP SDA SCL CS IFSEL RESET 47 46 VDD2
Block Diagram/Pin Assignment
60
59
58
57
56
55
54
53
52
51
50
49
48
EXTO 45 44 64 kbit DRAM 4096 w 16 b Microcontroller interface 43 42 1/2 decimation filter AOUT Data I/O 41 40
1
LRCKI BCKI SDI LRCKO BCKO SDO
EXTE
2
EXTF
3
GNDL
4
VDL
5
16-bit AD converter (three shared channels)
VDA1
6
Program ROM
39
VDD1
LPFO1
7
MICI Data RAM Compressor
8 38 37 Coefficient-offset RAM Boot ROM 36 35 34 33 Coefficient ROM Timing Gene. 32 31 Analog post filter MCKO MCKS CKS EXT6 EXT5 EXT4 Selector EXT3 EXT2
VRA1
9
Key control 2
AIL
10
LPFO2
11
Digital filter and aD-type modulator
VRA2 2-ch 1 bit DAC
12 Multiplier/adder
LPFO3
13
AIR
14
GNDA1
15
Analog post filter
16 VRL VRR VDA2 AOR
17
18
19
20
21
22 GNDAR
23 DZ
24 VDX
25 XO
26 XI
27 GNDX
28 GNDD1
29 EXT0
30 EXT1
GNDAL
AOL
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Pin Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Pin Name EXTO EXTE EXTF GNDL VDL VDA1 LPFO1 MICI VRA1 AIL LPFO2 VRA2 LPFO3 AIR GNDA1 GNDAL AOL VRL VDA2 VRR AOR GNDAR DZ VDX XO XI GNDX GNDD1 EXT0 EXT1 EXT2 EXT3 EXT4 EXT5 EXT6 CKS MCKS MCKO VDD1 SDO BCKO LRCKO SDI I/O O O O 3/4 3/4 3/4 O I 3/4 I O 3/4 O I 3/4 3/4 O 3/4 3/4 3/4 O 3/4 O 3/4 O I 3/4 3/4 O O O O O O O I I O 3/4 O O O I Extended output port D Extended output port E Extended output port F DRAM ground DRAM power supply ADC power supply Op-amp output for microphone input Op-amp input for microphone input ADC reference voltage 1 Op-amp input for line L-channel Op-amp output for line L-channel ADC reference voltage 2 Op-amp output for line R-channel Op-amp input for line R-channel ADC ground DAC L-channel ground DAC L-channel output DAC reference voltage DAC power supply DAC reference voltage DAC R-channel output DAC R-channel ground Digital zero input detection ("H" = zero detection) Oscillator block power supply Oscillator connection Oscillator connection or clock input Oscillator block ground Digital ground 1 Extended output port 0 Extended output port 1 Extended output port 2 Extended output port 3 Extended output port 4 Extended output port 5 Extended output port 6 System clock selection ("H" = 512 fs, "L" = 384 fs) MCKO output clock selection ("H" = 1/1, "L" = 1/2 divider) System clock output Digital power supply 1 Digital audio data output Bit clock output Channel clock output Digital audio data input Schmitt input Schmitt input Schmitt input Function Remarks
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Pin No. 44 45 46 47 48 Pin Name BCKI LRCKI VDD2
RESET
I/O I I 3/4 I (U) I Bit clock input Channel clock input Digital power supply 2 Reset ("L" = reset)
Function
Remarks Schmitt input Schmitt input
With pull-up resistor Schmitt input Schmitt input
IFSEL
Microcontroller interface selection ("H" = three-lead mode, "L" = I2C mode) Three-lead mode: Command send start signal
2
49 50 51 52 53 54 55 56 57 58 59 60
CS
I I O 3/4 I (U) I O O O O O O
Schmitt input Schmitt input Schmitt input Schmitt input With pull-up resistor Schmitt input
I C: chip select SCL SDA EMP
TEST
Microcontroller interface serial clock Microcontroller interface serial data De-emphasis setting ("H" = ON) Test mode setting ("H" = fixed) Digital ground 2 Extended output port 7 Extended output port 8 Extended output port 9 Extended output port A Extended output port B Extended output port C
GNDD2 EXT7 EXT8 EXT9 EXTA EXTB EXTC
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Block Operations
1. Operating Clocks
The master clock can be selected between 512 or 384 fs using the CKS pin. The master clock uses oscillator or external clock input, through the XI pin. Regardless of a master clock, the number of digital signal processing steps are predetermined. However, the DA converter's operating clock varies according to the master clock mode. The MCKS pin sets the MCKO output, selecting 1/1 or 1/2 divider of the XI pin.
Table 1.1
Operating Clock Selection and DA Converter Oversampling Rate
CKS Pin L MCKS Pin L H L H H 512 fs 512 fs XI Input MCKO Output 192 fs 384 fs 256 fs 256 fs DAC Oversampling Rate
384 fs
192 fs
2. Digital Audio Data Input/Output
2.1 Sync Mode
The data input/output bit clock and internal sync (master) mode or external sync (slave) mode are set using microcontroller interface bits SYNM1 and SYNM2. Initialization by reset sets master mode.
Table 2.1 Sync Mode and Input/Output Bit Clock Settings
SYNM2 0 0 1 1 SYNM1 0 1 0 1 SYNC Mode BCKI (Note 1) (Note 2) Slave Slave Slave 32 fs 48 fs 64 fs BCKI BCKI BCKI BCKO 64 fs Master
Note 1: See Table 2.2. Note 2: XI input divider clock
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2.2 Data Input Formats
Table 2.2 and Figure 2.1 show the data input formats. Microcontroller interface bits IBIT1, IBIT2, and IBIT3 select the format. In master mode, the BCKI clock rate varies through the range shown in 2.2. In slave mode, the BCKI input clock is directly output through the IC internal buffer as the data output bit clock (BCKO). Therefore, when using the digital data output, input the clock shown in Table 2.2. The IIS-compatible format can accept up to 24 bits of data. When inputting data shorter than 24 bits, fix the lower bits to 0.
Table 2.2
SYNM2 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 SYNM1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 IBIT3 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 IBIT2 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 IBIT1 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0
Data Input Formats
Format MSB first, Right-Justified mode, 16-bit data MSB first, Right-Justified mode, 18-bit data Master mode MSB first, Right-Justified mode, 20-bit data MSB first, Right-Justified mode, 24-bit data IIS-compatible, 24 bits MSB first, Right-Justified mode, 16-bit data Prohibited Prohibited Prohibited IIS-compatible, 16 bits MSB first, Right-Justified mode, 16-bit data MSB first, Right-Justified mode, 18-bit data Slave mode MSB first, Right-Justified mode, 20-bit data MSB first, Right-Justified mode, 24-bit data IIS-compatible, 24 bits MSB first, Right-Justified mode, 16-bit data MSB first, Right-Justified mode, 18-bit data MSB first, Right-Justified mode, 20-bit data MSB first, Right-Justified mode, 24-bit data IIS-compatible, 24 bits BCKI 32 fs to 128 fs 36 fs to 128 fs 40 fs to 128 fs 48 fs to 128 fs 64 fs 32 fs 32 fs 32 fs 32 fs 32 fs 48 fs 48 fs 48 fs 48 fs 48 fs 64 fs 64 fs 64 fs 64 fs 64 fs
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a) (IBIT3, IBIT2, IBIT1) = (0, 0, 0): MSB first, Right-Justified mode, 16-bit data LRCKI BCKI LSB SDI 0 15 0 15 0 MSB LSB MSB LSB
b) (IBIT3, IBIT2, IBIT1) = (0, 0, 1): MSB first, Right-Justified mode, 18-bit data LRCKI BCKI LSB SDI 0 17 0 17 0 MSB LSB MSB LSB
c) (IBIT3, IBIT2, IBIT1) = (0, 1, 0): MSB first, Right-Justified mode, 20-bit data LRCKI BCKI LSB SDI 0 19 0 19 0 MSB LSB MSB LSB
d) (IBIT3, IBIT2, IBIT1) = (0, 1, 1): MSB first, Right-Justified mode, 24-bit data LRCKI BCKI LSB SDI 0 23 0 23 0 MSB LSB MSB LSB
e) (IBIT3, IBIT2, IBIT1) = (1, 0, 0): IIS-compatible, 24 bits max LRCKI BCKI MSB SDI 23 0 23 0 23 LSB MSB LSB MSB
Note 3: In either mode, sections where "SDI" is omitted are don't care (no internal data loading).
Figure 2.1
Data Input Formats (BCK = 64 fs)
The microcontroller interface RLS bit controls the polarity of the input/output channel clock (LRCKI, LRCKO).
Table 2.3
RLS 0 1
Channel Clock Polarity
Operation
L-channel data input/output when LRCKI and LRCKO = "H" L-channel data input/output when LRCKI and LRCKO = "L"
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2.3 Zero Data Detection Function Common to L/R
The TC9444F incorporates a function to output a zero detection flag from the DZ pin when input data contain a string of digital zeros. This is used to forcibly mute the analog output. Table 2.4 shows the time that elapses until data are detected as zero data. If digital zeros continue to be output during this period, a zero detection flag is set. Moreover, setting the DZINH bit in the microcontroller interface mode command to "H" halts zero detection, fixing the DZ pin to "L" and disabling the zero detection function (see the microcontroller interface section below).
Table 2.4
fs Detection Time
Digital Zero Data Detection Time
32 kHz 1024 ms 44.1 kHz 743 ms 48 kHz 683 ms
A reset sets the DZ signal to "H".
2.4
Data Output Formats
Table 2.5 and Figure 2.2 show the data output formats. Microcontroller interface bits OBIT1 and OBIT2 select the format. In master mode, the BCKI clock rate varies through the range shown in Table 2.2. Note, however, that BCKO is fixed to 64 fs. In slave mode, the BCKI input clock is directly output as the data output bit clock (BCKO) through the IC internal buffer (see section 2.2).
Table 2.5
SYNM2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SYNM1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 IBIT2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 IBIT1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Data Output Formats
Format MSB first, Right-Justified mode, 16-bit data Master mode MSB first, Right-Justified mode, 20-bit data MSB first, Right-Justified mode, 24-bit data IIS-compatible, 24 bits MSB first, Right-Justified mode, 16-bit data Prohibited Prohibited IIS-compatible, 16 bits MSB first, Right-Justified mode, 16-bit data MSB first, Right-Justified mode, 20-bit data Slave mode MSB first, Right-Justified mode, 24-bit data IIS-compatible, 24 bits MSB first, Right-Justified mode, 16-bit data MSB first, Right-Justified mode, 20-bit data MSB first, Right-Justified mode, 24-bit data IIS-compatible, 24 bits BCKI 64 fs 64 fs 64 fs 64 fs 32 fs (= BCKI) 32 fs (= BCKI) 32 fs (= BCKI) 32 fs (= BCKI) 48 fs (= BCKI) 48 fs (= BCKI) 48 fs (= BCKI) 48 fs (= BCKI) 64 fs (= BCKI) 64 fs (= BCKI) 64 fs (= BCKI) 64 fs (= BCKI)
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(SYNM2, 1) = (0, 0) or (1, 1) BCKO = 64 fs
LRCKO BCKO a) (OBIT2, OBIT1) = (0, 0): MSB first, Right-Justified mode, 16-bit data LSB SDO 0 15 0 15 0 MSB LSB MSB LSB
b) (OIBIT2, OBIT1) = (0, 1): MSB first, Right-Justified mode, 20-bit data LSB SDO 0 19 0 19 0 MSB LSB MSB LSB
c) (OBIT2, OBIT1) = (1, 0): MSB first, Right-Justified mode, 24-bit data LSB SDO 0 23 0 23 0 MSB LSB MSB LSB
d) (OBIT2, OBIT1) = (1, 1): IIS-compatible, 24 bits max MSB SDO 23 0 23 0 23 LSB MSB LSB MSB
(SYNM2, 1) = (1, 0) BCKO = 48 fs
LRCKO BCKO a) (OBIT2, OBIT1) = (0, 0): MSB first, Right-Justified mode, 16-bit data LSB SDO 0 15 0 15 0 MSB LSB MSB LSB
b) (OIBIT2, OIBIT1) = (0, 1): MSB first, Right-Justified mode, 20-bit data LSB SDO 0 19 0 19 0 MSB LSB MSB LSB
c) (OBIT2, OBIT1) = (1, 0): MSB first, Right-Justified mode, 24-bit data LSB MSB SDO 0 23 0 23 0 23 LSB MSB LSB MSB
d) (OBIT2, OBIT1) = (1, 1): IIS-compatible, 24 bits max LSB MSB SDO 0 23 0 23 0 23 LSB MSB LSB MSB
(SYNM2, 1) = (0, 1) BCKO = 32 fs
LRCKO BCKO a) (OBIT2, OBIT1) = (0, 0): MSB first, Right-Justified mode, 16-bit data LSB MSB SDO 0 15 0 15 0 15 LSB MSB LSB MSB
b) (OIBIT2, OBIT1) = (0, 1): MSB first, Right-Justified mode, 20-bit data...Prohibited c) (OBIT2, OBIT1) = (1, 0): MSB first, Right-Justified mode, 24-bit data...Prohibited d) (OBIT2, OBIT1) = (1, 1): IIS-compatible, 24 bits max LSB MSB SDO 0 15 0 15 0 15 LSB MSB LSB MSB
Figure 2.2
Data Output Formats
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3. Microcontroller Interface
Consisting of commands and data, the microcontroller interface block is designed as a simple and easy-to-use interface. This interface has two modes: I2C bus mode and three-lead mode. I2C bus mode can be switched by a DC setting via a pin.
3.1
Commands
One-byte (8-bit) commands are used to perform a range of settings. Some commands are followed by one to three bytes of data. An initial reset sets the microcontroller interface block to master mode. Boot ROM data can be used to output a sound at reset (analog through mode). After power-on, reset at least once by setting the RESET pin to low level.
Table 3.1
Command BOOT MUTE KEYCON VC BKSA BKSB EMP DECI ATIME RTIME COMP ATTA ATTB KEYCON2 EXTO CRAM MODE CH 0 1 2 3 4 5 6 7 8 9 A B B B B C D CL 0 0 to 3 0 to F 0 to F 0 to 3 0, 1 0 to F 0 to 3 0 to 3 0 to 6 0 to F 0 1 2 3 0, 1 0 to 3
List of Commands
Data 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 2-byte 2-byte 2-byte 2-byte 3-byte 1-byte Setting Contents Initializes coefficient RAM. Turns soft mute and RAMCLR on/off. Key control; amount of key shift 16-page bank vocal cancel/change, multi-sound source 4-page bank function reserve 2-page bank function reserve De-emphasis Delay RAM decimation rate Level detection attack time Level detection release time Compressor function Digital attenuator level A Digital attenuator level B Controls an independent key or sets vibrato. Extended output port data Writes coefficient RAM. Sets IC operating mode.
Note 4: The functions of some commands vary according to the internal program. Also, some programs contain commands that need not be set. Refer to the separate software datasheet.
The commands are described below. The values in the table marked by an asterisk are the initial values at a reset. Setting RESET to "L" also mutes the DA converter output (op-amp feed-back causes the DA converter to output VREF). Accordingly, to completely mute the analog output during operation, digitally mute the output using the MUTE command, then set RESET to "L".
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3.2 BOOT Command
One-byte command to initialize coefficient RAM. Initializes coefficient RAM values to the internal BOOT ROM values, retaining the other command interface settings. After the BOOT command is received, initialization completes in a 1-fs cycle. Boot release is not required. When reset is made by setting the RESET pin to "L", boot is still executed.
3.3
MUTE Command
One-byte command to clear data RAM and delay RAM, and to execute a soft mute using the digital attenuator.
Table 3.2
CH 3 1 0
MUTE Command
CL 2 0 1 RAMCLR 0 MUTE
Note 5: At a reset, the initial value is CL = 0H. MUTE: MUTE = "H" sets soft mute. RAMCLR: RAMCLR = "H" clears data RAM and delay RAM.
At a soft mute, the time constant is determined by the operation sampling frequency and the time constant selection bit set by the ATTA command. After the soft mute is released, the digital attenuator is restored to the set level. In data RAM, sequentially writing all-zero data (fixing the input data to 000000H) while RAMCLR = "H" clears data RAM. Therefore, the number of fs cycles required to completely clear data RAM depends on the program. Normally, several cycles are required. For a program which is written to in one place only, a 128-word update takes no more than 3 ms. In delay RAM, after RAMCLR = H, 0000H is sequentially written to delay RAM at subsequent write operations (INIT operation). When using delay RAM to significantly change the effect of the SFC processing, to clear the data in RAM, take the following steps. First set the MUTE bit. Then, after waiting only the length of the digital attenuator time constant, set RAMCLR to "H" to clear the data in RAM. Then set the RAMCLR and MUTE bits to "L". This will enable you to change the signal processing content without any switching noise.
3.4
KEYCON Command
One-byte command to control the amount of key shift. The CL value indicates the amount of key shift. The difference between the 20H command and the 28H command is the point at which key control processing completely stops. Using the 20H command to turn key control off disables the use of internal delay RAM in the key control processing, thus allowing delay RAM to be allocated to other processing. The amount of key shift set by the KEYCON command applies to both L and R stereo key control and to monaural key control. The key shift is set in semitone steps. As delay RAM is used in key control processing, when switching the key shift setting between 0 and a value other than 0, the signal is intermittent. The soft mute automatically comes on to avoid switching noise at this time. After the command is issued, the following steps are performed automatically. Mute (R) Internal settings switched (R) Mute released This series of processing operations takes around 46 ms to execute.
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Table 3.3 Setting Key Shift Amount
CH 2 2 2 2 2 2 2 2 *2 2 2 2 2 2 2 2 CL 0 1 2 3 4 5 6 7 8 9 A B C D E F Setting Content Key shift 0 (key control off) +1200 cent +600 cent +500 cent +400 cent +300 cent +200 cent +100 cent Key shift 0 -100 cent -200 cent -300 cent -400 cent -500 cent -600 cent -1200 cent
3.5
VC Command
One-byte command to set through, vocal cancel, and vocal change for each input source. Refer to the separate software datasheet.
3.6
BKSA Command
One-byte command to set four-page bank switching.
3.7
BKSB Command
One-byte command to set two-page bank switching.
3.8
EMPH Command
This command selects an internal de-emphasis digital filter. The filter is either a digital filter selected, via software, by switching a DSP coefficient bank, or an internal DA converter digital filter selected via hardware. The filter is set through the microcontroller interface. The filter is on only when the EMP pin goes high. This command sets the filter on/off directly from the CD processor EMP flag without passing through the microcontroller. As well as a de-emphasis filter, the DSP block filter can also be used as a high-pass filter for canceling DC offset. (the CROM data determines the filter's function.)
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Table 3.4 EMPH Command
CH 3 6 ESB2 2 ESB1 CL 1 ESA2 0 ESA1
Note 6: At a reset, the initial value is CL = 5H.
Table 3.5 Settings with EMPH Command
CH ESB2 6 *6 6 6 6 *6 6 6 3/4 3/4 3/4 3/4 0 0 1 1 ESB1 3/4 3/4 3/4 3/4 0 1 0 1 CL ESA2 0 0 1 1 3/4 3/4 3/4 3/4 ESA1 0 1 0 1 3/4 3/4 3/4 3/4 DSP block DSP block DSP block DSP block Output DAC block Output DAC block Output DAC block Output DAC block Bank 0 (fs = 44.1 kHz) Bank 1 (off) Bank 2 (fs = 48 kHz) Bank 3 (fs = 32 kHz) fs = 44.1 kHz Off (through) fs = 48 kHz fs = 32 kHz Setting Block Filter Characteristics
3.9
DECI Command
One-byte command to select the decimation filter for delay processing in delay RAM. At a reset, the initial value is 1/3 decimation (CL = 2). This command determines only the decimation filter band. The decimation rate in delay RAM is determined by the OFRAM command value.
Table 3.6
CH 7 7 *7 7 CL 0 1 2 3
DECI Command
Setting Content
1/1 decimation 1/2 decimation 1/3 decimation 1/4 decimation
3.10 ATIME Command
One-byte command to set the compressor block attack time.
Table 3.7
CH 8 8 *8 8 CL 0 1 2 3 ATK1 L L H H ATK0 L H L H
ATIME Command
Attack Time [ms] CB2, 1 = 0, 1 3 6 12 24 CB2, 1 = 1, 0 2 4 8 16 CB2, 1 = 1, 1 1 2 4 8
CB2, 1 = 0, 0 4 8 16 32
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3.11 RTIME Command
One-byte command to set the compressor block release time.
Table 3.8
CH 9 *9 9 9 9 9 9 CL 0 1 2 3 4 5 6 REL1 L L H L H H H REL1 L L L H L L H REL0 L H L H L H L
RTIME Command [s]
Release Time CB2, 1 = 0, 0 1.1 1.6 2.6 4.6 8.7 16.9 33.3 CB2, 1 = 0, 1 0.5 1.0 2.0 4.1 8.2 16.3 32.6 CB2, 1 = 1, 0 0.3 0.7 1.3 2.6 5.2 10.4 20.8 CB2, 1 = 1, 1 0.1 0.3 0.6 1.1 2.2 4.5 9.0
3.12 COMP Command
One-byte command to select the compressor function.
Table 3.9
CH 3 A VCHG
COMP Command
CL 2 CBS 1 CB2 0 CB1
Note 7: At a reset, the initial value is CL = 8H. VCHG: VCHG = "H" selects (turns on) the vocal change function. CBS: Selects the compression ratio. CBS = "L" selects a ratio of 24dB; CBS = "H" selects 36dB (refer to the table) CB2, 1: Used for precise selection of the compression ratio.
Table 3.10
CBS 0 0 0 0 1 1 1 1
Compression Ratio Settings
CB2 0 0 1 1 0 0 1 1 CB1 0 1 0 1 0 1 0 1 Compression Ratio 24dB 18dB 12dB 6dB 36dB 27dB 18dB 9dB
Noise can result when CB2, 1 are used to switch the compression ratio. To switch the ratio without clunking, refer to the software datasheet.
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3.13 ATTA Command
Command to set the digital attenuator level by adding two-byte data. When the lower 14 bits of the data are set to 2000H, the attenuator level is 0dB. The upper two bits are the attenuator time constant selection bits. These bits select the soft mute time constants. When switching using the MUTE or KEYCON command, the value set by ATTA is also valid for the automatic mute function.
Table 3.11
CH B CL 0 DSA2 DSA1 ALA13
ATTA Command
D1 D0 ALA11 ALA10 ALA09 ALA08 ALA07 ~ ALA00
ALA12
Note 8: At a reset, the initial values are DSA = 0H (23 ms) and ALA [13:00] = 2000H (0dB).
The following formula determines the data ALA [13:00] depending on the level (LEVEL [dB]) to be set. ALA [13:00] = 2000H*10^ (LEVEL/20).
Table 3.12
Attenuator Setting Level
Output Level +6.020dB ...... +3.523dB ...... -0.000dB -0.001dB -0.002dB ...... -3.000dB ...... -6.021dB ...... -72.247dB -78.268dB -dB
ALA [13:00] 3FFFH ...... 3000H ...... 2000H 1FFFH 1FFEH ...... 16A7H ...... 1000H ...... 0002H 0001H 0000H
Table 3.13
DSA2 L L H H DSA1 L H L H
Attenuator Time Constants
Time Constant fs = 32 kHz 32 ms 128 ms 256 ms 512 ms fs = 44.1 kHz 23 ms 92 ms 186 ms 372 ms fs = 48 kHz 21 ms 86 ms 171 ms 341 ms
Time required for change from 0dB to -dB.
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3.14 ATTB Command
Command to set the cross fade level for the vibrato function on/off by adding two-byte data. When the lower 14 bits of the data are set to 2000H, the attenuator level is 0dB. The upper two bits are the attenuator time constant selection bits. These bits select the soft mute time constants.
Table 3.14
CH B CL 1 DSB2 DSB1 ALB13
ATTB Command
D1 D0 ALB11 ALB10 ALB09 ALB08 ALB07 ~ ALB00
ALB12
Note 9: At a reset, the initial values are DSB = 0H (23 ms) and ALB [13:00] = 2000H (0dB).
The values are set in the same way as the settings for the ATTA command.
3.15 KEYCON2 Command
Command to set the independent key control right channel or to set the vibrato function by adding two-byte data. Because the initial reset sets ENA to "L", L/R common key control by KEYCON is enabled at an initial reset.
Table 3.15
CH B CL 2 0 0 ENA VIB
KEYCON2 Command
D1 K2R11 K2R10 K2R09 K2R08 K2R07 D0 ~ K2R00
Note 10: At a reset, the initial values are D1 = D2 = 0H. ENA: Set to "H" when using independent key control or vibrato. VIB: Set to "H" when using the vibrato function. K2R [11:00]: When KEYCON2 is used for independent key control, these bits set the key control rate. When KEYCON2 is used to select the vibrato function, these bits set the step value that determines the vibrato cycle.
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Table 3.16 Key Control Set by KEYCON2 (ENA = "H", VIB = "L")
K2R [11:00] 400 1A8 157 10A 0C2 07D 03D D1 24 21 21 21 20 20 20 D0 00 A8 57 0A C2 7D 3D
Amount of Key Shift +1200 cent +600 cent +500 cent +400 cent +300 cent +200 cent +100 cent ...... +50 cent +40 cent +30 cent +20 cent +10 cent -10 cent -20 cent -30 cent -40 cent -50 cent ...... -100 cent -200 cent -300 cent -400 cent -500 cent -600 cent -1200 cent
01E 018 012 00C 006 FFA FF4 FEE FE9 FE3
20 20 20 20 20 2F 2F 2F 2F 2F
1E 18 12 0C 06 FA F4 EE E9 E3
EC7 F90 F50 F2D EFF ED4 E00
2F 2F 2F 2F 2E 2E 2E
C7 90 50 2D FF D4 00
K2R [11:00] = (2^ (N/1200 [cent]) - 1.0) *400H
Table 3.17
Vibrato Cycle Set by KEYCON2 (ENA = "H", VIB = "H")
K2R [11:00] D1 D0
Cycle [Hz] ...... 2 ...... 4 ...... 8 ......
05D
30
5D
0BA
30
BA
175
31
75
K2R [11:00] = N/22500 [Hz] *100000H
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TC9444F
3.16 EXTO Command
Command to set the output data of the extended output port by adding two-byte data. The two-byte data are output in parallel directly from the EXT0 to EXTF pins. The command is used to control the LEDs which display the key control on/off status and the amount of key shift.
Table 3.18
CH B CL 3 EXTF EXTE EXTD EXTC
EXTO Command
D1 EXTB EXTA EXT9 EXT8 EXT7 D0 ~ EXT0
Note 11: At a reset, the initial values are D1 = D0 = 0H.
3.17 CRAM Command
Command to write coefficient RAM data by adding three-byte data. As in the following table, the value of the MSB of the address is assigned to the LSB of the CL bits.
Table 3.19
CH C 0 0 CL 0 AD6 AD5
CRAM Command
D2 AD4 AD3 AD2 AD1 AD0 AD17 AD16 D1
D2 DT15
D1 ~ DT08 DT07
D0 ~ DT00
Note 12: A reset or a boot command sets the coefficient RAM value to its initial value.
The R/W offset addresses of coefficient RAM and delay RAM are written as 18 bits of data. An address consists of three memory allocation bits, three decimation rate bits, and 12 offset address bits. Because the content of these settings depends on the internal program, refer to the separate software datasheet.
Table 3.20
CH C 0 0 CL 0 AD6 AD5
OFRAM Command
D2 AD4 AD3 AD2 AD1 AD0 MAL2 MAL1 D1
D2 MAL0 DECI2 DECI1
D1 DECI0 DTI1 ~ DT08 DT07
D0 ~ DT00
Note 13: A reset or a boot command sets the offset RAM value to its initial value.
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TC9444F
In addition Delay RAM is properly used by MAL [2:0] as RAM of 1024, 2048, and 4096 word, as shown in the following figure.
FFFH 1024 word C00H 1024 word 800H 1024 word 400H 1024 word 000H A B E C G D F
Note 14: Since C block is assigned to Keycontrol R-ch, and D block is assingned to Keycontrol L-ch, it is neseccary to be set to KEY = 0H when using it here.
Figure 3.1
Block Division of Delay RAM
Table 3.21
MAL2 0 0 0 0 1 1 1
Block Assignment and Address Range of Delay RAM
MAL1 0 0 1 1 0 0 1 MAL0 0 1 0 1 0 1 3/4 Block A B C D E F G Address Range 3FFh to 000h 7FFh to 400h BFFh to 800h FFFh to C00h 7FFh to 000h FFFh to C00h FFFh to 000h
Table 3.22
DECI2 0 0 0 0 DECI1 0 0 1 1
Setting of Decimation Ratio
DECI0 0 1 0 1 Decimation Ratio 1/1 1/2 1/3 1/4
The same or overlapping block cannot be accessed by different decimation ratio. Moreover, decimation ratio set up here and decimation ratio set up by DECI command need to be fundamentally made in agreement. DECI bit set up with an offset address determines decimation ratio of memory access, and a setup to DECI command determines the band of a decimation filter.
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TC9444F
3.18 MODE Command
Command to set the IC operating mode by adding one-byte data. This command bundles parameters so that they need be set once only at power-on. The CL bits are also used to make settings.
Table 3.23
CH 3 D 0 2 SYMM2 CL 1 SYMM1 0 RLS 7 OBIT2
MODE Command
D0 6 OBIT1 5 IBIT3 4 IBIT2 3 IBIT1 2 MCKINH 1 DZINH 0 ADPD
Note 15: At a reset, the initial values are SYNM2 = SYNM1 = 0, RLS = 1, D0 = 00H. (master mode, 16-bit input/output) SYNM1, 2: Select sync mode RLS: Selects the channel clock polarity (when RLS = "H" and LRCK = "L" or when RLS = "L" and LRCK = "H", L-channel data selected). OBIT1, 2: Select the digital audio output format. IBIT1, 2, 3: Select the digital audio input format. MCKINH: When "H", disables the MCKO pin output (MCK pin is fixed to low). DZINH: When "H", disables the digital zero detection output (DZ pin is fixed to low). ADPD: When "H", the AD converter power save and output are masked by setting them to digital zeros.
The MCKINH bit is used to halt the XI input clock (or the halved input clock) output from the MCKO pin. The MCKO pin uses a large output buffer for high-speed clock output. However, to suppress unnecessary output without using this pin, set MCKINH to High. A function is supported to forcibly mute the DAC output by checking whether digital data input from the SDI pin are all zeroes and by setting the DZ pin high if all-zero input continues for a specified detection time (Table 2.4). When digital input and analog input are switched, digital input zero detection becomes active, setting the DZ pin to High. The DZINH bit is used to inhibit the DZ pin from going High. Setting the ADPD bit to High halts the AD converter internal circuits and masks the AD converter output by setting to digital zeros. As some circuitry is halted at this time, the power dissipation drops slightly.
4. AD Converter
The TC9444F incorporates a successive approximation 16-bit AD converter with a two times oversampling rate. The AD converter performs three-channel interleave processing for the line input L/R-channels and the microphone input. The microphone input is designed to internally generate an echo effect. The microphone main signal and the microphone echo signal are combined outside the IC. The microphone main signal and the microphone echo component can also be added internally using a microphone through-path in the IC. When not using an AD converter, connect jumpers between the MICI-LPFO1, AIL-LPFO2, and AIR-LPFO3 pins.
5. DA Converter
Incorporates a SD-type modulation 1-bit DA converter and a tertiary analog post filter.
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TC9444F
6. Reset Timing
After turning on the power supply, always perform a reset by setting the /RESET pin to Low. Figure 6.1 shows the reset and boot timing. When performing a power-on reset, note the timing shown in Figure 6.2.
RESET
tRw > 0.2 ms
tBOOT < 50 ms Boot operation completed. Do not write to the coefficient or offset RAM until boot is complete.
Figure 6.1
Reset and Boot
VDD
80%
RESET
40%
tRST > 1 ms
Figure 6.2
Power-On Reset Timing
7. Microcontroller Interface Signal Timing
Microcontroller interface signal timing supports three-lead mode and I2C bus mode.
7.1
Three-Lead Bus Mode
Setting IFSEL = "H" sets the microcontroller interface to three-lead bus mode. Setting the CS signal = "L" enables control from the microcontroller. Figure 7.1 shows the interface timing when three-lead mode is selected. When transmitting two or more commands, be sure to set CS to H between each command. When writing to coefficient or offset RAM, be sure to write the data word by word in 1 fs per word. As coefficient or offset RAM cannot be updated in multiple-word batches, take particular care when updating filter coefficients.
7.2
I C Bus Mode
Setting IFSEL = "L" sets the microcontroller interface to I2C bus mode. In I2C bus mode, the CS pin can be fixed to "L". Note that the CS pin signal can also be used as the chip select signal. The I2C slave address is: MSB LSB 1101 1000 ^^^^^^^^^^^^^ Data can only be written to this address. Therefore, fix the LSB of read/write mode bits to 0. As I2C bus mode does not permit continuous writing, insert an END condition after each command, then a START condition to start writing data again.
2
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TC9444F
T6
Four-Byte Commands
T1
T2 T3
T4
T5
CS
SCL d.c. DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 d.c. DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 d.c. DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0 d.c.
SDA
d.c.
C7
C6
C5
C4
C3
C2
C1
C0
d.c.: don't care
T7
When consecutively transmitting two or more commands:
T1 > 0.2 ms: Interface setup time T2 > 0.2 ms: Shift clock "L" time T3 > 0.2 ms: Shift clock "H" time
d.c. When transmitting two or more commands, be sure to set CS to "H" between the commands. DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 d.c. C7 C6 C5 C4 C3 C2 C1 C0 d.c.
CS
SCL
SDA
d.c.
C7
C6
C5
C4
C3
C2
C1
C0
T4 > 0.2 ms: Data setup time T5 > 0.2 ms: Data hold time T6 > 0.2 ms: Interface hold time T7 > 0.2 ms: CS signal "H" duration
T8
CSN Coefficient data 2 transmitted Write the data to coefficient or offset RAM word by word in 1 fs per word.
Coefficient data 1 transmitted
T8 > 1/fs: Coefficient, offset RAM write cycle
Figure 7.1
Three-Lead Interface Timing (IFSEL = "H")
Two-Byte Commands
Fixed to "L" (usable as chip select)
CS
SCL CM7 CM6 CM5 CM4 CM3 CM2 CM1 CM0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
SDA
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
When transmitting multiple commands
SCL CM7 CM6 CM5 CM4 CM3 CM2 CM1 CM0 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 CM7 CM6 CM5 CM4 CM3 CM2 CM1 CM0
SDA
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
Insert an END condition after each command, then transmit a START condition followed by ID.
Figure 7.2
I C Interface Timing (IFSEL = "L")
2
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TC9444F
8. Digital Data Input/Output Timing
Rising Edge, Falling Edge
90% MCKO tr tf 10% LRCKO BCKO SDO tr tf 90% 10%
Master Clock
The MCKO pin outputs the XI input clock or the XI input clock divided by two.
XI
MCKO when MCKS = "H" MCKO when MCKS = "L" td1
td1
SDO Output
SDO is output on the BCKO falling edge with both internal and external synchronization.
BCKO SDO td2
Master Mode
BCKO and LRCKO are divided from the XI input clock.
At 512 fs XI
BCKO td3 LRCKO td4
Slave Mode
At 512 fs XI
LRCKI Synchronization width BCKI
BCO tdls LRCKI
LRCKO td6
Data Input
LRCKI tLRh BCKI tLRs
SDI tDls tDlh
Figure 7.3
Digital Data Input/Output Timing 23 2002-01-11
TC9444F
Maximum Ratings (Ta = 25C)
Characteristics Power supply voltage Input voltage Power dissipation Operating temperature Storage temperature Symbol VDD Vin PD Topr Tstg Rating -0.3 to 6.0 -0.3 to VDD + 0.3 500 -40 to 85 -55 to 150 Unit V V mW C C
Electrical Characteristics (unless otherwise specified, Ta = 25C, VDD = 5.0 V)
DC Characteristics
Characteristics Operating voltage Current consumption "H" level Input voltage "L" level "H" level Input current "L" level Output current 1 "H" level VIL IIH IIL IOH1 IOL1 IOH2 IOL2 Rup 3/4 Digital input pins When VOH = 4.5 V When VOH = 0.5 V When VOH = 4.5 V When VOH = 0.5 V
RESET , TEST pin
Symbol VDD IDD VIH
Test Circuit 3/4 3/4
Test Condition Ta = -40 to 85C XI = 16.9 MHz, 384 fs mode
Min 4.5 3/4 VDD 0.8 0 3/4 -1.0 -2.0 3/4 -4.0 3/4 3/4
Typ. 5.0 57 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 50
Max 5.5 80 3/4
Unit V mA
3/4
Digital input pins
V VDD 0.2 1.0 3/4 3/4 2.0 3/4 4.0 3/4 kW mA mA
(Note 16) "L" level Output current 2 "H" level
3/4
mA
(Note 17) "L" level Pull-up resistors
3/4 3/4
Note 16: DZ, EXT0 to F, LRCKO, BCKO, SDO, SDA pins In I C bus mode, the SDA pin is "L" output only (open drain). Note 17: MCKO pin
2
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TC9444F
AC Characteristics
AD Converter
Characteristics Maximum input level S/(N + D) ratio THD + N Crosstalk Symbol Ain S/N (AD) THD (AD) CT (AD) Test Circuit 1 1 1 1 Test Condition VDD = 5.0 V -50dB, 1 kHz sine wave input -0dB, 1 kHz sine wave input 3/4 Min 3/4 72 3/4 3/4 Typ. 1.15 80 -65 -68 Max 1.20 3/4 -57 -60 Unit Vrms dB dB dB
DA Converter
Characteristics Output level S/N ratio THD + N Crosstalk CT (DA) 1 Symbol Aout S/N (DA) THD (DA) THD (DA) Test Circuit 1 1 1 1 Test Condition 3/4 -30dB, 1 kHz sine wave input -0dB, 1 kHz sine wave input -0dB, 10 kHz sine wave input 3/4 Min 3/4 84 3/4 3/4 3/4 Typ. 1.2 93 -86 -83 -90 Max 3/4 3/4 -78 -75 -82 Unit Vrms dB dB dB
Timings
Characteristics Symbol Test Circuit 3/4 Test Condition CL = 50 pF, LRCKO, BCKO, SDO MCKO 3/4 CL = 50 pF, LRCKO, BCKO, SDO MCKO Common td1 td2 Delay time In master mode td3 td4 In slave mode SDI setup time SDI hold time LRCKI setup time LRCKI hold time Interface setup time Interface shift clock pulse width Interface data setup time Interface data hold time Interface hold time Interface CS signal "H" duration Coefficient and offset RAM write cycle Power-on reset time Reset pulse width Boot time td5 td6 tDIs tDIh tLRs tLRh T1 T2, T3 T4 T5 T6 T7 T8 tRST tRw tBOOT 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 XI (R) MCKO BCKO (R) SDO XI (R) BCKO XI (R) LRCKO BCKI (R) BCKO LRCKI (R) LRCKO 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Time required for boot Min 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 50 50 50 50 0.2 0.2 0.2 0.2 0.2 0.2 1/fs 1 0.2 3/4 Typ. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Max 30 20 30 ns 20 20 5 15 ns 30 30 30 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 50 ns ns ns ns ms ms ms ms ms ms s ms ms ms Unit
Rise time
tr
ns
Fall time
tf
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2002-01-11
TC9444F
Microcontroller interface Anritsu MG22A SDA SCL CS RST GND 60 EMP SDA SCL CS EXT9 EXT8 EXT7 EXTB EXTC EXTA TEST IFSEL VDD2 59 58 57 56 55 54 53 52 51 50 49 48 47 46 Digital data input MCKO BCKI 44 SDI 43 0.1 mF LRCKO 42 BCKO 41 SDO 40 VDD1 39 TC9444F MCKO 38 MCKS 37 0.1 mF CKS 36 EXT6 35 EXT5 34 EXT4 33 0.1 mF 0.1 mF 0.1 mF EXT3 32 EXT2 31 XO XI GNDX GNDD1 EXT0 EXT1 0.1 mF 2 1Y 3 1A 4 2Y 5 2A 6 3Y 7 3A 8 GND 1 VCC NC 16 6Y 15 6A 14 NC 13 5Y 12 5A 11 4Y 10 4A 9 Digital data input SDO SDI BCKI LRCKI 2 EXTE 0.1 mF 3 EXTF 4 GNDL 5 VDL 6 VDA1 7 LPFO1 8 MICI 9 VRA1 10 AIL 11 LPFO2 12 VRA2 13 LPFO3 14 AIR 15 GNDA1 VRR AOR DZ GNDAL AOL VRL VDA2 VDX GNDAR 0.1 mF GNDD2 RESET 1 EXTO LRCKI 45
Test Circuit
Shibasoku AM51A Analog input Analog output
400 Hz HPF 20 kHz LPF 30 kHz HPF
MIC in
1200 pF
51 W 560 pF
L-ch in
3.3 mF
10 kW
10 kW
1200 pF
51 W 560 pF
R-ch in
3.3 mF
10 kW
10 kW
1200 pF
51 W 560 pF
220 pF
10 kW
220 pF
10 kW
220 pF
10 kW
47 mF
47 mF
L-ch out
470 W 47 mF 47 mF
3.3 mF
16
17
18
19
20
21
22
23
24
25 16.9 MHz 33 pF
26
27
28
29
30
10 kW
2200 pF
100 mF 100 mF
R-ch out
470 W
3.3 mF
10 kW
2200 pF
26
33 pF
TC4HC4050AP
3.3 mF
10 kW
10 kW
2002-01-11
TC9444F
Package Dimensions
Weight: 1.08 g (typ.)
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TC9444F
RESTRICTIONS ON PRODUCT USE
000707EBA
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
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2002-01-11
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