View AS7C164_307221.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

0D\
$6&
9 .[ &026 65$0 )HDWXUHV
* AS7C164 (5V version) * Commercial temperature * Organization: 8,192 words x 8 bits * Center power and ground pins * High speed - 12/15/20 ns address access time - 6/7/8 ns output enable access time * Low power consumption: ACTIVE - 550 mW (AS7C164) / max @ 12 ns
* Low power consumption: STANDBY - 11 mW (AS7C164) / max CMOS I/O * 2.0V data retention * Easy memory expansion with CE1, CE2, OE inputs * TTL-compatible, three-state I/O * 28-pin JEDEC standard package - 300 mil SOJ * ESD protection 2000 volts * Latch-up current 200 mA
/RJLF EORFN GLDJUDP
VCC GND Input buffer A1 A2 A3 A4 A10 A11 A12 I/O7
3LQ DUUDQJHPHQW
28-pin PDIP, SOJ (300 mL)
I/O0 Column decoder AAAAAA 056789 WE OE CE1 CE2
Control circuit
6HOHFWLRQ JXLGH
-12 Maximum address access time Maximum output enable access time Maximum operating current Maximum CMOS standby current 12 6 110 2.0 -15 15 7 100 2.0 -20 20 8 90 2.0 Unit ns ns mA mA
Y
$OOLDQFH 6HPLFRQGXFWRU
AS7C164
128x64x8 Array (65,536)
NC A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
Vcc WE CE2 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3
Row decoder
Sense amp
RI
&RS\ULJKW $OOLDQFH 6HPLFRQGXFWRU $OO ULJKWV UHVHUYHG
$6&
)XQFWLRQDO GHVFULSWLRQ
The AS7C164 is a high performance CMOS 65,536-bit Static Random Access Memory (SRAM) device organized as 8,192 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 12/15/20 ns with output enable access times (tOE) of 6/7/8 ns are ideal for high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank memory systems. When CE1 is High or CE2 is Low the device enters standby mode. The standard AS7C164 is guaranteed not to exceed 11.0 mW power consumption in standby mode, and typically requires only 250 W; it offers 2.0V data retention with maximum power of 120 W. A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0-I/O7 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) High. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply. The AS7C164 is packaged in 300 mil SOJ packages.
$EVROXWH PD[LPXP UDWLQJV
Parameter Voltage on VCC relative to GND Voltage on any pin relative to GND Power dissipation Storage temperature (plastic) Ambient temperature with VCC applied DC current into outputs (low) Device AS7C164 Symbol Vt1 Vt2 PD Tstg Tbias Iout Min -0.50 -0.50 - -65 -55 - Max +7.0 VCC + 0.50 1.0 +150 +125 20 Unit V V W
oC oC
mA
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
7UXWK WDEOH
CE1 H X L L L CE2 X L H H H WE X X H H L OE X X H L X Data High Z High Z High Z Dout Din Mode Standby (ISB, ISB1) Standby (ISB, ISB1) Output disable (ICC) Read (ICC) Write (ICC)
Key: X = Don't Care, L = Low, H = High
Y
$OOLDQFH 6HPLFRQGXFWRU
RI
$6&
5HFRPPHQGHG RSHUDWLQJ FRQGLWLRQV
Parameter Supply voltage Input voltage Ambient operating temperature
* VIL min = -3.0V for pulse width less than tRC/2.
Device AS7C164 AS7C164 AS7C164
Symbol VCC VIH VIL TA
Min 4.5 2.2 -0.5* 0
Typical 5.0 - - -
Max 5.5 VCC+1 0.8 70
Unit V V V
oC
'& RSHUDWLQJ FKDUDFWHULVWLFV RYHU WKH RSHUDWLQJ UDQJH
-12 Parameter Input leakage current Symbol
|ILI| |ILO|
-15
-20
Test Conditions VCC = Max, VIN = GND to VCC VCC = Max, CE1 = VIH or CE2 = VIL, VOUT = GND to VCC VCC = Max, CE1 = VIL, CE2 = VIH, f = fMax, IOUT = 0 mA VCC = Max, CE1 = VIH or CE2 = VIL, f = fMax VCC = Max, CE1 VCC-0.2V or CE2 0.2V, VIN 0.2V or VIN VCC-0.2V, f = 0 IOL = 8 mA, VCC = Min IOH = -4 mA, VCC = Min
Device
Min Max Min Max Min Max Unit - 1 - 1 - 1 A
Output leakage current
-
1
-
1
-
1
A
Operating power supply current
ICC
AS7C164
-
110
-
100
-
90
mA
ISB Standby power supply current ISB1
AS7C164
-
30
-
25
-
25
mA
AS7C164
-
2.0
-
2.0
-
2.0
mA
Output voltage
VOL VOH
- 2.4
0.4 -
- 2.4
0.4 -
- 2.4
0.4 -
V V
&DSDFLWDQFH I 0+] 7D R & 9&&
Parameter Input capacitance I/O capacitance Symbol CIN CI/O Signals
120,1$/
Test conditions Vin = 0V Vin = Vout = 0V I/O Max 5 7 Unit pF pF
A, CE1, CE2, WE, OE
Y
$OOLDQFH 6HPLFRQGXFWRU
RI
$6&
5HDG F\FOH RYHU WKH RSHUDWLQJ UDQJH
-12 Parameter Read cycle time Address access time Chip enable (CE1) access time Chip enable (CE2) access time Output enable (OE) access time Output hold from address change CE1 Low to output in low Z CE2 High to output in low Z CE1 High to output in high Z CE2 Low to output in high Z OE Low to output in low Z OE High to output in high Z Power up time Power down time Symbol tRC tAA tACE1 tACE2 tOE tOH tCLZ1 tCLZ2 tCHZ1 tCHZ2 tOLZ tOHZ tPU tPD Falling input Min 12 - - - - 3 3 3 - - 0 - 0 - Max - 12 12 12 6 - - - 3 3 - 3 - 12 Min 15 - - - - 3 3 3 - - 0 - 0 - -15 Max - 15 15 15 7 - - - 4 4 - 4 - 15 Min 20 - - - - 3 3 3 - - 0 - 0 - -20 Max - 20 20 20 8 - - - 5 5 - 5 - 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 4, 5, 12 4, 5, 12 4, 5, 12 4, 5, 12 4, 5 4, 5 4, 5, 12 4, 5, 12 3 3, 12 3, 12 Notes
.H\ WR VZLWFKLQJ ZDYHIRUPV
Rising input Undefined/don't care
5HDG ZDYHIRUP DGGUHVV FRQWUROOHG
tRC Address tAA DOUT Data valid tOH
5HDG ZDYHIRUP &( DQG &( FRQWUROOHG
tRC1 CE1 CE2 tOE OE tOLZ tACE1, tACE2 DOUT tCLZ1, tCLZ2 Supply current tPU 50% Data valid tPD 50% ICC ISB tOHZ tCHZ1, tCHZ2
Y
$OOLDQFH 6HPLFRQGXFWRU
RI
$6&
:ULWH F\FOH RYHU WKH RSHUDWLQJ UDQJH
-12 Parameter Write cycle time Chip enable (CE1) to write end Chip enable (CE2) to write end Address setup to write end Address setup time Write pulse width Write recovery time Address hold from write end Data valid to write end Data hold time Write enable to output in high Z Output active from write end Symbol tWC tCW1 tCW2 tAW tAS tWP tWR tAH tDW tDH tWZ tOW Min 12 9 9 9 0 8 0 0 6 0 - 3 Max - - - - - - - - - - 5 - Min 15 10 10 10 0 9 0 0 7 0 - 3 -15 Max - - - - - - - - - - 5 - Min 20 12 12 12 0 12 0 0 8 0 - 3 -20 Max - - - - - - - - - - 5 - Unit ns ns ns ns ns ns ns ns ns ns ns ns 4, 5 4, 5 4, 5 12 12 12 Notes
:ULWH ZDYHIRUP :( FRQWUROOHG
tWC tAW Address tWP WE tAS DIN tWZ DOUT tDW Data valid tOW tDH tWR tAH
:ULWH ZDYHIRUP &( DQG &( FRQWUROOHG
tWC tAW Address tAS CE1 CE2 tWP WE tWZ DIN DOUT tDW Data valid tDH tCW1, tCW2 tWR tAH
Y
$OOLDQFH 6HPLFRQGXFWRU
RI
$6&
'DWD UHWHQWLRQ FKDUDFWHULVWLFV RYHU WKH RSHUDWLQJ UDQJH
Parameter VCC for data retention Data retention current Chip enable to data retention time Operation recovery time Symbol VDR ICCDR tCDR tR Test conditions VCC = 2.0V CE1 VCC-0.2V or CE2 0.2V Min 2.0 - 0 tRC Max - 60 - - Unit V A ns ns
'DWD UHWHQWLRQ ZDYHIRUP
Data retention mode VCC VCC tCDR CE1 CS2 VIH VIH tCDR VDR VIH VIH tR VDR 2.0V VCC tR
VDR
$& WHVW FRQGLWLRQV
Output load: see Figure B or Figure C. Input pulse level: GND to 3.0V. See Figure A. Input rise and fall times: 2 ns. See Figure A. Input and output timing reference levels: 1.5V.
DRXW 255 Thevenin Equivalent: 168 DRXW +1.728V (5V) +5V 480 +3.0V GND 90% 10% 2ns 90% 10% C(14) GND Figure B: 5V Output loDG DRXW 255 +5V 320 C(14)
Figure A: Input pulse
GND Figure C: 3.3V Output load
1RWHV
1 2 3 4 5 6 7 8 9 10 11 12 13 14 During VCC power-up, a pull-up resistor to VCC on CE1 is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions, Figures A, B, and C. tCLZ and tCHZ are specified with CL = 5pF as in Figures B or C. Transition is measured 500mV from steady-state voltage. This parameter is guaranteed, but not 100% tested. WE is High for read cycle. CE1 and OE are Low and CE2 is High for read cycle. Address valid prior to or coincident with CE1 transition Low and CE2 transition High. All read cycle timings are referenced from the last valid address to the first transitioning address. CE1 or WE must be High or CE2 Low during address transitions. Either CE or WE asserting high terminates a write cycle. All write cycle timings are referenced from the last valid address to the first transitioning address. CE1 and CE2 have identical timing. 2V data retention applies to the commercial operating range only. C = 30pF, except on High Z and Low Z parameters, where C = 5pF.
Y
$OOLDQFH 6HPLFRQGXFWRU
RI
$6&
7\SLFDO '& DQG $& FKDUDFWHULVWLFV
Normalized supply current ICC, ISB vs. supply voltage VCC Normalized supply current ICC, ISB vs. ambient temperature Ta Normalized ISB1 (log scale) 625 25 5 1 0.2 Normalized supply current ISB1 vs. ambient temperature Ta
1.4 1.2 Normalized ICC, ISB 1.0 0.8 0.6 0.4 0.2
1.4 1.2 Normalized ICC, ISB
ICC
1.0 0.8 0.6 0.4 0.2
ICC
VCC = VCC(NOMINAL)
ISB
ISB
0.04 -55 -10 35 80 125 Ambient temperature (C)
0.0 MIN
NOMINAL Supply voltage (V) Normalized access time tAA vs. supply voltage VCC
MAX
0.0 -55
-10 35 80 125 Ambient temperature (C) Normalized access time tAA vs. ambient temperature Ta
1.5 1.4 Normalized access time 1.3 1.2 1.1 1.0 0.9 0.8 MIN
1.5 1.4 Normalized access time
1.4 1.2
Normalized supply current ICC vs. cycle frequency 1/tRC, 1/tWC VCC = VCC(NOMINAL) Ta = 25C
Ta = 25C
1.2 1.1 1.0 0.9 0.8 -55 -10 35 80 125 Ambient temperature (C) Output sink current IOL vs. output voltage VOL
Normalized ICC
1.3
VCC = VCC(NOMINAL)
1.0 0.8 0.6 0.4 0.2 0.0 0
NOMINAL Supply voltage (V) Output source current IOH vs. output voltage VOH
MAX
25 50 75 Cycle frequency (MHz)
100
Typical access time change tAA vs. output capacitive loading 35 30 Change in tAA (ns) VCC = VCC(NOMINAL)
140 Output source current (mA) 120 100 80 60 40 20 0 0
140 Output sink current (mA) 120 100 80 60 40 20 0 VCC 0
VCC = VCC(NOMINAL)PL Ta = 25C
VCC = VCC(NOMINAL) Ta = 25C
25 20 15 10 5 0
VCC Output voltage (V)
0
Output voltage (V)
250 500 750 Capacitance (pF)
1000
Y
$OOLDQFH 6HPLFRQGXFWRU
RI
$6&
3DFNDJH GLPHQVLRQV
300 mil 28-pin SOJ
'
H
% $ E
( (
$
Seating Plane
3LQ $ (
F
A A1 A2 B b c D E E1 E2 e
28-pin SOJ in mil Min Max 0.140 0.025 0.095 0.105 0.028 TYP 0.018 TYP 0.010 TYP 0.730 0.245 0.285 0.295 0.305 0.327 0.347 0.050 BSC
2UGHULQJ FRGHV
Package\ Access time Plastic SOJ\300 mL Volt/Temp 5V commercial 12 ns AS7C164-12JC 15 ns AS7C164-15JC 20 ns AS7C164-20JC
3DUW QXPEHULQJ V\VWHP
AS7C SRAM prefix 164 Device number X Blank = Standard power -XX Access time J=SOJ 300 mil X Package code: C Commercial temperature range, 0C to 70C
Y
$OOLDQFH 6HPLFRQGXFWRU
RI
(c) Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use

▲Up To Search▲

Price & Availability of AS7C164

	To Download AS7C164 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .