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| Ordering number : EN*5236 CMOS LSI LC78845Q Sample Rate Converter for Digital Audio Preliminary Overview The LC78845Q is a synchronous sample rate converter for digital audio signals. Package Dimensions unit: mm 3156-QFP48E [LC78845Q] Features * Converts data sampled at 32 or 48 kHz to 44.1-kHz sampled data. * Passes 44.1-kHz sampled data trough without change. * Supports 384fs and 512fs system clock rates. * 8x oversampling filters * Soft muting function * Built-in PLL circuit SANYO: QIP48E Specifications Absolute Maximum Ratings at Ta = 25C Parameter Maximum supply voltage I/O voltages Operating temperature Storage temperature Symbol VDD max VI, VO Topr Tstg Conditions Ratings -0.3 to +7.0 -0.3 to VDD + 0.3 -30 to +70 -55 to +125 Unit V V C C DC Characteristics Parameter Input voltage range Input high-level voltage Input low-level voltage Output high-level voltage Output low-level voltage Symbol VIN VIH VIL VOH VOL IOH = -1 A IOL = 1 A VDD - 0.05 VSS + 0.05 Ta = -30 to +70C Conditions min 0 0.7 VDD 0.3 VDD typ max VDD Unit V V V V V This LSI can easily use CCB that is SANYO's original bus format. * CCB is a trademark of SANYO ELECTRIC CO., LTD. * CCB is SANYO's original bus format and all the bus addresses are controlled by SANYO. SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN 22896HA (OT) No. 5236-1/10 LC78845Q AC Characteristics 1. Audio data input Parameter BCLKI pulse width DATAI setup time DATAI hold time LRCKI hold time LRCKI setup time Symbol tBKW tDS tDH tLH tLS Conditions min 50 20 20 25 25 typ max Unit ns ns ns ns ns 2. Audio data output Parameter BCLKO pulse width DATAO output delay time DATAO setup time DATAO hold time LRCKO output delay time LRCKO setup time LRCKO hold time WCLKO setup time WCLKO hold time Symbol tBWO tDAD tDSO tDHO tLRD tLSO tLHO tWSO tWHO 50 50 50 50 50 50 25 Conditions min 100 25 typ max Unit ns ns ns ns ns ns ns ns ns No. 5236-2/10 LC78845Q 3. Serial input (CCB = low) Parameter CL pulse width DI setup time DI hold time CE pulse width CE setup time CE hold time DO0 to DO7 output delay time Symbol tCLW tDS tDH tCEW tCS tCH tDOD Conditions min 50 20 20 50 20 20 25 typ max Unit ns ns ns ns ns ns ns 4. Serial input (CCB = high) Parameter CL pulse width DI setup time DI hold time CE setup time CE hold time DO0 to DO7 output delay time with respect to the rise of CE Symbol tCLW tDS tDH tCS tCH tDOD Conditions min 50 20 20 20 20 25 typ max Unit ns ns ns ns ns ns No. 5236-3/10 LC78845Q Pin Assignment Although the DVDD and AVDD pins in this IC are given different names to correspond to the internal circuit structure, they are connected internally through the circuit substrate. As a result, if different voltages are applied to these pins, abnormal currents will flow in the chip. Since this can cause latchup, power supplies with identical voltages and identical power-on timings must be used. Pin Functions Pin No. 1 2 3 4 5 6 7 8 9 10 Symbol MKSEL INITB MCK1 BCLKI DGND DGND DVDD LRCKI DATAI CCB Overview DF master clock selection Reset input DF master clock input Audio signal input Digital system ground Digital system ground Digital system power supply Audio signal input Audio signal left/right clock and data input pins Audio signal bit clock input pin Low: 384fs, high: 512fs Low: initialization operation Function Serial input format specification Selects the input format for data from the microprocessor input pins. 11 SPSEL Serial/parallel control Allows certain of the setting pins to be set from serial data over the microprocessor interface. Low: serial, high: parallel (states set by input pins) Continued on next page. No. 5236-4/10 LC78845Q Continued from preceding page. Pin No. 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Symbol CE CL DI DO7 DO6 DO5 DGND DVDD DO4 DO3 DO2 DO1 DO0 DATAO LRCKO WCLKO BCLKO DGND N.C AGND VCO VIN R STOP UNLK MCK2 AVDD AVDD MUTE FSEL3 TEST1 DVDD DVDD FSEL2 FSEL1 TEST2 TEST3 Analog system ground PLL control PLL control PLL control Oscillator stop signal input Unlock detection output Synchronization clock output Analog system power supply Analog system power supply Muting Output data fs selection Test pin Digital system power supply Digital system power supply Input signal fs selection Selects the fs for the input signal. Low: muting off, high: muting on Low: fs data, high: 2fs data Must be held low during normal operation. Low-pass filter connection Free-running setting VCO band adjustment Low: oscillator stopped, high: PLL running Outputs a high level when the PLL circuit is unlocked. Outputs the clock generated by the VCO. Digital system ground -- Audio signal output Audio signal outputs (data, left/right clock, word clock, and bit clock) Parallel data output Output of 8-bit parallel data according to microprocessor input Digital system ground Digital system power supply Parallel data output Output of 8-bit parallel data according to microprocessor input Microprocessor input pins Overview Data enable signal input Shift clock input Address/data input Function Test pins Must be held low during normal operation. No. 5236-5/10 LC78845Q Block Diagram Note: 1. 2. 3. 4. 5. BCLKI, LRCKI, DATAI BCLKO, LRCKO, DATAO, WCLKO R, VIN, VCO, UNLK MKSEL, FSEL1, FSEL2, MUTE, STOP CCB, SPSEL, CE, CL, DI No. 5236-6/10 LC78845Q Input and Output Formats 1. Input format Audio data is input through the audio data input pins (BCLKI, LRCKI, and DATAI) in the following format. MKSEL = L: fBCK = 48fs MKSEL = H: fBCK = 64fs 2. Output format 1 Audio data is output through the audio data output pins (BCLKO, WCLKO, LRCKO, and DATAO) in the following format. BCLKO = 64fs (fixed) LRCKO = fs (fixed) WCLKO = 2fs (fixed) 3. Output format 2 (When the input fs is 44.1 kHz) When data sampled at 44.1 kHz is input, that data is output directly without change. The WCLKO output is held low in this case. No. 5236-7/10 LC78845Q Pin Settings 1. Input master clock setup (when SPSEL is high) Input the master clock for the internal digital filters to MCK1 (pin 3). Also, set whether that clock is 384fs or 512fs with MKSEL (pin 1). Pin MKSEL L 384fs H 512fs 2. Input data fs setting (when SPSEL is high) The input data sampling frequency must be set. FSEL1 and FSEL2 (pins 46 and 45) are used for this setting. Data sampled at a 32 or 48 kHz sampling frequency is converted to data with a 44.1 kHz sampling frequency. If data sampled at 44.1 kHz is input, it is passed through unchanged. Sampling frequency 44.1 kHz 48 kHz 32 kHz FSEL1 0 1 1 FSEL2 0 1 3. Output data setup The output data can be switched between fs and 2fs. FSEL3 (pin 41) is used to change this setting. Pin FSEL3 L fs H 2fs 4. Setup from serial input The MKSEL, FSEL1, FSEL2, MUTE, and STOP settings can be set using the serial bus by setting SPSEL (pin 11) low. The 8 bits of input data is output in parallel regardless of the SPSEL setting. Serial input format 1 (CCB = high) Serial input format 2 (CCB = low) No. 5236-8/10 LC78845Q INITB = H SPSEL = L LSI selection Address MKSEL FSEL1 FSEL2 MUTE STOP -- Data B0 to B3 A0 to A3 D0 D1 D2 D3 D4 D5 to D7 INITB = L -- -- L L L H L H The data and the signals correspond as listed in the tables. Since the external pins (MKSEL etc.) set by the serial input are unused, applications must assure that these pins do not become floating. If initialization is performed, set the initial values listed in the table. 5. Muting A soft muting function is applied to the data if the MUTE pin (pin 40) is set high when data with a 32 or 48 kHz sampling frequency is input. The input signal values are gradually attenuated so that the data reaches - 1024/fs (seconds) later. When the soft muting function is turned off, the amplitude becomes the same as that of the input 1024/fs (seconds) later. For input data with a 44.1 sampling frequency, the data is forcibly set to 0 on the next rising edge of the LRCK signal after the MUTE signal goes from low to high. Similarly, data is output on the next rising edge of the LRCK signal after the MUTE signal goes from high to low. 6. Initialization When power is first applied, the LSI must be initialized when the pin settings are changed. Initialization is performed by holding INITB (pin 2) low for at least 1 s in the state where the MCK1 signal is input after the power supply voltage has stabilized. No. 5236-9/10 LC78845Q 7. PLL block The PLL block generates a 14.112 MHz master clock (MCK2) that is used for all three frequencies; 32, 44.1, and 48 kHz, when either 32 or 48 kHz is specified as the input data sampling frequency. * STOP pin setting STOP L H The VCO is stopped. The VCO operates. Function * UNLK pin UNLK L H Function Indicates that the PLL circuit is locked. Indicates that the PLL circuit is in the unlocked state. The UNLK pin is high during unlocked periods and during the 1024/fs (seconds) required for the unlocked to locked transition. The LSI performs the same processing during the locked to unlocked transition as it does when MUTE is high. * External circuits Symbol R1 R2 R3 R4 C1 C2 Value 150 5.1 k 5.1 k 24 k 0.02 0.1 F Unit s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 1996. Specifications and information herein are subject to change without notice. PS No. 5236-10/10 |
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