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Product Preview OCTAL TRANSCEIVER/REGISTER WITH 3-STATE OUTPUTS These devices consist of bus transceiver circuits with 3-state D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a high logic level. Output Enable (OE) and DIR pins are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or the B register or in both. The select controls can multiplex stored and real-time (transparent mode) data. The direction control determines which bus will receive data when the enable OE is Active LOW. In the isolation mode (OE HIGH), A data may be stored in the B register and/or B data may be stored in the A register. MC54/74F646 MC54/74F648 OCTAL TRANSCEIVER/REGISTER WITH 3-STATE OUTPUTS FASTTM SCHOTTKY TTL * * * * Independent Registers for A and B Multiplexed Real-Time and Stored Data Choice of True (F646) and Inverting (F648) Data Paths 3-State Outputs PIN ASSIGNMENTS VCC CPBA SBA 24 23 22 OE 21 B0 20 B1 19 B2 18 B3 17 B4 16 B5 15 B6 14 B7 13 24 1 J SUFFIX CERAMIC CASE 758-01 F646 24 1 N SUFFIX PLASTIC CASE 724-03 1 2 3 4 A0 OE 21 5 A1 B0 20 6 A2 B1 19 7 A3 B2 18 8 A4 B3 17 9 A5 B4 16 10 A6 B5 15 11 12 CPAB SAB DIR VCC CPBA SBA 24 23 22 A7 GND B6 14 B7 13 24 1 DW SUFFIX SOIC CASE 751E-03 F648 ORDERING INFORMATION MC54FXXXJ Ceramic MC74FXXXN Plastic MC74FXXXDW SOIC 1 2 3 4 A0 5 5 A1 6 A2 6 A2 7 A3 8 A4 7 A3 9 A5 8 A4 10 A6 9 A5 11 A7 10 A6 11 12 CPAB SAB DIR 4 A7 GND 4 5 6 A2 7 A3 8 A4 9 A5 10 A6 11 A7 LOGIC SYMBOLS 1 2 3 23 22 21 A A1 CPAB 0 SAB DIR CPBA SBA OE B0 B1 20 19 F646 B2 18 B3 B4 17 16 B5 B6 15 14 B7 13 1 2 3 23 22 21 A A1 CPAB 0 SAB DIR CPBA SBA OE B0 B1 20 19 F648 B2 18 B3 B4 17 16 B5 B6 15 14 B7 13 This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. FAST AND LS TTL DATA 4-395 MC54/74F646 * MC54/74F648 FUNCTION TABLE Inputs OE bar H H H H L L L L L L L L DIR X X X X H H H H L L L L CPAB H or L X X H or L X X X X CPBA H or L X X X X X X H or L SAB X X X X L L H H X X X X SBA X X X X X X X X L L H H Data I/O* Operation/Function A0-A7 Input Input Input Input Input Input Input Input Output Output Output Output B0-B7 Input Input Input Input Output Output Output Output Input Input Input Input Isolation Store An Data in A Register Store Bn Data in B Register Store An/Bn Data in A/B Register An to Bn -- Real Time (Transparent Mode) Store An Data in A Register A Register to Bn (Stored Mode) Clock An Data to Bn and into A Register Bn to An -- Real Time (Transparent Mode) Store Bn Data in B Register B Register to An (Stored Mode) Clock An Data to Bn and into B Register *The data output function may be enabled or disabled by various signals at the OE bar and DIR inputs. Data input functions are always enabled; i.e., data at the *bus pins will be stored on every low-to-high transition of the appropriate clock inputs. H = HIGH voltage level L = LOW voltage level X = Don't Care = Low-to-High transition GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter DC Supply Voltage Operating Ambient Temperature Range Output Current High Output Current Low 54, 74 54 74 54 74 54 74 Min 4.5 -55 0 -- -- -- -- Typ 5.0 25 25 -- -- -- -- Max 5.5 125 70 -12 -15 48 64 Unit V C mA mA FAST AND LS TTL DATA 4-396 MC54/74F646 * MC54/74F648 LOGIC DIAGRAM F646 OE DIR CPBA SBA SAB CPAB 1 OF 8 CHANNELS C0 A0 D0 B0 D0 C0 TO 7 OTHER CHANNELS FAST AND LS TTL DATA 4-397 MC54/74F646 * MC54/74F648 LOGIC DIAGRAM F648 OE DIR CPBA SBA SAB CPAB 1 OF 8 CHANNELS C0 A0 D0 B0 D0 C0 TO 7 OTHER CHANNELS FAST AND LS TTL DATA 4-398 MC54/74F646 * MC54/74F648 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage 54/74 74 VOH Output HIGH Voltage An, Bn 54 74 54 VOL Output LOW Voltage An, Bn 74 Non I/O Pins IIH Input HIGH Current Non I/O Pins I/O (Aa, Bn) IIL IIH + IOZH IIL + IOZL IOS Input LOW Current Output Leakage Current Output Leakage Current Output Short Circuit Current (Note 2) ICCH ICC Power Supply Current ICCL ICCZ Non I/O Pins I/O (An, Bn) I/O (An, Bn) Parameter Min 2.0 -- -- 2.4 2.7 2.0 2.0 -- -- -- -- -- -- -- -- -100 -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- 0.8 -1.2 -- -- -- -- 0.55 0.55 20 100 1.0 -600 70 -650 -225 135 150 150 mA Unit V V V V V V V V V A A mA A A A mA Test Conditions (Note 1) Guaranteed as a HIGH Signal Guaranteed as a LOW Signal VCC = MIN, IIN = -18 mA IOH = -3.0 mA IOH = -3.0 mA IOH = -12.0 mA IOH = -15.0 mA IOL = 48 mA IOL = 64 mA VCC = 4.5 V VCC = 4.75 V VCC = 4.5 V VCC = 4.5 V VCC = MIN VCC = MIN VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 5.5 V VCC = MAX, VIN = 0.5 V VCC = MAX VOUT = 2.7 V VCC = MAX, VOUT = 0.5 V VCC = MAX, VOUT = GND Vout = HIGH Vout = LOW Vout = HIGH Z VCC = MAX NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type. 2. Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 4-399 MC54/74F646 * MC54/74F648 AC ELECTRICAL CHARACTERISTICS 54/74F TA = +25C VCC = +5.0 V CL = 50 pF RL = 500 Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ Parameter Maximum Clock Frequency Propagation Delay Clock to Bus Propagation Delay Bus to Bus (F646) Propagation Delay Bus to Bus (F648) Propagation Delay SBA or SAB to An or Bn Output Enable Time OE to An or Bn Output Disable Time OE to An or Bn Output Enable Time DIR to An or Bn Output Disable Time DIR to An or Bn Min 100 2.0 2.0 1.0 1.0 1.0 1.0 2.0 2.0 2.0 2.0 1.0 2.0 2.0 2.0 1.0 2.0 Max -- 7.0 8.0 7.0 6.5 7.0 6.5 7.5 7.5 7.0 7.0 7.0 7.0 7.0 7.0 7.0 7.0 54F TA = -55C to +125C VCC = +5.0 V 10% CL = 50 pF RL = 500 Min 75 2.0 2.0 1.0 1.0 1.0 1.0 2.0 2.0 2.0 2.0 1.0 2.0 2.0 2.0 1.0 2.0 Max -- 8.5 9.5 8.0 8.0 10.0 9.0 10.0 10.0 9.5 9.5 9.5 9.5 9.5 9.5 9.5 9.5 74F TA = 0C to +70C VCC = +5.0 V 10% CL = 50 pF RL = 500 Min 90 2.0 2.0 1.0 1.0 1.0 1.0 2.0 2.0 2.0 2.0 1.0 2.0 2.0 2.0 1.0 2.0 Max -- 8.0 9.0 7.5 7.0 7.5 7.0 9.0 9.0 8.5 8.5 8.5 8.5 8.5 8.5 8.5 8.5 Unit MHz ns ns ns ns ns ns ns ns AC OPERATING REQUIREMENTS 54/74F TA = +25C VCC = +5.0 V CL = 50 pF RL = 500 Symbol ts(H) ts(L) th(H) th(L) tw(H) tw(L) Parameter Setup Time, HIGH or LOW Bus to Clock Hold Time, HIGH or LOW Bus to Clock Clock Pulse Width HIGH or LOW Min 4.0 4.0 0.0 0.0 4.0 5.0 Max -- -- -- -- -- -- 54F TA = -55C to +125C VCC = +5.0 V 10% CL = 50 pF RL = 500 Min 5.0 5.0 0.0 0.0 4.0 5.0 Max -- -- -- -- -- -- 74F TA = 0C to +70C VCC = +5.0 V 10% CL = 50 pF RL = 500 Min 5.0 5.0 0.0 0.0 4.0 5.0 Max -- -- -- -- -- -- Unit ns ns ns FAST AND LS TTL DATA 4-400 -A24 13 Case 751E-03 DW Suffix 24-Pin Plastic SO-24 (WIDE) NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. 3. CONTROLLING DIMENSION: MILLIMETER. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. 751E 01 AND 02 OBSOLETE, NEW STANDARD 751E 03. -B1 12 P 12 PL 0.25 (0.010) M B M G R X 45 -TD 24 PL 0.25 (0.010) M C K T B S SEATING PLANE M F J A S DIM A B C D F G J K M P R MILLIMETERS MIN MAX 15.25 7.40 2.35 0.35 0.41 15.54 7.60 2.65 0.49 0.90 INCHES MIN MAX 0.601 0.292 0.093 0.014 0.016 0.612 0.299 0.104 0.019 0.035 1.27 BSC 0.229 0.127 0 10.05 0.25 0.317 0.292 8 10.55 0.75 0.050 BSC 0.0090 0.0050 0 0.395 0.010 0.0125 0.0115 8 0.415 0.029 Case 758-01 J Suffix 24-Pin Ceramic Dual In-Line 24 13 NOTES: 1. DIMENSION L TO CENTER OF LEADS WHEN B 1 12 FORMED PARALLEL. 2. DIMENSIONING AND TOLERANCING PER ANSI Y14.5, 1973. -AF C L -TSEATING PLANE N G D 20 PL 0.25 (0.010) M K P J DIM A B C D F G J K L N P MILLIMETERS MIN MAX 31.50 7.24 3.68 0.38 1.14 32.64 7.75 4.44 0.53 1.57 INCHES MIN MAX 1.240 0.285 0.145 0.015 0.045 1.285 0.305 0.175 0.021 0.062 2.54 BSC 0.20 2.54 7.62 0.51 9.14 0.33 4.19 7.87 1.27 10.16 0.100 BSC 0.008 0.100 0.300 0.020 0.360 0.013 0.165 0.310 0.050 0.400 INSIDE OF LEADS T A M Case 724-03 N Suffix 24-Pin Plastic NOTES: -A24 1 13 1. 2. CHAMFERRED CONTOUR OPTIONAL. DIM L" TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSIONS AND TOLERANCES PER ANSI Y14.5M, 1982. -B12 4. CONTROLLING DIMENSION: INCH. C -TSEATING PLANE L K E G F D 24 PL 0.25 (0.010) M NOTE 1 N M J 24 PL 0.25 (0.010) T A M M T B M DIM A B C D E F G J K L M N MILLIMETERS MIN MAX 31.25 6.35 3.69 0.38 32.13 6.85 4.44 0.51 INCHES MIN MAX 1.230 0.250 0.145 0.015 1.265 0.270 0.175 0.020 1.27 BSC 1.02 1.52 0.050 BSC 0.040 0.060 2.54 BSC 0.18 2.80 0.30 3.55 0.100 BSC 0.007 0.110 0.012 0.140 7.62 BSC 0 0.51 15 1.01 0.300 BSC 0 0.020 15 0.040 FAST AND LS TTL DATA 4-401 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Literature Distribution Centers: USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. FAST AND LS TTL DATA 4-402 |
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