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Features
* All-in-one Design
- MIDI Control Processor - Synthesis - Compatible Effects: Reverb + Chorus - Programmable Spatializer or Four-channel Surround(1) - Four-band Stereo Equalizer State-of-the-art Synthesis Supplies Best Quality for Price - 34-voice Polyphony + Effects - Up to 1 MB Wavetable/Firmware Support Synthesizer Chipset: SAM9713 + 8-Mbit ROM + 32K x 8 SRAM + DAC Hardware-programmable DAC Mode - I2S 16 to 20 bits - Japanese 16 bits Firmware/Sample Set Available for Turnkey Designs - 8-Mbit GS(R) GMS960800B(2) - 8-Mbit CleanWave(R) GMS970800B Typical Applications: Cost-sensitive Portable Karaoke/VCD Karaoke 80-lead TQFP Package: Small Footprint, Easy Mounting Ideal for Battery Operation - Low Power - Power-down Mode - Wide Supply Voltage Range: 3V to 4.5V Core, 3V to 5.5V Periphery 1. Four-channel surround requires additional DAC. 2. GMS960800B with express permission of Roland Corporation. Special licensing conditions apply. Refer to warning on last page of this datasheet.
* * * * * * *
Low-cost Integrated Synthesizer with Effects SAM9713
Notes:
Description
The highly integrated architecture of the SAM9713 combines a specialized high-performance RISC digital signal processor and a general-purpose 16-bit CISC control processor on a single chip. An on-chip memory management unit allows the digital signal processor and the control processor to share external ROM and RAM devices. The ROM bus width should be 16 bits while the SRAM can be selected to be 8 or 16 bits wide. When using an 8-bit SRAM, fast type (static cache) should be selected because two SRAM cycles will be completed in one ROM cycle duration. Running at 300 million operations per second (MOPS), the digital signal processor supports high-quality PCM synthesis as well as most important functions like reverb, chorus, surround effect and equalizer. By adding an additional stereo DAC, fourchannel audio surround can also be obtained. The SAM9713 operates from a low-frequency 9.6 MHz typical crystal. A built-in PLL raises this frequency to a 38.4 MHz internal clock that controls the two processors. Care has been taken that output pin signals change only when necessary. This minimizes RFI (radio frequency interferences) and power consumption. Minimizing RFI is mostly important in order to comply with standards such as FCC, CSA and CE. The core power supply for the SAM9713 should range from 3V to 4.5V; the periphery supports' supply from 3V to 5.5V. Therefore, by selecting 3.3V ROM, SRAM and DAC, it is possible to develop low-power/low-voltage portable applications.
Rev. 1712A-12/00
1
Figure 1. Typical Hardware Configuration
1 MB ROM
32K x 8 RAM
MIDI IN
SAM9713
Stereo DAC
Audio Out
Pin Description
Pins by Function
Table 1. Power Supply Group
Pin Name GND VCC VC3 Pin Number 5, 14, 21, 23, 36, 38, 57, 61, 62, 65, 74 1, 6, 13, 18, 22, 32, 56, 6480 7, 17, 63 Type PWR PWR PWR Function Digital Ground All pins should be connected to a ground plane. Power Supply, 3V to 5.5V All pins should be connected to a VCC plane Core Power Supply, 3V to 4.5V All pins should be connected to nominal 3.3V. If 3.3V is not available, then VC3 can be derived from 5V by two 1N4148 diodes in series.
Table 2. Serial MIDI
Pin Name MIDI IN Pin Number 15 Type IN Function Serial TTL MIDI IN. All controls are received by this pin.
Table 3. External ROM/RAM Group
Pin Name WA0 - WA18 Pin Number 37, 39, 41 - 55, 58, 59 Type OUT Function External ROM/RAM address for up to 512K words (8M bits) of memory. ROM memory holds firmware and PCM data. RAM memory holds working variables and effects delay lines. External ROM/RAM data. Holds read data from ROM or RAM when WOE is low, writes data to RAM when WWE is low. External ROM chip select, active low. External RAM chip select, active low.
WD0 - WD15 WCS0 WCS1
66 - 73, 75 - 79, 2 - 4 29 30
I/O OUT OUT
2
SAM9713
SAM9713
Pin Name WOE WWE RBS Pin Number 31 28 20 Type OUT OUT OUT Function External ROM/RAM output enable, active low. External RAM write, active low. RAM byte select. Used as lower address from RAM when an 8-bit wide RAM is connected.
Table 4. Digital Audio Group
Pin Name CLBD WSBD DABD0 DABD1 DAC/DAAD Pin Number 19 27 25 26 24 Type OUT OUT OUT OUT IN Function Digital audio bit clock Digital audio left/right select Digital audio main stereo output Auxiliary digital stereo output. Reserved for surround effects. DAC type: 0 = I2S 16 to 20 bits, 1 = Japanese 16 bits Can also be used as digital audio input if 32K x 16 RAM is connected.
Table 5. Miscellaneous Group
Pin Name X1 - X2 LFT RESET PDWN Pin Number 10, 9 8 11 12 IN IN Type Function 9.6 MHz crystal connection. An external 9.6 MHz clock can also be used on X1 (3.3V input). X2 cannot be used to drive external circuits. PLL external RC network Reset input, active low. This is a Schmitt trigger input, allowing direct connection of an RC network. Power-down, active low. When power-down is active, then all output pins will be floated. The crystal oscillator will be stopped. To exit from power-down, PDWN should be high and RESET applied. Test pins. Should be grounded. When high, indicates that the synthesizer is up and running.
TEST0 TEST2 RUN
33, 34, 35 16
IN OUT
3
Pinout
Figure 2. SAM9713 Pinout in 80-lead TQFP Package
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
VCC WD12 WD11 WD10 WD9 WD8 GND WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0 GND VCC VC3 GND GND
VCC WD13 WD14 WD15 GND VCC VC3 LFT X2 X1 RESET PDWN VCC GND MIDI IN RUN VC3 VCC CLBD RBS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
NC WA18 WA17 GND VCC WA16 WA15 WA14 WA13 WA12 WA11 WA10 WA9 WA8 WA7 WA6 WA5 WA4 WA3 WA2
4
SAM9713
GND VCC GND DAC/DAAD DABD0 DABD1 WSBD WWE WCS0 WCS1 WOE VCC TEST0 TEST1 TEST2 GND WA0 GND WA1 NC
SAM9713
Mechanical Dimensions
Figure 3. 80-lead Thin Plastic Quad Flat Pack
Table 6. Package Dimensions (in mm)
Dimension A A1 A2 D D1 E E1 L P B Min 1.40 0.05 1.35 15.90 13.90 15.90 13.90 0.45 - 0.22 Typ 1.50 0.10 1.40 16.00 14.00 16.00 14.00 0.60 0.65 0.32 Max 1.60 0.15 1.45 16.10 14.10 16.10 14.10 0.75 - 0.38
5
Absolute Maximum Ratings
Table 7. Absolute Maximum Ratings
Symbol Parameter/Condition Ambient Temperature (power applied) Storage Temperature Voltage on any pin (except X1) VCC VC3 Supply Voltage Supply Voltage Maximum IOL per I/O pin Min -40 -6.5 -0.5 -0.5 -0.5 Typ Max +85 +150 VCC + 0.5 6.5 4.5 10 Unit C C V V V mA
Recommended Operating Conditions
Table 8. Recommended Operating Conditions
Symbol VCC VC3 TA Note: Parameter/Condition Supply Voltage(1) Supply Voltage Min 3 3 Typ 3.3/5.0 3.3 Max 5.5 4.5 Unit V V
Operating Ambient Temperature 0 70 C 1. When using 3.3V supply in a 5V environment, care must be taken that pin voltage does not exceed VCC + 0.5V. Pin X1 is powered by VC3 input. If X1 is driven by a 5V device, then a minimum series resistor is required (typ 330).
DC Characteristics
Table 9. DC Characteristics (TA = 25C, VC3 = 3.3V 10%)
Symbol VIL VIH VOL VOH ICC Parameter/Condition Low-level Input Voltage High-level Input Voltage Low-level Output Voltage IOL = -3.2mA High-level Output Voltage IOH = 0.8mA Power Supply Current (crystal freq. = 9.6 MHz) Power-down Supply Current VCC 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 2.8 4.5 70 25 70 90 35 100 Min -0.5 -0.5 2.3 3.3 Typ Max 1.0 1.7 VCC + 0.5 VCC + 0.5 0.45 0.45 Unit V V V V V V V V mA mA A
6
SAM9713
SAM9713
Timings
All timing conditions: TA = 25C, VCC = 5V, VC3 = 3.3V, all outputs except X2 and LFT load capacitance = 30pF, crystal frequency or external clock at X1 = 9.6 MHz.
External ROM Timing
Figure 4. ROM Read Cycle tRC WCS0 tCSOE WA0 WA18 tPOE WOE tOE WD0 WD15 tACE tDF
Table 10. Timing Parameters
Symbol tRC tCSOE tPOE tACE tOE tDF Parameter Read Cycle Time Chip Select Low/Address Valid to WOE Low Output Enable Pulse Width Chip Select/Address Access Time Output Enable Access Time Chip Select or WOE High to Input Data High-Z 125 70 0 50 Min 130 45 78 80 Typ Max Unit ns ns ns ns ns ns
7
External RAM Timing
Figure 5. 16-bit SRAM Read Cycle
tRC WCS1 tCSOE WA0 WA18 tPOE WOE WWE tOE WD0 WD15 tACE tDF
Figure 6. 16-bit SRAM Write Cycle tWC WCS1 tCSWE WA0 WA18 WOE WWE tDW WD0 WD15 tDH
tWP
8
SAM9713
SAM9713
Table 11. Timing Parameters
Symbol tRC tCSOE tPOE tACE tOE tDF tWC tCSWE tWP tDW tDH Parameter Read Cycle Time Chip Select Low/Address Valid to WOE Low Output Enable Pulse Width Chip Select/Address Access Time Output Enable Access Time Chip Select or WOE High to Input Data High-Z Write Cycle Time Write Enable Low from CS or Address or WOE Write Pulse Width Data Out Setup Time Data Out Hold Time 95 10 125 70 0 130 40 104 50 Min 130 45 78 80 Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns
Figure 7. 8-bit SRAM Read Cycle
tRC WCS1 tCSOE WA0 WA18 tPOE WOE WWE tACE RBS tOE WD0 WD7 LOW tACH tDF HIGH tORB
9
Figure 8. 8-bit SRAM Write Cycle
tWC WCS1 tCSWE WA0 WA18 WOE tWP WWE RBS tDW1 WD0 WD7 tDH1 tDW2 HIGH tDH2 tAS tWP
LOW
Table 12. Timing Parameters
Symbol tRC tCSOE tPOE tACE tOE tORB tACH tDF tWC tCSWE tWP tDW1 tDH1 tAS tDW2 tDH2 Parameter Word Read Cycle Time Chip Select Low/Address Valid to WOE Low Output Enable Pulse Width Chip Select/Address Low Byte Access Time Output Enable Low Byte Access Time Output Enable Low to Byte Select High Byte Select High Byte Access Time Chip Select or WOE High to Input Data High-Z Word Write Cycle Time 1st WWE Low from CS or Address or WOE Write (Low and High Byte) Pulse Width Data Out Low Byte Setup Time Data Out Low Byte Hold Time RBS High to Second Write Pulse Data Out High Byte Setup Time Data Out High Byte Hold Time 45 0 130 40 20 25 20 8 40 10 50 70 20 26 Min 130 45 78 80 Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
10
SAM9713
SAM9713
Digital Audio
Figure 9. Digital Audio Timing tCW WSBD CLBD DABD0 DABD1 DAC/DAAD* tSOD tSOD tCW tCLBD
* when used as audio in
Table 13. Timing Parameters
Symbol tCW tSOD tCLBD Parameter CLBD Rising to WSBD Change DABD Valid before/after CLBD Rising CLBD Cycle Time Min 200 200 416.67 Typ Max Unit ns ns ns
Digital Audio Frame
Figure 10. Digital Audio Frame Format
WSBD (I2S) WSBD (Japanese) CLBD
DABD0 DABD1 DAC/DAAD*
X
XXX
XX
X
XX
XX
X
MSB
LSB (16 bits)
LSB (20 bits) LSB (18 bits)
MSB
* when used as audio in
Notes:
1. Selection between I2S and Japanese format is through pin DAC/DAAD in case of 32K x 8 SRAM. 2. Digital audio in is available only in case of 32K x 16 SRAM. In this case, DAAD is 16 bits only.
11
Reset and Power-down
During power-up, the RESET input should be held low until the crystal oscillator and PLL are stabilized, which can take about 20 ms. A typical RC/diode power-up network can be used. After the low-to-high transition of RESET, the following occurs: * Synthesis enters an idle state * The RUN output is set to zero * Firmware execution starts from address 0100H in ROM space (WCS0 low) If PDWN is asserted low, then all I/Os and outputs will be floated and the crystal oscillator and PLL will be stopped. The chip enters a deep power-down sleep mode. To exit power-down, PDWN has to be asserted high, then RESET applied.
Recommended Board Layout
As for all HCMOS high-integration ICs, some rules of board layout should be followed for reliable device operation: * GND, VCC, VC3 distribution, decouplings All GND, VCC, VC3 pins should be connected. GND and V CC planes are strongly recommended below the SAM9713. The board GND and VCC distribution should be in grid form. For 5V V CC operation, if 3.3V is not available, VC3 can be connected to VCC by two 1N4148 diodes in series. This guarantees a minimum voltage drop of 1.2V. Recommended VCC decoupling is 0.1 F at each corner of the IC with an additional 10 F decoupling close to the crystal. VC3 requires a single 0.1 F decoupling close to the IC. * Crystal, LFT The paths between the crystal, the crystal compensation capacitors, the LFT filter R-C-R and the SAM9713 should be short and shielded. The ground return from the compensation capacitors and LFT filter should be the GND plane from SAM9713. * Analog section A specific AGND ground plane should be provided, which connects by a single trace to the GND ground. No digital signals should cross the AGND plane. Refer to the codec vendor recommended layout for correct implementation of the analog section. * Unused inputs Unused inputs should always be connected. A floating input can cause internal oscillation inside the IC, which can destroy the IC by dramatically increasing the power consumption. If you plan to use the power-down feature, care should be taken that no pin is left floating during power- down. Usually, a 1 M ground return is sufficient.
12
SAM9713
SAM9713
Recommended Crystal Compensation and LFT Filter
C1 GND 22 pF X1 9.6 MHz GND C4 22 pF LFT C2 2.2 nF R1 100 VCC C3 10 nF GND PDWN/ X2 X1
DABD1
Note:
The X2 output cannot be used to drive another circuit.
DABD0
WSBD
CLBD
RUN
13
14
SAM9713
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Warning: GMS960800B may not be installed in any musical instrument except electronic keyboards and synthesizers that have a sale price of less than $75 FOB. Using this product in the manufacture of musical instruments or selling this product for use in a musical instrument (other than the exceptions noted above) is a violation of the intellectual property rights of Roland Corporation and will result in liability for infringement. literature@atmel.com
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1712A-12/00/0M
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