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MOSEL VITELIC
V43644R04V(C)TG-10PC 3.3 VOLT 4M x 64 HIGH PERFORMANCE PC100 UNBUFFERED SDRAM MODULE
PRELIMINARY
Features
s 168 Pin Unbuffered 4,194,304 x 64 bit Oganization SDRAM Modules s Utilizes High Performance 4M x 16 SDRAM in TSOPII-54 Packages s Fully PC Board Layout Compatible to INTEL'S Rev 1.0 Module Specification s Single +3.3V ( 0.3V) Power Supply s Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) s Auto Refresh (CBR) and Self Refresh s All Inputs, Outputs are LVTTL Compatible s 4096 Refresh Cycles every 64 ms s Serial Present Detect (SPD) s SDRAM Performance
Description
The V43644R04V(C)TG-10PC memory module is organized 4,194,304 x 64 bits in a 168 pin dual in line memory module (DIMM). The 4M x 64 memory module uses 4 Mosel-Vitelic 4M x 16 SDRAM. The x64 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required.
Key Component Timing Parameters
tCK tAC tAC Clock Frequency (max.) Clock Access Time CAS Latency = 3 Latency = 2
-8PC
125 6
Units
MHz ns
6
ns
s Module Frequency vs AC Parameter
Frequency
V43644R04V(C)TG-10PC 100 MHz (PC)
CL (CAS Latency)
3 2
tRCD
2 2
tRP
2 2
tRC
7 7
Unit
CLK CLK
V43644R04V(C)TG-10PC-01
V43644R04V(C)TG-10PC Rev. 1.1 June 2000
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MOSEL VITELIC
Pin Configurations (Front Side/Back Side)
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Front VSS I/O1 I/O2 I/O3 I/O4 VCC I/O5 I/O6 I/O7 I/O8 I/O9 VSS I/O10 I/O11 I/O12 I/O13 I/O14 VCC I/O15 I/O16 CBO* CB1* VSS NC NC VCC WE DQM0 Pin 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Front DQM1 CS0 DU VSS A0 A2 A4 A6 A8 A10(AP) BA1 VCC VCC CLK0 VSS DU CS2 DQM2 DQM3 DU VCC NC NC CB2* CB3* VSS I/O17 I/O18 Pin 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Front I/O19 I/O20 VCC I/O21 NC DU CKE1 VSS I/O22 I/O23 I/O24 VSS I/O25 I/O26 I/O27 I/O28 VCC I/O29 I/O30 I/O31 I/O32 VSS CLK2 NC WP SDA SCL VCC Pin 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Back VSS I/O33 I/O34 I/O35 I/O36 VCC I/O37 I/O38 I/O39 I/O40 I/O41 VSS I/O42 I/O43 I/O44 I/O45 I/O46 VCC I/O47 I/O48 CB4* CB5* VSS NC NC VCC CAS DQM4
V43644R04V(C)TG-10PC
Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Back DQM5 CS1 RAS VSS A1 A3 A5 A7 A9 BA0 A11 VCC CLK1 NC VSS CKE0 CS3 DQM6 DQM7 DU VCC NC NC CB6* CB7* VSS I/O49 I/O50 Pin 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Back I/O51 I/O52 VCC I/O53 NC DU NC VSS I/O54 I/O55 I/O56 VSS I/O57 I/O58 I/O59 I/O60 VCC I/O61 I/O62 I/O63 I/O64 VSS CLK3 NC SA0 SA1 SA2 VCC
Notes:
* These pins are not used in this module.
Pin Names
A0-A11 I/O1-I/O64 RAS CAS WE BA0, BA1 CKE0, CKE1 CS0-CS3 CLK0-CLK3 DQM0-DQM7 VCC VSS SCL Address Inputs Data Inputs/Outputs Row Address Strobe Column Address Strobe Read/Write Input Bank Selects Clock Enable Chip Select Clock Input Data Mask Power (+3.3 Volts) Ground Clock for Presence Detect CB0-CB7 NC DU SA0-A2 SDA Serial Data OUT for Presence Detect Serial Data IN for Presence Detect Check Bits (x72 Organization) No Connection Don't Use
V43644R04V(C)TG-10PC Rev. 1.1 June 2000
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MOSEL VITELIC
Part Number Information
V
MOSEL-VITELIC MANUFACTURED SDRAM
V43644R04V(C)TG-10PC
4
3
64
4
R
0
4
V
C
T
G
-
10PC
-10PC 100MHz 2-2-2
GOLD TSOP COMPONENT REVISION LEVEL BLANK = B REV. C = C REV. WIDTH DEPTH 168 PIN UNBUFFERED DIMM X 16 COMPONENT LVTTL 4 BANKS REFRESH RATE 4K
V43644R04V(C)TG-10PC-02
3.3V
Block Diagram
CS0 DQM0 I/O1-I/O8 10 DQM1 I/O9-I/O16 10 CS2 DQM2 I/O17-I/O24 10 DQM3 I/O25-I/O32 10 E2PROM SPD (256 WORD X 8 BIT) SCL SA2 SA1 SA0 SDA WP BA0, BA1
47K
CS LDQM I/O1-I/O8 UDQM I/O1-I/O8
DQM4 I/O33-I/O40 10 D0 DQM5 I/O41-I/O48 10
CS LDQM I/O1-I/O8 UDQM I/O1-I/O8
D2
CS LDQM I/O1-I/O8 UDQM I/O1-I/O8
DQM6 I/O49-I/O56 10 D1 DQM7 I/O57-I/O64 10 CKE0 RAS, CAS, WE A(11:0)
CS LDQM I/O1-I/O8 UDQM I/O1-I/O8
D3
CKE: SDRAM D0-D3 SDRAM D0-D3 A(11:0): SDRAM D0-D3 BA0, BA1: SDRAM D0-D3 D0-D3 D0-D3 10 CLK1, CLK3 10pF
VCC VSS CLOCK WIRING CLK0 CLK1 CLK2 CLK3 4 SDRAM +15pF Termination 2 SDRAM +15pF Termination
V43644R04V(C)TG-10PC-03
V43644R04V(C)TG-10PC Rev. 1.1 June
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MOSEL VITELIC
Serial Presence Detect Information
A serial presence detect storage device E PROM - is assembled onto the module. Information about the module configuration, speed, etc. is
2
V43644R04V(C)TG-10PC
written into the E2PROM device during module production using a serial presence detect protocol (I2C synchronous 2-wire bus)
SPD-Table:
Hex Value Byte Number
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Function Described
Number of SPD bytes Total bytes in Serial PD Memory Type Number of Row Addresses (without BS bits) Number of Column Addresses (for x16 SDRAM) Number of DIMM Banks Module Data Width Module Data Width (continued) Module Interface Levels SDRAM Cycle Time at CL=3 SDRAM Access Time from Clock at CL=3 Dimm Config (Error Det/Corr.) Refresh Rate/Type SDRAM width, Primary Error Checking SDRAM Data Width Minimum Clock Delay from Back to Back Random Column Address Burst Length Supported Number of SDRAM Banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM Module Attributes SDRAM Device Attributes: General Minimum Clock Cycle Time at CAS Latency = 2 Maximum Data Access Time from Clock for CL = 2 Minimum Clock Cycle Time at CL = 1 Maximum Data Access Time from Clock at CL = 1 Minimum Row Precharge Time tRP Minimum Row Active to Row Active Delay tRRD Minimum RAS to CAS Delay tRCD
SPD Entry Value
128 256 SDRAM 12 8 1 64 0 LVTTL 10.0 ns 6.0 ns none Self-Refresh, 15.6s x16 n/a / x8 tccd = 1 CLK 1, 2, 4, 8 & full Page 4 CL = 2 & 3 CS Latency = 0 WL = 0 Non Buffered/Non Reg. Vcc tol 10% 10.0 ns 6.0 ns Not Supported Not Supported 20 ns 16 ns 20 ns
100 MHz -10PC
80 08 04 0C 08 01 40 00 01 A0 60 00 80 10 00 01
16 17 18 19 20 21 22 23 24 25 26 27 28 29
8F 04 06 01 01 00 0E A0 60 00 00 14 10 14
V43644R04V(C)TG-10PC Rev. 1.1 June 2000
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MOSEL VITELIC
SPD-Table: (Continued)
V43644R04V(C)TG-10PC
Hex Value Byte Number
30 31 32 33 34 35 36-61 62 63 64-125
Function Described
Minimum RAS Pulse Width tRAS Module Bank Density (Per Bank) SDRAM Input Setup Time SDRAM Input Hold Time SDRAM Data Input Setup Time SDRAM Data Input Hold Time Superset Information (May be used in Future) SPD Revision Checksum for Bytes 0 - 62 Manufacturers's Information (Optional) (FFh if not used) Max. Frequency Specification 100 MHz Support Details Unused Storage Location
SPD Entry Value
45 ns 32 M 2 ns 1 ns 2 ns 1 ns
100 MHz -10PC
2D 08 20 10 20 10 00
Revision 1.2
12 FD XX
126 127 128+
100 MHz
64 AF 00
TA = 0C to 70C; VSS = 0 V; VDD, VDDQ = 3.3V 0.3V
Limit Values Symbol
VIH VIL VOH VOL II(L) IO(L)
DC Characteristics
Parameter
Input High Voltage Input Low Voltage Output High Voltage (IOUT = -2.0 mA) Output Low Voltage (IOUT = 2.0 mA) Input Leakage Current, any input (0 V < VIN < 3.6 V, all other inputs = 0V) Output leakage current (DQ is disabled, 0V < VOUT < VCC)
Min.
2.0 -0.5 2.4 -- -40
Max.
VCC+0.3 0.8 -- 0.4 40
Unit
V V V V A A
-40
40
V43644R04V(C)TG-10PC Rev. 1.1 June
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MOSEL VITELIC
Capacitance
Symbol
CI1 CI2 CICL CI3 CI4 CIO CSC CSD
V43644R04V(C)TG-10PC
TA = 0C to 70C; VDD = 3.3V 0.3V, f = 1 MHz
Parameter
Input Capacitance (A0 to A11, RAS, CAS, WE) Input Capacitance (CS0-CS3) Input Capacitance (CLK0-CLK3) Input Capacitance (CKE0, CKE1) Input Capacitance (DQM0-DQM7) Input/Output Capacitance (I/O1-I/064) Input Capacitance (SCL, SA0-2) Input/Output Capacitance
Limit Values
45 20 22 22 13 13 8 10
Unit
pF pF pF pF pF pF pF pF
Standby and Refresh Currents1
TA = 0C to 70C, VCC = 3.3V 0.3V
Symbol Parameter
ICC1 Operating Current
Test Conditions
Burst length = 4, CL = 3 tRC> = tRC(min), tCK> = tCK(min), IO = 0 mA 2 Bank Interleave Operation CKE< = VIL(max), tCK> = tCK(min) CKE< = VIL(max), tCK = Infinite CKE> = VIH(min), tCK> = tCK(min), Input changed once in 3 cycles CKE> = VIH(min), tCK = Infinite, No Input change
4M x 64
440
Unit
mA
Note
1,2
ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS ICC4
Precharged Standby Current in Power Down Mode Precharged Standby Current in Non-Power Down Mode
12 8 200
mA mA mA CS = High
20
mA
Active Standby Current in Power Down Mode Active Standby Current in Non-Power Down Mode
CKE< = VIL(max), tCK> = tCK(min) CKE< = VIL(max), tCK = Infinite CKE> = VIH(min), tCK> = tCK(min), Input changed one time CKE> = VIH(min), tCK = Infinite, No Input change
32 16 120
mA mA mA CS = High
80
mA
Burst Operating Current
Burst length = Full Page, tRC = Infinite, CL = 3, tCK> = tCK(min), IO = 0 mA 2 Banks Activated tRC>= tRC(min) CKE = <0,2 V
620
mA
1, 2
ICC5 ICC6
Auto Refresh Current Self Refresh Current
520 8
mA mA
1,2 1,2
V43644R04V(C)TG-10PC Rev. 1.1 June 2000
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MOSEL VITELIC
AC Characteristics 3,4
TA = 0 to 70C; VSS = 0V; VCC = 3.3V 0.3V, tT = 1 ns
V43644R04V(C)TG-10PC
Limit Values
-10PC # Symbol Parameter Min. Max. Unit Note
Clock and Clock Enable
1 tCK Clock Cycle Time CAS Latency = 3 CAS Latency = 2 System frequency CAS Latency = 3 CAS Latency = 2 Clock Access Time CAS Latency = 3 CAS Latency = 2 Clock High Pulse Width Clock Low Pulse Width Input Setup time Input Hold Time CKE Setup Time (Power down mode) CKE Setup Time (Self Refresh Exit) Transition time (rise and fall) 10 10 - - - - 3 3 2 1 2.5 8 1 100 100 6 6 - - - - - - - ns ns MHz MHz 4,5 ns ns ns ns ns ns ns ns ns 6 6 7 7 8 9
2
fCK
3
tAC
4 5 6 7 8 9 10
tCH tCL tCS tCH tCKSP tCKSR tT
Common Parameters
11 12 13 14 15 16 tRCD tRC tRAS tRP tRRD tCCD RAS to CAS delay Cycle Time Active Command Period Precharge Time Bank to Bank Delay Time CAS to CAS delay time (same bank) 20 70 45 20 16 1 - 120k - - - - ns ns ns ns ns CLK
Refresh Cycle
17 18 tSREX tREF Self Refresh Exit Time Refresh Period (4096 cycles) 10 64 - - ns ms 9 8
Read Cycle
19 20 21 22 tOH tLZ tHZ tDQZ Data Out Hold Time Data Out to Low Impedance Time Data Out to High Impedance Time DQM Data Out Disable Latency 3 0 3 2 - - 9 - ns ns ns CLK 10 4
Write Cycle
23 24 25 tDPL tDAL tDQW Data input to Precharge (write recovery) Data In to Active/refresh DQM Write Mask Latency 2 5 0 - - - CLK CLK CLK 11
V43644R04V(C)TG-10PC Rev. 1.1 June
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MOSEL VITELIC
Notes:
V43644R04V(C)TG-10PC
1. The specified values are valid when addresses are changed no more than once during tCK(min.) and when No Operation commands are registered on every rising clock edge during tRC(min). Values are shown per module bank. 2. The specified values are valid when data inputs (DQ's) are stable during tRC(min.). 3. All AC characteristics are shown for device level. An initial pause of 100 s is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 4. AC timing tests have VIL = 0.4V and VIH = 2.4V with the timing referenced to the 1.4V crossover point. The transition time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0V.
tCH 2.4V CLOCK 0.4V
+ 1.4 V 50 Ohm Z=50 Ohm I/O 50 pF
tCL
tSETUP tHOLD
tT
INPUT
1.4V
tAC tLZ tOH
tAC
I/O 50 pF
1.4V
OUTPUT
Measurement conditions for tac and toh
tHZ
5. If clock rising time is longer than 1 ns, a time (tT/2 -0.5) ns has to be added to this parameter. 6. Rated at 1.5V 7. If tT is longer than 1 ns, a time (tT -1) ns has to be added to this parameter. 8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to "wake-up" the device. 9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 10. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels.
11. tDAL is equivalent to tDPL + tRP.
V43644R04V(C)TG-10PC Rev. 1.1 June 2000
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MOSEL VITELIC
Package Diagram
SDRAM DIMM Module Package
V43644R04V(C)TG-10PC
All measurements in mm 133.35
127.35
(2.54 max)
1 3.0
10
11
40
41
84
17.78
34.925
1.27 0.100 42.18 66.68 A B C
85
94
95
124
125
168 4.0 0.100 D
6.35
6.35
1.27
1.0 0.05
3.125
3.125
2.4 min.
0.2 0.15
2.0 Detail A 2.26 Detail B
2.0 Detail C
8.25
4.45
V43644R04V(C)TG-10PC-04
RADIUS 1.27 + 0.10
Tolerances: (0.13) unless otherwise specified.
V43644R04V(C)TG-10PC Rev. 1.1 June
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MOSEL VITELIC
Label Information
MOSEL VITELIC
Part Number Criteria of PC100 or PC133 (refer to MVI datasheet)
V43644R04V(C)TG-10PC
V43644R04VCTG-10PC PC100U-222-612-A Taiwan XXXX-XXXXXXX
DIMM manufacture date code
Trace Code
PC100 U - 222 - 6 12 - A
UNBUFFERED DIMM CL = 2 (CLK) tRCD = 2 (CLK) tRP = 2 (CLK) Gerber file Intel(R) PC100 x 8 Based Intel SPD Revision 1.2 tAC = 6 ns
V43644R04V(C)TG-10PC-05
V43644R04V(C)TG-10PC Rev. 1.1 June 2000
10
MOSEL VITELIC
U.S.A.
3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952
WORLDWIDE OFFICES
TAIWAN
7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 NO 19 LI HSIN ROAD SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 886-3-579-5888 FAX: 886-3-566-5888
V43644R04V(C)TG-10PC
UK & IRELAND
SUITE 50, GROVEWOOD BUSINESS CENTRE STRATHCLYDE BUSINESS PARK BELLSHILL, LANARKSHIRE, SCOTLAND, ML4 3NQ PHONE: 01698-748515 FAX: 01698-748516
SINGAPORE
10 ANSON ROAD #23-13 INTERNATIONAL PLAZA SINGAPORE 079903 PHONE: 65-3231801 FAX: 65-3237013
HONG KONG
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JAPAN
WBG MARIVE WEST 25F 6, NAKASE 2-CHOME MIHAMA-KU, CHIBA-SHI CHIBA 261-7125 PHONE: 81-43-299-6000 FAX: 81-43-299-6555
GERMANY (CONTINENTAL EUROPE & ISRAEL)
71083 HERRENBERG BENZSTR. 32 GERMANY PHONE: +49 7032 2796-0 FAX: +49 7032 2796 22
U.S. SALES OFFICES
NORTHWESTERN
3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952
SOUTHWESTERN
302 N. EL CAMINO REAL #200 SAN CLEMENTE, CA 92672 PHONE: 949-361-7873 FAX: 949-361-7807
CENTRAL, NORTHEASTERN & SOUTHEASTERN
604 FIELDWOOD CIRCLE RICHARDSON, TX 75081 PHONE: 972-690-1402 FAX: 972-690-0341
(c) Copyright 2000, MOSEL VITELIC Inc.
6/00 Printed in U.S.A.
The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications.
MOSEL VITELIC
3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461

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