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2.5 V to 5.5 V, Parallel Interface Octal Voltage Output 8-/10-/12-Bit DACs AD5346/AD5347/AD5348
FEATURES
AD5346: octal 8-bit DAC AD5347: octal 10-bit DAC AD5348: octal 12-bit DAC Low power operation: 1.4 mA (max) @ 3.6 V Power-down to 120 nA @ 3 V, 400 nA @ 5 V Guaranteed monotonic by design over all codes Rail-to-rail output range: 0 V to VREF or 0 V to 2 x VREF Power-on reset to 0 V Simultaneous update of DAC outputs via LDAC pin Asynchronous CLR facility Readback Buffered/unbuffered reference inputs 20 ns WR time 38-lead TSSOP/6 mm x 6 mm 40-lead LFCSP packaging Temperature range: -40C to +105C
GENERAL DESCRIPTION
The AD5346/AD5347/AD53481 are octal 8-, 10-, and 12-bit DACs, operating from a 2.5 V to 5.5 V supply. These devices incorporate an on-chip output buffer that can drive the output to both supply rails, and also allow a choice of buffered or unbuffered reference input. The AD5346/AD5347/AD5348 have a parallel interface. CS selects the device and data is loaded into the input registers on the rising edge of WR. A readback feature allows the internal DAC registers to be read back through the digital port. The GAIN pin on these devices allows the output range to be set at 0 V to VREF or 0 V to 2 x VREF. Input data to the DACs is double-buffered, allowing simultaneous update of multiple DACs in a system using the LDAC pin. An asynchronous CLR input is also provided, which resets the contents of the input register and the DAC register to all zeros. These devices also incorporate a power-on reset circuit that ensures that the DAC output powers on to 0 V and remains there until valid data is written to the device. All three parts are pin compatible, which allows users to select the amount of resolution appropriate for their application without redesigning their circuit board.
APPLICATIONS
Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Optical networking Automatic test equipment Mobile communications Programmable attenuators Industrial process control
VDD AGND DGND
FUNCTIONAL BLOCK DIAGRAM
VREFAB VREFCD
POWER-ON RESET DAC REGISTER DAC REGISTER DAC REGISTER DAC REGISTER DAC REGISTER DAC REGISTER DAC REGISTER DAC REGISTER STRING DAC A STRING DAC B STRING DAC C STRING DAC D STRING DAC E STRING DAC F STRING DAC G STRING DAC H
AD5348
BUF GAIN DB11 . . . DB0
INPUT REGISTER INPUT REGISTER INPUT REGISTER BUFFER
VOUTA VOUTB VOUTC VOUTD VOUTE VOUTF VOUTG VOUTH
BUFFER
BUFFER
CS RD WR A2 A1 A0
INTERFACE LOGIC
INPUT REGISTER INPUT REGISTER INPUT REGISTER INPUT REGISTER INPUT REGISTER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
CLR LDAC
POWER-DOWN LOGIC
03331-0-001
VREFGH
VREFEF
PD
Figure 1.
1
Protected by U.S. Patent No. 5,969,657; other patents pending.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2003 Analog Devices, Inc. All rights reserved.
AD5346/AD5347/AD5348 TABLE OF CONTENTS
Specifications..................................................................................... 3 AC Characteristics............................................................................ 4 Timing Characteristics..................................................................... 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 AD5346 Pin Configurations and Function Descriptions ........... 7 AD5347 Pin Configurations and Function Descriptions ........... 8 AD5348 Pin Configurations and Function Descriptions ........... 9 Terminology .................................................................................... 10 Typical Performance Characteristics ........................................... 12 Functional Description .................................................................. 16 Digital-to-Analog Section ......................................................... 16 Resistor String ............................................................................. 16 DAC Reference Input................................................................. 16 Output Amplifier ........................................................................ 16 Parallel Interface ......................................................................... 17 Power-On Reset.......................................................................... 17 Power-Down Mode .................................................................... 17 Suggested Data Bus Formats..................................................... 18 Applications Information .............................................................. 19 Typical Application Circuits ..................................................... 19 Driving VDD from the Reference Voltage................................. 19 Bipolar Operation Using the AD5346/AD5347/AD5348..... 19 Decoding Multiple AD5346/AD5347/AD5348s.................... 20 AD5346/AD5347/AD5348 as Digitally Programmable Window Detectors ...................................................................... 20 Programmable Current Source ................................................ 20 Coarse and Fine Adjustment Using the AD5346/AD5347/AD5348 ....................................................... 21 Power Supply Bypassing and Grounding................................ 21 Outline Dimensions ....................................................................... 23 Ordering Guides......................................................................... 24
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 24
AD5346/AD5347/AD5348 SPECIFICATIONS
Table 1. VDD = 2.5 V to 5.5 V; VREF = 2 V; RL = 2 k to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted
Parameter DC PERFORMANCE3,4 AD5346 Resolution Relative Accuracy Differential Nonlinearity AD5347 Resolution Relative Accuracy Differential Nonlinearity AD5348 Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error Lower Deadband5 Upper Deadband5 Offset Error Drift6 Gain Error Drift6 DC Power Supply Rejection Ratio6 DC Crosstalk6 DAC REFERENCE INPUT6 VREF Input Range VREF Input Range VREF Input Impedance
2
Min
B Version1 Typ Max
Unit
Conditions/Comments
8 0.15 0.02 10 0.5 0.05 12 2 0.2 0.4 0.1 10 10 -12 -5 -60 200
1 0.25
Bits LSB LSB Bits LSB LSB Bits LSB LSB % of FSR % of FSR mV mV ppm of FSR/C ppm of FSR/C dB V
Guaranteed monotonic by design over all codes
4 0.5
Guaranteed monotonic by design over all codes
16 1 3 1 60 60
Guaranteed monotonic by design over all codes
Lower deadband exists only if offset error is negative VDD = 5 V; upper deadband exists only if VREF = VDD
VDD = 10% RL = 2 k to GND, 2 k to VDD; CL = 200 pF to GND; Gain = +1 Buffered reference mode Unbuffered reference mode Buffered reference mode and power-down mode Gain = +1; input impedance = RDAC Gain = +2; input impedance = RDAC Frequency = 10 kHz Frequency = 10 kHz Rail-to-rail operation
1 0.25 >10 90 45 -90 -75 0.001 VDD - 0.001 0.5 25 16 2.5 5
VDD VDD
Reference Feedthrough Channel-to-Channel Isolation OUTPUT CHARACTERISTICS6 Minimum Output Voltage4, 7 Maximum Output Voltage4, 7 DC Output Impedance Short Circuit Current Power-Up Time LOGIC INPUTS6 Input Current VIL, Input Low Voltage
V V M k k dB dB V min V max mA mA s s
VDD = 5 V VDD = 3 V Coming out of power-down mode; VDD = 5 V Coming out of power-down mode; VDD = 3 V
1 0.8 0.7 0.6 1.7 5
VIH, Input High Voltage Pin Capacitance
A V V V V pF
VDD = 5 V 10% VDD = 3 V 10% VDD = 2.5 V VDD = 2.5 V to 5.5 V
Rev. 0 | Page 3 of 24
AD5346/AD5347/AD5348
Parameter LOGIC OUTPUTS6 VDD = 4.5 V to 5.5 V Output Low Voltage, VOL Output High Voltage, VOH VDD = 2.5 V to 3.6 V Output Low Voltage, VOL Output High Voltage, VOH POWER REQUIREMENTS VDD IDD (Normal Mode) VDD = 4.5 V to 5.5 V VDD = 2.5 V to 3.6 V IDD (Power-Down Mode) VDD = 4.5 V to 5.5 V VDD = 2.5 V to 3.6 V
See footnotes after the AC Characteristics table.
2
Min
B Version1 Typ Max
Unit
Conditions/Comments
0.4 VDD - 1 0.4 VDD - 0.5 2.5 1 0.8 5.5 1.65 1.4
V V V V V mA mA
ISINK = 200 A ISOURCE = 200 A ISINK = 200 A ISOURCE = 200 A
VIH = VDD, VIL = GND All DACs in unbuffered mode. In buffered mode, extra current is typically x A per DAC, where x = 5 A + VREF/RDAC VIH = VDD, VIL = GND
0.4 0.12
1 1
A A
AC CHARACTERISTICS6
Table 2. VDD = 2.5 V to 5.5 V; RL = 2 k to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted
Parameter Output Voltage Settling Time AD5346 AD5347 AD5348 Slew Rate Major Code Transition Glitch Energy Digital Feedthrough Digital Crosstalk Analog Crosstalk DAC-to-DAC Crosstalk Multiplying Bandwidth Total Harmonic Distortion
2
Min
B Version1 Typ Max 6 7 8 0.7 8 0.5 1 1 3.5 200 -70 8 9 10
Unit s s s V/s nV-s nV-s nV-s nV-s nV-s kHz dB
Conditions/Comments VREF = 2 V 1/4 scale to 3/4 scale change (40 H to C0 H) 1/4 scale to 3/4 scale change (100 H to 300 H) 1/4 scale to 3/4 scale change (400 H to C00 H) 1 LSB change around major carry
VREF = 2 V 0.1 V p-p; unbuffered mode VREF = 2. V 0.1 V p-p; frequency = 10 kHz; unbuffered mode
1 2
Temperature range: B Version: -40C to +105C; typical specifications are at 25C. See Terminology section. 3 Linearity is tested using a reduced code range: AD5346 (Code 8 to 255); AD5347 (Code 28 to 1023); AD5348 (Code 115 to 4095). 4 DC specifications tested with outputs unloaded. 5 This corresponds to x codes. x = deadband voltage/LSB size. 6 Guaranteed by design and characterization, not production tested. 7 For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, VREF = VDD and the offset plus gain error must be positive.
200A IOL
TO OUTPUT PIN
CL 50pF 200A IOH
VOH(min) + VOL(max) 2
03331-0-002
Figure 2. Load Circuit for Digital Output Timing Specifications
Rev. 0 | Page 4 of 24
AD5346/AD5347/AD5348 TIMING CHARACTERISTICS1, 2, 3
Table 3. VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted
Parameter Data Write Mode (Figure 3) t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 Data Readback Mode (Figure 4) t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26
1 2
Limit at TMIN, TMAX 0 0 20 5 4.5 5 5 4.5 5 4.5 20 10 20 20 0 0 0 0 20 30 0 22 30 4 30 22 30 30 30 30 50
Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns max ns max ns min ns max ns max ns max ns min ns min ns min ns min
Condition/Comments CS to WR setup time CS to WR hold time WR pulse width Data, GAIN, BUF setup time Data, GAIN, BUF hold time Synchronous mode. WR falling to LDAC falling. Synchronous mode. LDAC falling to WR rising. Synchronous mode. WR rising to LDAC rising. Asynchronous mode. LDAC rising to WR rising. Asynchronous mode. WR rising to LDAC falling. LDAC pulse width CLR pulse width Time between WR cycles A0, A1, A2 setup time A0, A1, A2 hold time A0, A1, A2 to CS setup time A0, A1, A2 to CS hold time CS to falling edge of RD RD pulse width; VDD = 3.6 V to 5.5 V RD pulse width; VDD = 2.5 V to 3.6 V CS to RD hold time Data access time after falling edge of RD; VDD = 3.6 V to 5.5 V Data access time after falling edge of RD VDD = 2.5 V to 3.6 V Bus relinquish time after rising edge of RD CS falling edge to data; VDD = 3.6 V to 5.5 V CS falling edge to data; VDD = 2.5 V to 3.6 V Time between RD cycles Time from RD to WR Time from WR to RD, VDD = 3.6 V to 5.5 V Time from WR to RD, VDD = 2.5 V to 3.6 V
Guaranteed by design and characterization, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 3 See Figure 2.
t1
CS
t2
A0-A2
t3
WR
t13
t16
CS
t17
t4
DATA, GAIN, BUF LDAC1
t5
t18
t6 t7 t9 t8
RD
t20 t19 t24
t10
t11
DATA
t21
t22
LDAC2
CLR A0-A2
t12 t14 t15
03331-0-003
t23
WR
t25
NOTES 1. SYNCHRONOUS LDAC UPDATE MODE 2. ASYNCHRONOUS LDAC UPDATE MODE
Figure 3. Parallel Interface Write Timing Diagram
Figure 4. Parallel Interface Read Timing Diagram
Rev. 0 | Page 5 of 24
03331-0-004
t26
AD5346/AD5347/AD5348 ABSOLUTE MAXIMUM RATINGS
Table 4. TA = 25C, unless otherwise noted
Parameter VDD to GND Digital Input Voltage to GND Digital Output Voltage to GND Reference Input Voltage to GND VOUT to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Junction Temperature 38-Lead TSSOP Package Power Dissipation JA Thermal Impedance JC Thermal Impedance 40-Lead LFCSP Package Power Dissipation JA Thermal Impedance (3-layer board) Lead Temperature, Soldering (10 sec) IR Reflow, Peak Temperature Rating -0.3 V to +7 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -40C to +105C -65C to +150C 150C (TJ max - TA)/ JA mW 98.3C/W 8.9C/W (TJ max - TA)/ JA mW 29.6C/W 300C 220C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 6 of 24
AD5346/AD5347/AD5348 AD5346 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VREFAB VREFCD GAIN
32
CLR
VREFGH
1
38 PD 37 CLR 36 GAIN 35 WR 34 RD
VDD
VDD
VREFGH
VREFEF
VREFEF 2 VREFCD 3 VDD 4 VREFAB 5 VOUTA 6 VOUTB 7 VOUTC 8 8-BIT
40
39
38
37
36
35
34
33
31 30 RD 29 CS 28 DB7
VOUTA 1 VOUTB 2 VOUTC 3 VOUTD 4 AGND 5 AGND 6 VOUTE 7 VOUTF 8 VOUTG 9 VOUTH 10
11 12 13 14 15 16 17 18 19 20
33 CS 32 DB7
AD5346
WR
27 DB6 26 DB5 25 DB4 24 DB3 23 DB2 22 DB1 21 DB0
03331-0-006
TOP VIEW 31 DB6 (Not to Scale) 9 30 DB5 VOUTD AGND 10 VOUTE 11 VOUTF 12 VOUTG 13 VOUTH 14 DGND 15 BUF 16 LDAC 17 A0 18 A1 19
29 DB4 28 DB3 27 DB2 26 DB1 25 DB0 24 DGND 23 DGND 22 DGND
03331-0-005
8-BIT
AD5346
TOP VIEW (Not to Scale)
LDAC
A0
DGND
A1
A2
DGND
PD
DGND
DGND
21 DGND 20 A2
Figure 6. AD5346 Pin Configuration--LFCSP
Figure 5. AD5346 Pin Configuration--TSSOP
Table 5. AD5346 Pin Function Descriptions
Pin Number TSSOP LFCSP 1 35 2 36 3 37 4 38, 39 Mnemonic VREFGH VREFEF VREFCD VDD Function Reference Input for DACs G and H. Reference Input for DACs E and F. Reference Input for DACs C and D. Power Supply Pin(s). This part can operate from 2.5 V to 5.5 V, and the supply should be decoupled with a 10 F capacitor in parallel with a 0.1 F capacitor to GND. Both VDD pins on the LFCSP package must be at the same potential. Reference Input for DACs A and B. Output of DAC X. Buffered output with rail-to-rail operation. Analog Ground. Ground reference for analog circuitry. Digital Ground. Ground reference for digital circuitry. Buffer Control Pin. Controls whether the reference input to the DAC is buffered or unbuffered. Active Low Control Input. Updates the DAC registers with the contents of the input registers, which allows all DAC outputs to be simultaneously updated. LSB Address Pin. Selects which DAC is to be written to. Address Pin. Selects which DAC is to be written to. MSB Address Pin. Selects which DAC is to be written to. Eight Parallel Data Inputs. DB7 is the MSB of these eight bits. Active Low Chip Select Input. Used in conjunction with WR to write data to the parallel interface, or with RD to read back data from a DAC. Active Low Read Input. Used in conjunction with CS to read data back from the internal DACs. Active Low Write Input. Used in conjunction with CS to write data to the parallel interface. Gain Control Pin. Controls whether the output range from the DAC is 0 V to VREF or 0 V to 2 x VREF. Asynchronous Active Low Control Input. Clears all input registers and DAC registers to zeros. Power-Down Pin. This active low control pin puts all DACs into power-down mode.
5 6-9, 11-14 10 15, 21-24 16 17 18 19 20 25-32 33 34 35 36 37 38
40 1-4, 7-10 5, 6 11, 17-20 12 13 14 15 16 21-28 29 30 31 32 33 34
VREFAB VOUTX AGND DGND BUF LDAC A0 A1 A2 DB0-DB7 CS RD WR GAIN CLR PD
Rev. 0 | Page 7 of 24
DGND
BUF
AD5346/AD5347/AD5348 AD5347 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VREFAB VREFCD GAIN
32
CLR
VDD
VDD
VREFGH
1
38 PD 37 CLR 36 GAIN 35 WR 34 RD
VREFGH
VREFEF
VREFEF 2 VREFCD 3 VDD 4 VREFAB 5 VOUTA 6 VOUTB 7 VOUTC 8 10-BIT
40
39
38
37
36
35
34
33
31 30 RD 29 CS 28 DB9
VOUTA 1 VOUTB 2 VOUTC 3 VOUTD 4 AGND 5 AGND 6 VOUTE 7 VOUTF 8 VOUTG 9 VOUTH 10
11 12 13 14 15 16 17 18 19 20
33 CS 32 DB9
AD5347
WR
27 DB8 26 DB7 25 DB6 24 DB5 23 DB4 22 DB3 21 DB2
03331-0-008
TOP VIEW 31 DB8 (Not to Scale) 30 DB7 VOUTD 9 AGND 10 VOUTE 11 VOUTF 12 VOUTG 13 VOUTH 14 DGND 15 BUF 16 LDAC 17 A0 18 A1 19
29 DB6 28 DB5 27 DB4 26 DB3 25 DB2 24 DB1 23 DB0 22 DGND
03331-0-007
10-BIT
AD5347
TOP VIEW (Not to Scale)
LDAC
A0
A1
A2
PD
DB0
DGND
DGND
21 DGND 20 A2
Figure 8. AD5347 Pin Configuration--LFCSP
Figure 7. AD5347 Pin Configuration--TSSOP
Table 6. AD5347 Pin Function Descriptions
Pin Number TSSOP LFCSP 1 35 2 36 3 37 4 38, 39 Mnemonic VREFGH VREFEF VREFCD VDD Function Reference Input for DACs G and H. Reference Input for DACs E and F. Reference Input for DACs C and D. Power Supply Pin(s). This part can operate from 2.5 V to 5.5 V, and the supply should be decoupled with a 10 F capacitor in parallel with a 0.1 F capacitor to GND. Both VDD pins on the LFCSP package must be at the same potential. Reference Input for DACs A and B. Output of DAC X. Buffered output with rail-to-rail operation. Analog Ground. Ground reference for analog circuitry. Digital Ground. Ground reference for digital circuitry. Buffer Control Pin. Controls whether the reference input to the DAC is buffered or unbuffered. Active Low Control Input. Updates the DAC registers with the contents of the input registers, which allows all DAC outputs to be simultaneously updated. LSB Address Pin. Selects which DAC is to be written to. Address Pin. Selects which DAC is to be written to. MSB Address Pin. Selects which DAC is to be written to. Ten Parallel Data Inputs. DB9 Is the MSB of these ten bits. Active Low Chip Select Input. Used in conjunction with WR to write data to the parallel interface, or with RD to read back data from a DAC. Active Low Read Input. Used in conjunction with CS to read data back from the internal DACs. Active Low Write Input. Used in conjunction with CS to write data to the parallel interface. Gain Control Pin. Controls whether the output range from the DAC is 0 V to VREF or 0 V to 2 x VREF. Asynchronous Active Low Control Input. Clears all input registers and DAC registers to zeros. Power-Down Pin. This active low control pin puts all DACs into power-down mode.
5 6-9, 11-14 10 15, 21-22 16 17 18 19 20 23-32 33 34 35 36 37 38
40 1-4, 7-10 5, 6 11, 17-18 12 13 14 15 16 19-28 29 30 31 32 33 34
VREFAB VOUTX AGND DGND BUF LDAC A0 A1 A2 DB0-DB9 CS RD WR GAIN CLR PD
Rev. 0 | Page 8 of 24
DGND
BUF
DB1
AD5346/AD5347/AD5348 AD5348 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VREFAB VREFCD GAIN
32
CLR
VDD
VDD
VREFGH
1
38 PD 37 CLR 36 GAIN 35 WR 34 RD
VREFGH
VREFEF
VREFEF 2 VREFCD 3 VDD 4 VREFAB 5 VOUTA 6 VOUTB 7 VOUTC 8 12-BIT
40
39
38
37
36
35
34
33
31 30 RD 29 CS 28 DB11
VOUTA 1 VOUTB 2 VOUTC 3 VOUTD 4 AGND 5 AGND 6 VOUTE 7 VOUTF 8 VOUTG 9 VOUTH 10
11 12 13 14 15 16 17 18 19 20
33 CS 32 DB11
AD5348
WR
27 DB10 26 DB9 25 DB8 24 DB7 23 DB6 22 DB5 21 DB4
03331-0-010
TOP VIEW 31 DB10 (Not to Scale) 30 DB9 VOUTD 9 AGND 10 VOUTE 11 VOUTF 12 VOUTG 13 VOUTH 14 DGND 15 BUF 16 LDAC 17 A0 18 A1 19
29 DB8 28 DB7 27 DB6 26 DB5 25 DB4 24 DB3 23 DB2 22 DB1
03331-0-009
12-BIT
AD5348
TOP VIEW (Not to Scale)
LDAC
A0
A1
A2
DB0
PD
DB1
DB2
DGND
21 DB0 20 A2
Figure 10. AD5348 Pin Configuration--LFCSP
Figure 9. AD5348 Pin Configuration--TSSOP
Table 7. AD5348 Pin Function Descriptions
Pin Number TSSOP LFCSP 1 35 2 36 3 37 4 38, 39 Mnemonic VREFGH VREFEF VREFCD VDD Function Reference Input for DACs G and H. Reference Input for DACs E and F. Reference Input for DACs C and D. Power Supply Pin(s). This part can operate from 2.5 V to 5.5 V, and the supply should be decoupled with a 10 F capacitor in parallel with a 0.1 F capacitor to GND. Both VDD pins on the LFCSP package must be at the same potential. Reference Input for DACs A and B. Output of DAC X. Buffered output with rail-to-rail operation. Analog Ground. Ground reference for analog circuitry. Digital Ground. Ground reference for digital circuitry. Buffer Control Pin. Controls whether the reference input to the DAC is buffered or unbuffered. Active Low Control Input. Updates the DAC registers with the contents of the input registers, which allows all DAC outputs to be simultaneously updated. LSB Address Pin. Selects which DAC is to be written to. Address Pin. Selects which DAC is to be written to. MSB Address Pin. Selects which DAC is to be written to. Twelve Parallel Data Inputs. DB11 is the MSB of these 12 bits. Active Low Chip Select Input. Used in conjunction with WR to write data to the parallel interface, or with RD to read back data from a DAC. Active Low Read Input. Used in conjunction with CS to read data back from the internal DACs. Active Low Write Input. Used in conjunction with CS to write data to the parallel interface. Gain Control Pin. Controls whether the output range from the DAC is 0 V to VREF or 0 V to 2 x VREF. Asynchronous Active Low Control Input. Clears all input registers and DAC registers to zeros. Power-Down Pin. This active low control pin puts all DACs into power-down mode.
5 6-9, 11-14 10 15 16 17 18 19 20 21-32 33 34 35 36 37 38
40 1-4, 7-10 5, 6 11 12 13 14 15 16 17-28 29 30 31 32 33 34
VREFAB VOUTX AGND DGND BUF LDAC A0 A1 A2 DB0-DB11 CS RD WR GAIN CLR PD
Rev. 0 | Page 9 of 24
BUF
DB3
AD5346/AD5347/AD5348 TERMINOLOGY
Relative Accuracy For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the actual endpoints of the DAC transfer function. Typical INL versus code plots can be seen in Figure 14, Figure 15, and Figure 16. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Typical DNL versus code plots can be seen in Figure 17, Figure 18, and Figure 19. Gain Error This is a measure of the span error of the DAC, including any error in the gain of the buffer amplifier. It is the deviation in slope of the actual DAC transfer characteristic from the ideal and is expressed as a percentage of the full-scale range. This is illustrated in Figure 11. Offset Error This is a measure of the offset error of the DAC and the output amplifier. It is expressed as a percentage of the full-scale range. If the offset voltage is positive, the output voltage still positive at zero input code. This is shown in Figure 12. Because the DACs operate from a single supply, a negative offset cannot appear at the output of the buffer amplifier. Instead, there is a code close to zero at which the amplifier output saturates (amplifier footroom). Below this code there is a dead band over which the output voltage does not change. This is illustrated in Figure 13.
POSITIVE GAIN ERROR ACTUAL NEGATIVE GAIN ERROR
AMPLIFIER FOOTROOM (~1mV) OUTPUT VOLTAGE
GAIN ERROR AND OFFSET ERROR
ACTUAL
OUTPUT VOLTAGE IDEAL
DAC CODE
Figure 12. Positive Offset Error and Gain Error
IDEAL
GAIN ERROR AND OFFSET ERROR
ACTUAL
NEGATIVE OFFSET
DAC CODE
DEADBAND CODES
OUTPUT VOLTAGE
NEGATIVE OFFSET
IDEAL
03331-0-013
DAC CODE
Figure 11. Gain Error
03331-0-011
Figure 13. Negative Offset Error and Gain Error
Rev. 0 | Page 10 of 24
03331-0-012
POSITIVE OFFSET
AD5346/AD5347/AD5348
Offset Error Drift This is a measure of the change in offset error with changes in temperature. It is expressed in (ppm of full-scale range)/C. Gain Error Drift This is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/C. DC Power-Supply Rejection Ratio (PSRR) This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. It is measured in dB. VREF is held at 2 V and VDD is varied 10%. DC Crosstalk This is the dc change in the output level of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) and output change of another DAC. It is expressed in V. Reference Feedthrough This is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated, i.e., LDAC is high. It is expressed in dB. Channel-to-Channel Isolation This is a ratio of the amplitude of the signal at the output of one DAC to a sine wave on the reference inputs of the other DACs. It is measured by grounding one VREF pin and applying a 10 kHz, 4 V p-p sine wave to the other VREF pins. It is expressed in dB. Major-Code Transition Glitch Energy This is the energy of the impulse injected into the analog output when the DAC changes state. It is normally specified as the area of the glitch in nV-s and is measured when the digital code is changed by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11). Digital Feedthrough This is a measure of the impulse injected into the analog output of the DAC from the digital input pins of the device, but it is measured when the DAC is not being written to, CS held high. It is specified in nV-s and is measured with a full-scale change on the digital input pins, i.e., from all 0s to all 1s and vice versa. Digital Crosstalk This is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is expressed in nV-s. Analog Crosstalk This is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa) while keeping LDAC high. Then pulse LDAC low and monitor the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nV-s. DAC-to-DAC Crosstalk This is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) with the LDAC pin set low and monitoring the output of another DAC. The energy of the glitch is expressed in nV-s. Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. Total Harmonic Distortion (THD) This is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measure of the harmonics present on the DAC output. It is measured in dB.
Rev. 0 | Page 11 of 24
AD5346/AD5347/AD5348 TYPICAL PERFORMANCE CHARACTERISTICS
1.0 TA = 25C VDD = 5V
0.3 TA = 25C VDD = 5V 0.2
0.5
INL ERROR (LSB)
0
DNL ERROR (LSB)
03331-0-014
0.1
0
-0.1
-0.5
03331-0-017
-0.2
-1.0 0 50 100 CODE 150 200
-0.3 0 50 100 CODE 150 200
250
250
Figure 14. AD5346 Typical INL Plot
Figure 17. AD5346 Typical DNL Plot
3 TA = 25C VDD = 5V 2
0.6 TA = 25C VDD = 5V 0.4
INL ERROR (LSB)
DNL ERROR (LSB)
1
0.2
0
0
-1
-0.2
-3 0 200 400 CODE 600 800
03331-0-015
-0.6 0 200 400 CODE 600 800
1000
1000
Figure 15. AD5347 Typical INL Plot
Figure 18. AD5347 Typical DNL Plot
12 TA = 25C VDD = 5V 8
1.0 TA = 25C VDD = 5V 0.5
INL ERROR (LSB)
4
DNL ERROR (LSB)
0
0
-4
-0.5
03331-0-016
03331-0-019
-8
-12 0 1000 2000 CODE 3000
-1.0 0 1000 2000 CODE 3000
4000
4000
Figure 16. AD5348 Typical INL Plot
Figure 19. AD5348 Typical DNL Plot
Rev. 0 | Page 12 of 24
03331-0-018
-2
-0.4
AD5346/AD5347/AD5348
0.5 0.4 0.3 0.2 VDD = 5V TA = 25C
0.2 0.1 TA = 25C VREF = 2V
MAX INL
0
ERROR (% FSR)
GAIN ERROR
ERROR (LSB)
MAX DNL
0.1 0 -0.1 -0.2
-0.1 -0.2 -0.3 -0.4 OFFSET ERROR
03331-0-034
MIN DNL
MIN INL
-0.3
03331-0-031
-0.4 -0.5
-0.5 -0.6 0 1 2 3 VDD (V) 4 5 6
0
1
2
VREF(V)
3
4
5
Figure 20. AD5346 INL and DNL Error vs. VREF
Figure 23. Offset Error and Gain Error vs. VDD
0.5 0.4 0.3 0.2 VDD = 5V VREF = 2V
5
MAX INL
4
5V SOURCE
3V SOURCE
ERROR (LSB)
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -40
MAX DNL
VOUT (V)
3
2
MIN DNL
1
03331-0-032
MIN INL
-20 0 60 20 40 TEMPERATURE (C) 80 100
0 0 1 2 3 4 SINK/SOURCE CURRENT (mA) 5 6
Figure 21. AD5346 INL and DNL Error vs. Temperature
Figure 24. VOUT Source and Sink Current Capability
1.0 VDD = 5V VREF = 2V 0.5
ERROR (% FSR)
1.0 0.9 0.8 0.7 0.6 VDD = 5V TA = 25C
0
IDD (mA)
OFFSET ERROR
0.5 0.4 0.3
-0.5
0.2
03331-0-033
GAIN ERROR -1.0 -40
0.1 0 ZERO SCALE HALF SCALE DAC CODE FULL SCALE
-20
0
60 20 40 TEMPERATURE (C)
80
100
Figure 22. AD5346 Offset Error and Gain Error vs. Temperature
Figure 25. Supply Current vs. DAC Code
Rev. 0 | Page 13 of 24
03331-0-036
03331-0-035
5V SINK
3V SINK
AD5346/AD5347/AD5348
1.4 1.2 VREF = 2V GAIN = 1 UNBUFFERED TA = -40C TA = +25C
TA = 25C VDD = 5V VREF = 5V
1.0
VOUTA
IDD (mA)
0.8 0.6 TA = +105C
CH1
LDAC
0.4
03331-0-037
CH2
0.2 0 2.5
3.0
3.5 4.0 4.5 SUPPLY VOLTAGE (V)
5.0
5.5
CH1 1V, CH2 5V, TIME BASE = 1s/DIV
Figure 26. Supply Current vs. Supply Voltage
Figure 29. Half-Scale Settling (1/4 to 3/4 Scale Code)
1.0 0.9 0.8 TA = 25C
TA = 25C VDD = 5V VREF = 2V CH1 VDD
IDD POWER-DOWN (A)
0.7 0.6 0.5 0.4 0.3 0.2 0.1
03331-0-038
VOUTA CH2
03331-0-041
0 2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
CH1 2V, CH2 200mV, TIME BASE = 200s/DIV
VDD (V)
Figure 27. Power-Down Current vs. Supply Voltage
Figure 30. Power-On Reset to 0 V
2.5 TA = 25C VDD = 5V 2.0
VOUT1 CH2
1.5
IDD (mA)
1.0
PD
VDD = 3V 0.5
03331-0-039
CH1
0 0 1 2 3 VLOGIC (V) 4 5
CH1 2.00V, CH2 1.00V, TIME BASE = 20s/DIV
Figure 28. Supply Current vs. Logic Input Voltage
Figure 31. Exiting Power-Down to Midscale
Rev. 0 | Page 14 of 24
03331-0-042
03331-0-040
AD5346/AD5347/AD5348
21
0.02 VDD = 5V TA = 25C 0.01
18 15
FREQUENCY
VDD = 3V 12
VDD = 5V
FULL-SCALE ERROR (V)
0
9
6 3
-0.01
03331-0-046
03331-0-043
0 0.6
-0.02 0 1 2 3 VREF (V) 4 5 6
0.8
1.0 IDD (mA)
1.2
1.4
Figure 32. IDD Histogram with VDD = 3 V and VDD = 5 V
Figure 35. Full-Scale Error vs. VREF
2.50
1.999
2.49
1.998
VOUT (V)
2.48
1.997
03331-0-044
2.47 1s/DIV
1.996
0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475
Figure 33. AD5348 Major Code Transition Glitch Energy
Figure 36. DAC-to-DAC Crosstalk
10
0 -10
-20
dB
-30
-40
03331-0-045
-50 -60 10 100 1k 10k 100k FREQUENCY (Hz) 1M
10M
Figure 34. Multiplying Bandwidth (Small Signal Frequency Response)
Rev. 0 | Page 15 of 24
511
03331-0-047
AD5346/AD5347/AD5348 FUNCTIONAL DESCRIPTION
The AD5346/AD5347/AD5348 are octal resistor-string DACs fabricated by a CMOS process with resolutions of 8, 10, and 12 bits, respectively. They are written to using a parallel interface. They operate from single supplies of 2.5 V to 5.5 V, and the output buffer amplifiers offer rail-to-rail output swing. The gain of the buffer amplifiers can be set to 1 or 2 to give an output voltage range of 0 V to VREF or 0 V to 2 x VREF. The AD5346/ AD5347/AD5348 have reference inputs that may be buffered to draw virtually no current from the reference source. The devices have a power-down feature that reduces current consumption to only 100 nA @ 3 V.
VREF R R TO OUTPUT AMPLIFIER
R
R
03331-0-021
R
DIGITAL-TO-ANALOG SECTION
The architecture of one DAC channel consists of a reference buffer and a resistor-string DAC followed by an output buffer amplifier. The voltage at the VREF pin provides the reference voltage for the DAC. Figure 37 shows a block diagram of the DAC architecture. Because the input coding to the DAC is straight binary, the ideal output voltage is given by
Figure 38. Resistor String
DAC REFERENCE INPUT
The DACs operate with an external reference. The AD5346/ AD5347/AD5348 have a reference input for each pair of DACs. The reference inputs may be configured as buffered or unbuffered. This option is controlled by the BUF pin. In buffered mode (BUF = 1), the current drawn from an external reference voltage is virtually zero because the impedance is at least 10 M. The reference input range is 1 V to VDD. In unbuffered mode (BUF = 0), the user can have a reference voltage as low as 0.25 V and as high as VDD because there is no restriction due to headroom and footroom of the reference amplifier. The impedance is still large at typically 90 k for 0 V to VREF mode and 45 k for 0 V to 2 x VREF mode. If using an external buffered reference (such as REF192), there is no need to use the on-chip buffer.
VOUT = VREF x where:
D x Gain 2N
D is the decimal equivalent of the binary code, which is loaded to the DAC register: 0-255 for AD5346 (8 bits) 0-1023 for AD5347 (10 bits) 0-4095 for AD5348 (12 bits) N is the DAC resolution. Gain is the output amplifier gain (1 or 2).
VREFAB
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating output voltages to within 1 mV of either rail. Its actual range depends on VREF, GAIN, the load on VOUT, and offset error.
VOUTA
03331-0-020
BUF
REFERENCE BUFFER (GAIN = +1 OR +2)
INPUT REGISTER
DAC REGISTER
RESISTOR STRING OUTPUT BUFFER AMPLIFIER
If a gain of +1 is selected (GAIN = 0), the output range is 0.001 V to VREF. If a gain of +2 is selected (GAIN = +1), the output range is 0.001 V to 2 x VREF. However, because of clamping, the maximum output is limited to VDD - 0.001 V. The output amplifier is capable of driving a load of 2 k to GND or VDD, in parallel with 500 pF to GND or VDD. The source and sink capabilities of the output amplifier can be seen in Figure 24. The slew rate is 0.7 V/s with a half-scale settling time to 0.5 LSB (at 8 bits) of 6 s with the output unloaded. See Figure 29.
Figure 37. Single DAC Channel Architecture
RESISTOR STRING
The resistor string section is shown in Figure 38. It is simply a string of resistors, each of value R. The digital code loaded to the DAC register determines at what node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic.
Rev. 0 | Page 16 of 24
AD5346/AD5347/AD5348
PARALLEL INTERFACE
The AD5346/AD5347/AD5348 load their data as a single 8-, 10-, or 12-bit word. where IDYNAMIC = cvf and c = capacitance or the data bus v = VDD f = readback frequency
Double-Buffered Interface
The AD5346/AD5347/AD5348 DACs all have double-buffered interfaces consisting of an input register and a DAC register. DAC data, BUF, and GAIN inputs are written to the input register under control of the Chip Select (CS) and Write (WR) pins. Access to the DAC register is controlled by the LDAC function. When LDAC is high, the DAC register is latched and the input register may change state without affecting the contents of the DAC register. However, when LDAC is brought low, the DAC register becomes transparent and the contents of the input register are transferred to it. The gain and buffer control signals are also double-buffered and are updated only when LDAC is taken low. This is useful if the user requires simultaneous updating of all DACs and peripherals. The user can write to all input registers individually and then, by pulsing the LDAC input low, all outputs update simultaneously. These parts contain an extra feature whereby the DAC register is not updated unless its input register has been updated since the last time that LDAC was brought low. Normally, when LDAC is brought low, the DAC registers are filled with the contents of the input registers. In the case of the AD5346/ AD5347/AD5348, the part updates the DAC register only if the input register has been changed since the last time the DAC register was updated. This removes unnecessary crosstalk.
Load DAC Input (LDAC)
LDAC transfers data from the input register to the DAC register, and therefore updates the outputs. The LDAC function enables double-buffering of the DAC data, GAIN data, and BUF. There are two LDAC modes:
* Synchronous Mode. In this mode, the DAC register is updated after new data is read in on the rising edge of the WR input. LDAC can be tied permanently low or pulsed as shown in Figure 3. Asynchronous Mode. In this mode, the outputs are not updated at the same time that the input register is written to. When LDAC goes low, the DAC register is updated with the contents of the input register.
*
POWER-ON RESET
The AD5346/AD5347/AD5348 have a power-on reset function, so that they power up in a defined state. The power-on state is
* * * *
Normal operation Reference input buffered 0 V to VREF output range Output voltage set to 0 V
Both input and DAC registers are filled with zeros and remain so until a valid write sequence is made to the device. This is particularly useful in applications where it is important to know the state of the DAC outputs while the device is powering up.
Clear Input (CLR)
CLR is an active low, asynchronous clear that resets the input and DAC registers.
POWER-DOWN MODE
The AD5346/AD5347/AD5348 have low power consumption, dissipating typically 2.4 mW with a 3 V supply and 5 mW with a 5 V supply. Power consumption can be further reduced when the DACs are not in use by putting them into power-down mode, which is selected by taking the PD pin low. When the PD pin is high, the DACs work normally with a typical power consumption of 1 mA at 5 V (0.8 mA at 3 V). In power-down mode, however, the supply current falls to 400 nA at 5 V (120 nA at 3 V) when the DACs are powered down. Not only does the supply current drop, but the output stage is also internally switched from the output of the amplifier, making it open-circuit. This has the advantage that the outputs are threestate while the part is in power-down mode, and provides a defined input condition for whatever is connected to the outputs of the DAC amplifiers. The output stage is illustrated in Figure 39.
RESISTOR STRING DAC AMPLIFIER
VOUT
03331-0-022
Chip Select Input (CS)
CS is an active low input that selects the device.
Write Input (WR)
WR is an active low input that controls writing of data to the device. Data is latched into the input register on the rising edge of WR.
Read Input (RD)
RD is an active low input that controls when data is read back from the internal DAC registers. On the falling edge of RD, data is shifted onto the data bus. Under the conditions of a high capacitive load and high supplies, the user must ensure that the dynamic current remains at an acceptable level, therefore ensuring that the die temperature is within specification. The die temperature can be calculated as
TDIE = TAMBIENT + VDD (IDD + IDYNAMIC)JA
POWER-DOWN CIRCUITRY
Figure 39. Output Stage During Power-Down
Rev. 0 | Page 17 of 24
AD5346/AD5347/AD5348
The bias generator, the output amplifier, the resistor string, and all other associated linear circuitry are all shut down when the power-down mode is activated. However, the contents of the registers are unaffected when in power-down. The time to exit power-down is typically 2.5 s for VDD = 5 V and 5 s when VDD = 3 V. This is the time from a rising edge on the PD pin to when the output voltage deviates from its power-down voltage. See Figure 31. The AD5347 and AD5348 data bus must be at least 10 and 12 bits wide, respectively, and are best suited to a 16-bit data bus system. Examples of data formats for putting GAIN and BUF on a 16-bit data bus are shown in Figure 40. Note that any unused bits above the actual DAC data may be used for GAIN and BUF.
AD5347
X X X X BUF GAIN DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
SUGGESTED DATA BUS FORMATS
In many applications, the GAIN and BUF pins are hardwired. However, if more flexibility is required, they can be included in a data bus. This enables the user to software program GAIN, giving the option of doubling the resolution in the lower half of the DAC range. In a bused system, GAIN and BUF may be treated as data inputs because they are written to the device during a write operation and take effect when LDAC is taken low. This means that the reference buffers and the output amplifier gain of multiple DAC devices can be controlled using common GAIN and BUF lines. Note that GAIN and BUF are not read back during an RD operation.
AD5348
X X BUF GAIN DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
03331-0-048
X = UNUSED BIT
Figure 40. AD5347/AD5348 Data Format for Word Load with GAIN and BUF Data on 16-Bit Bus
Table 8. AD5346/AD5347/AD5348 Truth Table
CLR LDAC CS 1 X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 WR X 1 X 01 01 01 01 01 01 01 01 1 1 1 1 1 1 1 1 X 0 RD X 1 X 1 1 1 1 1 1 1 1 10 10 10 10 10 10 10 10 1 0 1 1 1 1 0 X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 0 X X X = Don't Care A2 X X X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X X A1 X X X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X X A0 X X X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X X Function No Data Transfer No Data Transfer Clear All Registers Load DAC A Input Register Load DAC B Input Register Load DAC C Input Register Load DAC D Input Register Load DAC E Input Register Load DAC F Input Register Load DAC G Input Register Load DAC H Input Register Read Back DAC Register A Read Back DAC Register B Read Back DAC Register C Read Back DAC Register D Read Back DAC Register E Read Back DAC Register F Read Back DAC Register G Read Back DAC Register H Update DAC Registers Invalid Operation
Rev. 0 | Page 18 of 24
AD5346/AD5347/AD5348 APPLICATIONS INFORMATION
TYPICAL APPLICATION CIRCUITS
The AD5346/AD5347/AD5348 can be used with a wide range of reference voltages, especially if the reference inputs are configured as unbuffered, in which case the devices offer full, one-quadrant multiplying capability over a reference range of 0.25 V to VDD. More typically, these devices may be used with a fixed, precision reference voltage. Figure 41 shows a typical setup for the devices when using an external reference connected to the reference inputs. Suitable references for 5 V operation are the AD780, ADR381, and REF192 (2.5 V references). For 2.5 V operation, suitable external references are the AD589 and the AD1580 (1.2 V band gap references).
VDD = 2.5V to 5.5V
EXT REF GND
BIPOLAR OPERATION USING THE AD5346/AD5347/AD5348
The AD5346/AD5347/AD5348 have been designed for singlesupply operation, but a bipolar output range is also possible by using the circuit shown in Figure 43. This circuit has an output voltage range of 5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820, an AD8519, or an OP196 as the output amplifier.
5V R4 20k 0.1F 10F R3 10k VIN VDD VOUT 0.1F VREF* +5V
5V AD820/AD8519/ OP196 -5V R1 10k R2 20k
03331-0-026
0.1F VIN EXT REF GND VOUT
10F
AD5346/AD5347/ AD5348
VOUT*
VDD VREF* VOUT*
GND
AD5346/AD5347/ AD5348
03331-0-024
AD780/ADR381/REF192 WITH VDD = 5V OR AD589/AD1580 WITH VDD = 2.5V *ONLY ONE CHANNEL OF VREF AND VOUT SHOWN
*ONLY ONE CHANNEL OF VREF AND VOUT SHOWN
GND
Figure 43. Bipolar Operation with the AD5346/ AD5347/AD5348
Figure 41. AD5346/AD5347/AD5348 Using an External Reference
The output voltage for any input code can be calculated as follows:
VOUT = [(1 + R4/R3) x (R2/(R1 + R2) x (2 x VREF x D/2N)] - R4 x VREF/R3
DRIVING VDD FROM THE REFERENCE VOLTAGE
If an output range of 0 V to VDD is required, the simplest solution is to connect the reference inputs to VDD. Because this supply may not be very accurate and may be noisy, the devices can be powered from the reference voltage, for example, by using a 5 V reference such as the ADM663 or ADM666, as shown in Figure 42.
6V TO 16V
where:
D is the decimal equivalent of the code loaded to the DAC. N is the DAC resolution. VREF is the reference voltage input.
with:
10F
0.1F VIN ADM663/ADM666 EXT REF SENSE VOUT(2)
VDD VREF* 0.1F VOUT*
VREF = 5 V R1 = R3 = 10 k R2 = R4 = 20 k VDD = 5 V GAIN = 2 VOUT = (10 x D/2N) - 5
03331-0-025
GND VSET GND SHDN
AD5346/AD5347/ AD5348
GND
*ONLY ONE CHANNEL OF VREF AND VOUT SHOWN
Figure 42. Using an ADM663/ADM666 as Power and Reference to the AD5346/AD5347/AD5348
Rev. 0 | Page 19 of 24
AD5346/AD5347/AD5348
DECODING MULTIPLE AD5346/AD5347/AD5348s
The CS pin on these devices can be used in applications to decode a number of DACs. In this application, all DACs in the system receive the same data and WR pulses, but only the CS to one of the DACs will be active at any one time, so data will only be written to the DAC whose CS is low. The 74HC139 is used as a 2-line to 4-line decoder to address any of the DACs in the system. To prevent timing errors from occurring, the enable input should be brought to its inactive state while the coded address inputs are changing state. Figure 44 shows a diagram of a typical setup for decoding multiple devices in a system. Once data has been written sequentially to all DACs in a system, all the DACs can be updated simultaneously using a common LDAC line. A common CLR line can also be used to reset all DAC outputs to 0 V.
AD5346/AD5347
A0 A1 A2 WR LDAC CLR A0 /AD5348 A1 A2 WR DATA INPUTS LD AC CLR CS
5V 0.1F 10F VIN VREF VREFAB VDD VOUTA 1k FAIL 1k PASS
AD5346/AD5347/ AD5348
VOUTB GND
1/2 CMP04
1/6 74HC05
Figure 45. Programmable Window Detector
PROGRAMMABLE CURRENT SOURCE
Figure 46 shows the AD5346/AD5347/AD5348 used as the control element of a programmable current source. In this example, the full-scale current is set to 1 mA. The output voltage from the DAC is applied across the current setting resistor of 4.7 k in series with the 470 adjustment potentiometer, which gives an adjustment of about 5%. Suitable transistors to place in the feedback loop of the amplifier include the BC107 and the 2N3904, which enable the current source to operate from a minimum VSOURCE of 6 V. The operating range is determined by the operating characteristics of the transistor. Suitable amplifiers include the AD820 and the OP295, both having rail-to-rail operation on their outputs. The current for any digital input code and resistor value can be calculated as follows:
I = G x VREF where: G is the gain of the buffer amplifier (1 or 2). D is the digital input code. N is the DAC resolution (8, 10, or 12 bits). R is the sum of the resistor plus adjustment potentiometer in k. D mA (2 x R)
N
AD5346/AD5347
A0 /AD5348 A1 A2 WR DATA LD AC INPUTS CLR CS 1Y0 1Y1 74HC139 1B 1Y2 1Y3 DGND
ENABLE CODED ADDRESS
1G 1A
VCC
AD5346/AD5347
A0 /AD5348 A1 A2 WR DATA LD AC INPUTS CLR CS
AD5346/AD5347
A0 /AD5348 A1 A2 WR DATA INPUTS LD AC CLR CS
DATA BUS
VDD
03331-0-027
VDD = 5V
Figure 44. Decoding Multiple DAC Devices
0.1F
10F VSOURCE
AD5346/AD5347/AD5348 AS DIGITALLY PROGRAMMABLE WINDOW DETECTORS
A digitally programmable upper/lower limit detector using two of the DACs in the AD5346/AD5347/AD5348 is shown in Figure 45. Any pair of DACs in the device may be used, but for simplicity the description refers to DACs A and B. The upper and lower limits for the test are loaded to DACs A and B which, in turn, set the limits on the CMP04. If a signal at the VIN input is not within the programmed window, an LED indicates the fail condition.
VIN EXT REF GND VDD VOUT 0.1F VREF* VOUT*
5V
LOAD
AD5346/AD5347/ AD5348
4.7k
03331-0-029
GND 470 *ONLY ONE CHANNEL OF VREF AND VOUT SHOWN
Figure 46. Programmable Current Source
Rev. 0 | Page 20 of 24
03331-0-028
PASS/ FAIL
AD5346/AD5347/AD5348
COARSE AND FINE ADJUSTMENT USING THE AD5346/AD5347/AD5348
Two of the DACs in the AD5346/AD5347/AD5348 can be paired together to form a coarse and fine adjustment function, as shown in Figure 47. As with the window comparator previously described, the description refers to DACs A and B. DAC A provides the coarse adjustment, while DAC B provides the fine adjustment. Varying the ratio of R1 and R2 changes the relative effect of the coarse and fine adjustments. With the resistor values shown, the output amplifier has unity gain for the DAC A output, so the output range is 0 V to (VREF - 1 LSB). For DAC B, the amplifier has a gain of 7.6 x 10-3, giving DAC B a range equal to 2 LSBs of DAC A. The circuit is shown with a 2.5 V reference, but reference voltages up to VDD may be used. The op amps indicated allow a rail-to-rail output swing.
VDD = 5V R4 390 R3 51.2k 5V
POWER SUPPLY BYPASSING AND GROUNDING
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5346/AD5347/ AD5348 is mounted should be designed so that the analog and digital sections are separated and are confined to certain areas of the board. This facilitates the use of ground planes that can be separated easily. A minimum etch technique is generally best for ground planes because it gives the best shielding. Digital and analog ground planes should be joined in one place only. If the AD5346/AD5347/AD5348 is the only device requiring an AGND-to-DGND connection, then the ground planes should be connected at the AGND and DGND pins of the AD5346/ AD5347/AD5348. If the AD5346/AD5347/AD5348 is in a system where multiple devices require AGND-to-DGND connections, the connection should be made at one point only, a star ground point that should be established as close as possible to the AD5346/AD5347/AD5348. The AD5346/AD5347/AD5348 should have ample supply bypassing of 10 F in parallel with 0.1 F on the supply located as close to the package as possible, ideally right up against the device. The 10 F capacitors are the tantalum bead type. The 0.1 F capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), such as the common ceramic types that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. The power supply lines of the device should use the largest trace possible to provide low impedance paths and to reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other to reduce the effects of feedthrough through the board. A microstrip technique is by far the best, but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground plane, while signal traces are placed on the solder side.
0.1F
10F
VIN EXT REF VOUT GND 0.1F VREFAB
VDD VOUTA R1 390 R2 51.2k
03331-0-030
VOUT
AD5346/AD5347/ AD5348
VOUTB
AD780/ADR381/REF192 WITH VDD = 5V GND
Figure 47. Coarse and Fine Adjustment
Rev. 0 | Page 21 of 24
AD5346/AD5347/AD5348
Table 9. Overview of AD53xx Parallel Devices
Part No. SINGLES AD5330 AD5331 AD5340 AD5341 DUALS AD5332 AD5333 AD5342 AD5343 QUADS AD5334 AD5335 AD5336 AD5344 OCTALS AD5346 AD5347 AD4348 Resolution 8 10 12 12 8 10 12 12 8 10 10 12 8 10 12 DNL 0.25 0.5 1.0 1.0 0.25 0.5 1.0 1.0 0.25 0.5 0.5 1.0 0.25 0.5 1.0 VREF Pins 1 1 1 1 2 2 2 1 2 2 4 4 4 4 4 Settling Time 6 s 7 s 8 s 8 s 6 s 7 s 8 s 8 s 6 s 7 s 7 s 8 s 6 s 7 s 8 s Additional Pin Functions BUF GAIN HBEN CLR Package TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP, LFCSP TSSOP, LFCSP TSSOP, LFCSP Pins 20 20 24 20 20 24 28 20 24 24 28 28 38, 40 38, 40 38, 40
Table 10. Overview of AD53xx Serial Devices
Part No. SINGLES AD5300 AD5310 AD5320 AD5301 AD5311 AD5321 DUALS AD5302 AD5312 AD5322 AD5303 AD5313 AD5323 QUADS AD5304 AD5314 AD5324 AD5305 AD5315 AD5325 AD5306 AD5316 AD5326 AD5307 AD5317 AD5327 OCTALS AD5308 AD5318 AD5328 Resolution 8 10 12 8 10 12 8 10 12 8 10 12 8 10 12 8 10 12 8 10 12 8 10 12 8 10 12 DNL 0.25 0.5 1.0 0.25 0.5 1.0 0.25 0.5 1.0 0.25 0.5 1.0 0.25 0.5 1.0 0.25 0.5 1.0 0.25 0.5 1.0 0.25 0.5 1.0 0.25 0.5 1.0 VREF Pins 0 (VREF = VDD) 0 (VREF = VDD) 0 (VREF = VDD) 0 (VREF = VDD) 0 (VREF = VDD) 0 (VREF = VDD) 2 2 2 2 2 2 1 1 1 1 1 1 4 4 4 2 2 2 2 2 2 Settling Time 4 s 6 s 8 s 6 s 7 s 8 s 6 s 7 s 8 s 6 s 7 s 8 s 6 s 7 s 8 s 6 s 7 s 8 s 6 s 7 s 8 s 6 s 7 s 8 s 6 s 7 s 8 s
Rev. 0 | Page 22 of 24
Interface SPI(R) SPI SPI 2-Wire 2-Wire 2-Wire SPI SPI SPI SPI SPI SPI SPI SPI SPI 2-Wire 2-Wire 2-Wire 2-Wire 2-Wire 2-Wire SPI SPI SPI SPI SPI SPI
Package SOT-23, MSOP SOT-23, MSOP SOT-23, MSOP SOT-23, MSOP SOT-23, MSOP SOT-23, MSOP MSOP MSOP MSOP TSSOP TSSOP TSSOP MSOP MSOP MSOP MSOP MSOP MSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP
Pins 6, 8 6, 8 6, 8 6, 8 6, 8 6, 8 8 8 8 16 16 16 10 10 10 10 10 10 16 16 16 16 16 16 16 16 16
AD5346/AD5347/AD5348 OUTLINE DIMENSIONS
9.80 9.70 9.60
38
20
4.50 4.40 4.30 6.40 BSC
1 19
PIN 1 1.20 MAX 8 0
0.15 0.05 COPLANARITY 0.10 0.50 BSC 0.27 0.17
SEATING PLANE
0.20 0.09
0.70 0.60 0.45
COMPLIANT TO JEDEC STANDARDS MO-153BD-1
Figure 48. 38-Lead Thin Shrink Small Outline Package [TSSOP] (RU-38) Dimensions shown in millimeters
6.00 BSC SQ 0.60 MAX
0.60 MAX PIN 1 INDICATOR
31 30 40 1
PIN 1 INDICATOR
TOP VIEW
5.75 BSC SQ
0.50 BSC 0.50 0.40 0.30
BOTTOM VIEW
21 20 10 11
4.25 4.10 SQ 3.95
0.25 MIN 4.50 REF
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08
1.00 0.85 0.80
SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
Figure 49. 40-Lead Lead Frame Chip Scale Package [LFCSP] (CP-40) Dimensions shown in millimeters
Rev. 0 | Page 23 of 24
AD5346/AD5347/AD5348
ORDERING GUIDES
Table 11. AD5346 Ordering Guide
Model AD5346BRU AD5346BRU-REEL AD5346BRU-REEL7 AD5346BCP AD5346BCP-REEL AD5346BCP-REEL7 Temperature Range -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C Package Description TSSOP (Thin Shrink Small Outline Package) TSSOP (Thin Shrink Small Outline Package) TSSOP (Thin Shrink Small Outline Package) LFCSP (Lead Frame Chip Scale Package) LFCSP (Lead Frame Chip Scale Package) LFCSP (Lead Frame Chip Scale Package) Package Option RU-38 RU-38 RU-38 CP-40 CP-40 CP-40
Table 12. AD5347 Ordering Guide
Model AD5347BRU AD5347BRU-REEL AD5347BRU-REEL7 AD5347BCP AD5347BCP-REEL AD5347BCP-REEL7 Temperature Range -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C Package Description TSSOP (Thin Shrink Small Outline Package) TSSOP (Thin Shrink Small Outline Package) TSSOP (Thin Shrink Small Outline Package) LFCSP (Lead Frame Chip Scale Package) LFCSP (Lead Frame Chip Scale Package) LFCSP (Lead Frame Chip Scale Package) Package Option RU-38 RU-38 RU-38 CP-40 CP-40 CP-40
Table 13. AD5348 Ordering Guide
Model AD5348BRU AD5348BRU-REEL AD5348BRU-REEL7 AD5348BCP AD5348BCP-REEL AD5348BCP-REEL7 Temperature Range -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C Package Description TSSOP (Thin Shrink Small Outline Package) TSSOP (Thin Shrink Small Outline Package) TSSOP (Thin Shrink Small Outline Package) LFCSP (Lead Frame Chip Scale Package) LFCSP (Lead Frame Chip Scale Package) LFCSP (Lead Frame Chip Scale Package) Package Option RU-38 RU-38 RU-38 CP-40 CP-40 CP-40
(c) 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03331-0-11/03(0)
Rev. 0 | Page 24 of 24

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