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DG221
Quad SPST CMOS Analog Switch with Latches
Features
D D D D D Accepts 150-ns Write Pulse Width 5-V On-Chip Regulator Built on PLUS-40 Process Latches Are Transparent with WR Low Low On-Resistance: 60 W
Benefits
D Compatible with Most mP Buses D Allows Wide Power Supply Tolerance Without Affecting TTL Compatibility D Reduced Power Consumption D Allows Flexibility of Design
Applications
D D D D D D mP Based Systems Automatic Test Equipment Communication Systems Data Acquisition Systems Medical Instrumentation Factory Automation
Description
The DG221 is a monolithic quad single-pole, single-throw analog switch designed for precision switching applications in communication, instrumentation and process control systems. Featuring independent onboard latches and a common WR pin, each DG221 can be memory mapped, and addressed as a single data byte for simultaneous switching. Designed on the Siliconix PLUS-40 CMOS process, the DG221 combines low power and low on-resistance (60 W typical) while handling continuous currents up to 20 mA. An epitaxial layer prevents latchup. The device features true bidirectional performance in the on condition. These switches guarantee a rail-to-rail blocking capability (44 V max), in the off condition.
Functional Block Diagram and Pin Configuration
Four Latchable SPST Switches per Package Dual-In-Line and SOIC
Truth Table
IN2 D2 S2 V+ WR S3 D3 IN3 X X 1
IN1 D1 S1 V- GND S4 D4 IN4
1 2 3 4 5 6 7 8 Input Latch
16 15 14 13 12 11 10 9 Top View
INX
0 1
WR
0 0
Switch
ON OFF Control data latched-in, switches on or off as selected by last INX Maintains previous state
Logic "0" v 0.8 V Logic "1" w 2.4 V
Ordering Information Temp Range
0_C to 70_C -40_C to 85_C -55_C to 125_C
Package
16-Pin Plastic DIP 16-Pin Narrow SOIC 16-Pin CerDIP
Part Number
DG221CJ DG221DY DG221AK/883
Updates to this data sheet may be obtained via facsimile by calling Siliconix FaxBack, 1-408-970-5600. Please request FaxBack document #70041.
Siliconix S-52881--Rev. C, 28-Apr-97
1
DG221
Absolute Maximum Ratings
Voltages Referenced to V- V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V Digital Inputsa, VS, VD . . . . . . . . . . . . . . . . . (V-) -2 V to (V+) +2 V or 20 mA, whichever occurs first Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30 mA Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Peak Current, S or D (Pulsed 1 ms, 10% duty cycle) . . . . . . . . . 70 mA Storage Temperature: (AK Suffix) . . . . . . . . . . . . -65 to 150_C (CJ and DY Suffix) . . . . . . -65 to 125_C Power Dissipation (Package)b 16-Pin CerDIPc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW 16-Pin Plastic DIPd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 mW 16-Pin SOICe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 mW Notes: a. Signals on SX, DX, or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. All leads welded or soldered to PC Board. c. Derate 12 mW/_C above 75_C d. Derate 6.5 mW/_C above 25_C e. Derate 7.7 mW/_C above 75_C
Schematic Diagram (Typical Channel)
V+
5V Reg GND INX - + V- V+ WR - + V- Latch Level Shift/ Drive V+
S
D V-
Figure 1.
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Siliconix S-52881--Rev. C, 28-Apr-97
DG221
Specificationsa
Test Conditions Unless Otherwise Specified Parameter Analog Switch
Analog Signal Rangee Drain-Source On-Resistance Source Off Leakage Current Drain Off Leakage Current Drain On Leakage Current VANALOG rDS(on) IS(off) VS = "14 V VD = #14 V V, ID(off) ID(on) VS = VD = "14 V IS = -10 mA, VD = "10 V Full Room Full Room Full Room Full Room Full 60 "0.01 "0.02 "0.01 -1 -100 -1 -100 -1 -200 -15 15 90 135 1 100 1 100 1 200 -5 -100 -5 -100 -5 -200 -15 15 90 135 5 100 5 100 5 200 nA V W
A Suffix
-55 to 125_C
D Suffix
-40 to 85_C
Symbol
V+ = 15 V, V- = -15 V VIN = 2.4 V, 0.8f V, WR = 0
Tempb
Typc
Mind Maxd Mind Maxd Unit
Digital Control
Input Current IINL , IINH VIN = 0 V or = 2.4 V Room Full -0.0004 -1 -10 1 10 -1 -10 1 10 mA
Dynamic Characteristics
Turn-On Time Turn-Off Time Turn-On Time Write Turn-Off Time Write Write Pulse Width Input Setup Time Input Hold Time Charge Injection Source-Off Capacitance Drain-Off Capacitance Channel-On Capacitance Off Isolation Interchannel Crosstalk tON tOFF tON, WR tOFF, WR tW tS tH Q CS(off) CD(off) CD(on) OIRR XTALK VS = 1 Vp p, f = 100 kHz p-p CL = 15 pF, RL = 1 kW f = 1 MHz, VS, VD = 0 V CL = 1000 pF VGEN = 0 V, RGEN = 0 W See Figure 4 See Figure 3 Room Room Room Full Room Room Room Room Room Room 120 130 0 20 8 9 29 70 90 dB pF 150 180 20 340 150 180 20 pC 340 ns Room See Figure 2 Room Room 340 550 340 550 550 550
Power Supplies
Positive Supply Current Negative Supply Current I+ I- All Channels On or Off VIN = 0 V or 2.4 V Full Room 0.8 -0.4 -1 1.5 -1 1.5 mA
Notes: a. Refer to PROCESS OPTION FLOWCHART. b. Room = 25_C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Guaranteed by design, not subject to production test. f. VIN = input voltage to perform proper function.
Siliconix S-52881--Rev. C, 28-Apr-97
3
DG221
Test Circuits
+15 V 3V 50% 0V VS 90% Switch Output -15 V CL (includes fixture and stray capacitance) VO = VS RL RL + rDS(on) VO tON tOFF tr < 10 ns tf < 10 ns V+ 2V S IN GND WR V- D VO RL 1 kW CL 35 pF
Logic Input Switch Input
Figure 2. Switching Time
+15 V 0V WR S IN GND V- V+ D 3V WR IN 0V 3V 0V VS VOUT -15 V CL (includes fixture and stray capacitance) VO = VS RL RL + rDS(on) VO tON, WR tOFF , WR 90% tr < 10 ns tf < 10 ns 50%
2V
VO RL 1 kW CL 35 pF
Figure 3. WR Switching Time
3V 50% IN tS 3V 50% WR tW tH = Hold Time tS = Setup Time tW = WR Pulse Width tH tS tH
VOUT
The latches are level sensitive. When WR is held low the latches are transparent and the switches respond to the digital inputs. The digital inputs are latched on the rising edge of WR.
Figure 4. WR Setup Conditions
4
Siliconix S-52881--Rev. C, 28-Apr-97
DG221
Test Circuits (Cont'd)
+15 V DVO Rg Vg 3V WR V- V+ S IN D VO CL 1000 pF INX OFF ON OFF VO
-15 V
DVO = measured voltage error due to charge injection The charge injection in coulombs is Q = CL x DVO
Figure 5. Charge Injection
+15 V C
C
+15 V
V+
V+
VS D VO Rg = 50 W 0V NC
S1 IN1 S2 IN2 GND WR V-
D1 50 W D2 RL C
VS Rg = 50 W 2.4 V
S
IN GND WR V- C
RL
VO
0V -15 V
Off Isolation = 20 log C = RF bypass
VS VO
-15 V VS VO
XTALK Isolation = 20 log C = RF bypass
Figure 6. Off Isolation
Figure 7. Channel-to-Channel Crosstalk
Application Hintsa
V+ Positive Supply Voltage (V)
15 20 10 10
V- Negative Supply Voltage (V)
-15 -20 -10 -5
GND (V)
0 0 0 0
WR (V)
2.4/0.8 2.4/0.8 2.4/0.8 2.4/0.8
VIN Logic Input Voltage VINH(min)/VINL(max) (V)
2.4/0.8 2.4/0.8 2.4/0.8 2.4/0.8
VS or VD Analog Voltage Range (V)
-15 to 15 -20 to 20 -10 to 10 -5 to 10
Notes: a. Application Hints are for DESIGN AID ONLY, not guaranteed and not subject to production testing.
Siliconix S-52881--Rev. C, 28-Apr-97
5
DG221
Applications
+15 V VIN
V+
9 MW S1
DG221
IN1 D C
Q D1 S2
900 kW
IN2
D C
Q D2
90 kW
Data Bus IN3
S3
D C
Q D3 S4
9 kW
IN4 WR
D C
Q D4
1 kW
WR GND CS Address Decoder V-
Address Bus
-15 V The TL081 is used as an output buffer while the voltage divider provides attenuation.
+ TL081 -
VO
Figure 8. mP-Controlled Analog Signal Attenuator
Truth Table WRa
0 0 0 0 0 0
Output Attenuation for Figure 8 On Switch
All None 1 2 3 4
IN1
0 1 0 1 1 1
IN2
0 1 1 0 1 1
IN3
0 1 1 1 0 1
IN4
0 1 1 1 1 0
WR
0 0 0 0
IN1
0 1 1 1
IN2
1 0 1 1
IN3
1 1 0 1
IN4
1 1 1 0
Gain
0.1 0.01 0.001 0.0001
Notes: a. WR may be held at "0" for temporary operation similar to DG201A/DG201B. With WR at "0" SW1 will remain on as long as IN1 is held at "0".
6
Siliconix S-52881--Rev. C, 28-Apr-97

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