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Data Sheet PD60232 revC
IR22381QPBF/IR21381Q(PbF)
3-PHASE AC MOTOR CONTROLLER IC
Features
* * * * * * * * * * * * Floating channel up to +600V or +1200V "soft" over-current shutdown turns off desaturated output Integrated desaturation circuit Active biasing on sensing desaturation input Two stage turn on output for di/dt control Integrated brake IGBT driver with protection Voltage feedback sensing function Separate pull-up/pull-down output drive pins Matched delay outputs Under voltage lockout with hysteresis band Programmable deadtime Hard shutdown function
Product Summary
VOFFSET (max) IO +/- (min.) VOUT
Brake (IO +/- min.) Deadtime Asymmetry Skew (max.) Deadtime (typ. with RDT=39K) DESAT Blanking time (typ.) DESAT filter time (typ.) Active bias on Desat input pin DSH, DSL input voltage threshold (typ.) Soft shutdown duration time (typ.) Voltage feedback matching delay time (max.) 600V or 1200V 220mA / 460mA 12.5V-20V 40mA/80mA 125nsec 1sec 4.5sec 3.0sec 90 8.0V 6.0sec 400nsec
Description
The IR22381Q and IR21381Q are high voltage, 3-phase IGBT driver best suited for AC motor drive applications. Integrated desaturation logic provides all mode of overcurrent protection, including ground fault protection. The sensing desaturation input is provided by active bias stage to reject noise. Soft shutdown is predominantly initiated in the event of overcurrent followed by turnoff of all six outputs. A shutdown input is provided for a customized shutdown function. The DT pin allows external resistor to program the deadtime. Output drivers have separate turn on/off pins with two stage turn-on output to achieve the desired di/dt switching level of IGBT. Voltage feedback provides accurate volt x second measurement.
Package
64-Lead MQFP w/o 13 leads
Typical Connection
15V
3
VCC
3
To controller
IR22381QPBF
DC bus
VFH1,2,3 VFL1,2,3 DSB
VS1,2,3 DSL1,2,3 LOP1,2,3 LOQ1,2,3 LON1,2,3 COM
U V W
(Refer to Lead Assignments for correct pin configuration. This diagram shows electrical connections only)
BR DT VSS
1
To motor
LIN1,2,3 HIN1,2,3 FAULT BRIN SD
VB1,2,3 DSH1,2,3 HOP1,2,3 HOQ1,2,3 HON1,2,3
IR22381QPBF/IR21381Q(PbF)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to VSS, all currents are defined positive into any lead. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions.
Symbol VS VB VHO VCC COM VLO VIN VFLT VF VDSH VDSL VBR dVs/dt PD RthJA TJ TS TL
Definition High side offset voltage
Min.
Max.
Units
VB 1,2,3 - 25 VB 1,2,3 + 0.3 (IR22381) -0.3 1225 High side floating supply voltage (IR21381) -0.3 625 High side floating output voltage (HOP, HON, HOQ) VS1,2,3 - 0.3 VB 1,2,3 + 0.3 Low side and logic fixed supply voltage -0.3 25 Power ground VCC - 25 VCC + 0.3 Low side output voltage (LOP, LON, LOQ) VCOM -0.3 VCC + 0.3 V Logic input voltage (HIN/N, LIN, BRIN/N, SD) -0.3 VCC + 0.3 or VSS +15 Which ever is lower FAULT/N output voltage -0.3 VCC + 0.3 Feedback output voltage -0.3 VCC + 0.3 High side desat/feedback input voltage VB 1,2,3 - 25 VB 1,2,3 + 0.3 Low side desat/feedback input voltage VCC - 25 VCC + 0.3 Brake output voltage VCOM -0.3 VCC + 0.3 Allowable offset voltage slew rate -- 50 V/ns Package power dissipation @ TA +25C -- 2.0 W Thermal resistance, junction to ambient -- 60 C/W Junction temperature -- 125 Storage temperature C -55 150 Lead temperature (soldering, 10 seconds) -- 300
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute voltages referenced to VSS. The VS offset rating is tested with all supplies biased at 15V differential.
Symbol VB 1,2,3 VS1,2,3 VHO 1,2,3 VLO1,2,3 VIN VCC COM VFLT VF VDSH VDSL VBR TA
Definition High side floating supply voltage (Note 1) High side floating supply offset voltage High side (HOP/HOQ/HON) output voltage Low side (LOP/LOQ/LON) output voltage Logic input voltage (HIN/N, LIN, BRIN/N SD) Low side supply voltage (Note 1) Power ground FAULT/N output voltage Feedback output voltage High side desat/feedback input voltage Low side desat/feedback input voltage BR output voltage Ambient temperature
Min. VS1,2,3+12.5 (IR21381) Note 2 (IR22381) Note 2 VS1,2,3 VCOM 0 12.5 -5 0 0 VB 1,2,3 - 20 VCC - 20 VCOM -40
Max. VS1,2,3 + 20 600 1200 VS1,2,3 + VB VCC VSS + 5 20 +5 VCC VCC VB 1,2,3 VCC VCC 115
Units
V
C
Note 1: While internal circuitry is operational below the indicated supply voltages, the UV lockout disables the output drivers if the UV thresholds are not reached. Note 2: Logic operational for VS from VSS-5V to VSS+600V (IR21381) or 1200V (IR22381). Logic state held for VS from VSS-5V to VSSVBS. (Please refer to the Design Tip DT97-3 for more details).
2
IR22381QPBF/IR21381Q(PbF)
Static Electrical Characteristics
VBIAS (VCC, VBS1,2,3 ) = 15V and TA = 25 C unless otherwise specified. I/O diagrams don't show ESD protection circuits.
Pin: VCC, VSS, VB, VS
Symbol
VCCUV+ VCCUVVCCUVH VBSUV+ VBSUVVBSUVH ILK IQBS IQCC
Definition
Vcc1 supply undervoltage positive going threshold Vcc1 supply undervoltage negative going threshold Vcc1 supply undervoltage lockout hysteresis VBS supply undervoltage positive going threshold VBS supply undervoltage negative going threshold VBS supply undervoltage lockout hysteresis (IR21381Q) Offset supply leakage current (IR22381Q) Quiescent VBS supply current Quiescent Vcc supply current
Min Typ Max Units
10.3 9.5 10.3 9.5 11.2 10.2 1.0 11.2 10.2 1.0 150 3 12.5 11.3 11.9 10.9 50 50 300 6
Test Conditions
V
VB1,2,3 =VS1,2,3 = 600V VB1,2,3 =VS1,2,3 = A 1200V VLIN=0V,VHIN=5V, DSH1,2,3= VS1,2,3 mA VLIN=0V,VHIN=5V DT=1sec
Comparator
VCC/VB
UV
VCCUV/VBSUV
VSS/VS
Figure 1: Undervoltage diagram
Pin: HIN/N, LIN, BRIN/N, SD
The VIN, VTH and IIN parameters are referenced to VSS and are applicable to all six channels (HOP/HOQ/ HON1,2,3 and LOP/LOQ/LON1,2,3).
Symbol
VIH VIL Vt+ VtVT IIN+ IIN-
Definition
Logic "0" input voltage (HIN/N, LIN, BRIN/N, SD)(OUT=LO) Logic "1" input voltage (HIN/N, LIN, BRIN/N, SD)(OUT=HI) Logic input positive going threshold (HIN/N, LIN, BRIN/N, SD) Logic input negative going threshold (HIN/N, LIN, BRIN/N, SD) Logic input hysteresis(HIN/N, LIN, BRIN/N, SD) Logic "1" input bias current (HIN/N, BRIN/N) Logic "1" input bias current (LIN, SD) Logic "0" input bias current (HIN/N, BRIN/N) Logic "0" input bias current (LIN, SD)
Min Typ Max Units
2.0 1.2 0.8 -2 -2 1.6 1.2 0.4 85 85 0.8 2.0 1.6 0 140 140 0 A V
Test Conditions
VCC = 12.5V to 20V
VIN = 0V VIN = 5V VIN = 5V VIN = 0V
3
IR22381QPBF/IR21381Q(PbF)
Figure 2: HIN/N, LIN and BRIN/N diagram
Pin: FAULT/N, VFH, VFL
VOLVF is referenced to Vss Symbol Definition VOLVF VFH or VFL low level output voltage RON,VF RON,FLT VFH or VFL output on resistance FAULT/N low on resistance Min Typ Max Units Test Conditions 0.8 V IVF = 10mA 60 60
______ FAULT / VFL/VFH
RON Internal signal
VSS
Figure 3: FAULT/N, VFH, VFL diagram
Pin: DSL, DSH, DSB
VDESAT and IDESAT parameters are referenced to COM and VS1,2,3 Symbol Definition VDESAT+ High DSH1,2,3 and DSL1,2,3 and DSB input threshold voltage VDESATLow DSH1,2,3 and DSL1,2,3 or DSB input threshold voltage DS input voltage hysteresis VDSTH High DSH, DSL, DSB input bias current IDS+ Low DSH, DSL input bias current IDSLow DSB input bias current IDSBRIDSB DSH or DSL input bias current Min Typ Max Units Test Conditions 8.0 7.0 1.0 15 -150 -250 -11.1 V
A mA
VDESAT = 15V VDESAT = 0V VDESAT = 0V VDESAT = (VCC or VBS) - 1V
Figure 4: DSH, DSL and DSB diagram
4
IR22381QPBF/IR21381Q(PbF)
Pin: HOP, LOP, HOQ, LOQ
The VO and IO parameters are referenced to COM and VS1,2,3 and are applicable to the respective output leads: HO1,2,3 and LO1,2,3. Symbol Definition Min Typ Max Units Test Conditions VOH High level output voltage, VBIAS - VO (normal 2 V IO = -20mA switching). HOP=HOQ, LOP=LOQ. IO1+ Output high first stage short circuit pulsed current. HOP=HOQ, LOP=LOQ 200 350 mA V O=0V, VIN=1 (Note 1) PWton1 Figure 16 VO=0V, VIN=1 (Note 1) PW10s
IO2+
Output high second stage short circuit pulsed current. 100 HOP=HOQ, LOP=LOQ
HINx/N = 0V, for LOx LIN = 5V
200
-
Note 1: for HOx
Figure 5: HOP/HOQ and LOP/LOQ diagram
Pin: HON, LON, SSDH, SSDL
The VO and IO parameters are referenced to COM and VS1,2,3 and are applicable to the respective output leads: HO1,2,3 and LO1,2,3 . Symbol VOL RON,SS IODefinition Low level output voltage, VO (normal switching) HON, LON Soft shutdown on resistance (see Note 2) Output low short circuit pulsed current Min Typ Max Units Test Conditions 2 V IO = 20mA 500 250 540 mA PW tSS VO=15V, VIN=0 (Note 3) PW10s
Note 2: SSD operation only Note 3: for HOx HINx/N = 5V, for LOx
LIN = 0V
Figure 6: HON, LON diagram
5
IR22381QPBF/IR21381Q(PbF)
Pin: BR
The VO and IO parameters are referenced to COM and are applicable to BR output . Symbol Definition Min Typ Max Units VOHB BR high level output voltage, VCC- VBR 6 V VOLB BR low level output voltage, VBR 3 IOBR+ IOBRBR output high short circuit pulsed current BR output low short circuit pulsed current 40 80 70 125 mA Test Conditions IBR = -20mA IBR = 20mA VBR=15V, VBRIN/N=0V PW10s VBR=0V, VBRIN/N=5V PW10s
AC Electrical Characteristics
VBIAS (VCC, VBS ) = 15V, VS1,2,3 =VSS, TA = 25 C and CL= 1000pF unless otherwise specified. Symbol Definition Min. Typ. Max. Units -- 200 -- 750 750 -- -- -- -- -- -- -- ns DSB to LO hard shutdown propagation delay DSB to BR hard shutdown propagation delay VFH high to low propagation delay VFH low to high propagation delay VFL low to high propagation delay VFL high to low propagation delay Minimum pulse width of VFH and VFL -- 3300 -- 3000 -- -- -- -- -- 550 550 550 550 400 -- -- -- -- -- -- -- Test Conditions VIN = 0 & 5V RL(HOQ/LOQ)=10 VIN = 0 & 5V VS1,2,3 = 0 to 600 or 1200V HOP=HON,LOP=LON Figure 7 VHIN = 0V, VDESAT = 15V, Figure 11 VLIN = 5V VDESAT = 15V, Figure 11 VHIN = 0V, VDESAT = 15V, Figure 11 VLIN = 5V VDESAT = 15V, Figure 11 VBRIN = 0V VDSB = 15V, Figure 11 VDESAT = 15V to 0V Figure 12 VDESAT = 0V to 15V Figure 12 VDESAT = 0V to 15V Figure 12 VDESAT = 15V to 0V Figure 12 VDESAT = 15V to 0V or 0V to 15V Figure 12 Propagation Delay Characteristics ton1 Turn-on first stage duration time ton toff tr tf tDESAT1 tDESAT2 tDESAT3 tDESAT4 tDESAT5 tDESAT6 tDESAT7 tVFHL1,2,3 tVFHHL1,2,3 tVFLH1,2,3 tVFLL1,2,3 tPWVF Turn-on propagation delay Turn-off propagation delay Turn-on rise time Turn-off fall time DSH to HO soft shutdown propagation delay at HO turn-on DSH to HO soft shutdown propagation delay after blanking DSL to LO soft shutdown propagation delay at LO turn-on DSL to LO soft shutdown propagation delay after blanking DSB to HO hard shutdown propagation delay
250 550 250 550 -- 80 -- 25 -- 4500 -- 3000 -- 4500 -- 3000 -- 3300
6
IR22381QPBF/IR21381Q(PbF)
AC Electrical Characteristics cont.
VBIAS (VCC, VBS ) = 15V, VS1,2,3 =VSS, TA = 25 C and CL= 1000pF unless otherwise specified. Symbol Definition Min. Typ. Max. Units -- 3000 -- 6000 -- 4800 -- 3300 -- 4500 -- 3000 -- 3000 -- -- -- -- -- -- -- ns Test Conditions CL=1000pF, VDS=15V Figure 8-9 VHIN = 0V, VDS=15V, Figure 11 VLIN = 5V, VDS=15V, Figure 11 Propagation Delay Characteristics cont. tDS Soft shutdown minimum pulse width of desat tSS tFLT,DESAT1 tFLT,DESAT2 tFLT,DESAT3 tFLT,DESAT4 tFLTDSB tFLTCLR tfault tBL tSD tEN tonBR toffBR trBR tfBR DT Soft shutdown duration period DSH to FAULT propagation delay at HO turn-on DSH to FAULT propagation delay after blanking DSL to FAULT propagation delay at LO turn-on DSL to FAULT propagation delay after blanking DSB to FAULT propagation delay LIN1=LIN2=LIN3=0 to FAULT Minimum FAULT duration period DS blanking time at turn on SD to output shutdown propagation delay SD disable propagation delay BR output turn-on propagation BR output turn-off propagation BR output turn-on rise time BR output turn-off fall time Deadtime 9.0 -- -- 9.0 15.0 21.0 -- 4500 -- -- -- -- -- -- 600 600 110 125 235 130 -- 900 900 200 200 400 250 ns s
VBRIN/N = 0V VDESAT = 15V, Figure 11 VDESAT=15V, Figure 11 VDESAT=15V, Figure 15 FLTCLR pending VIN = on VDESAT=15V, Figure 11 VIN = on VDESAT=0V, Figure 14 VIN = on VDESAT=0V, Figure 14 Figure 7
Dead-time/Delay Matching Characteristics 800 1000 1200 76 100 124 Figure 12, External resistor=39k Figure 12,External resistor=0k Figure 12, External resistor=220k DT=1000ns Figure 12 DT=1000ns Figure 12 Input pulse width >400nsec, Figure 13
4500 5000 5500 MDT PM Deadtime asymmetry skew, any of DTLoff1,2,3-DTHoff1,2,3 PWM propagation delay matching max {ton/toff} -min {ton/toff}, (ton/toff are applicable to all six channels) Voltage feedback delay matching, I any of tVFHL1,2,3 , tVFHHL1,2,3 , tVFLL1,2,3 , tVFLH1,2,3 - any of tVFHL1,2,3 , tVFHHL1,2,3 , tVFLL1,2,3 , tVFLH1,2,3 -- -- -- -- 125 125
ns
VM
--
--
400
7
IR22381QPBF/IR21381Q(PbF)
Figure 7: Switching Time Waveforms
Figure 8: Low Side Desat Soft Shutdown Timing Waveform
8
IR22381QPBF/IR21381Q(PbF)
Figure 9: High Side Desat Soft Shutdown Timing Waveform
Figure 10: Brake Desat Timing Waveform
9
IR22381QPBF/IR21381Q(PbF)
Figure 11: Desat Timing Diagram
10
IR22381QPBF/IR21381Q(PbF)
HIN LIN HO (HOP=HOQ=HON)
DTLoff DTHoff
90% 50% 10% 50%
DT
DT
90%
50%
10%
50%
LO (LOP=LOQ=LON)
Figure 12: Internal Dead-Time Timing
VB1,2,3
DSH1,2,3
VS1,2,3
VDESAT-
VDESAT+
VB1,2,3
DSL1,2,3
VS1,2,3
VDESAT+
tVFHL1,2,3
VDESAT-
tVFHH1,2,3
VCC
90%
VFH1,2,3
10%
VSS
tVFLH1,2,3
VCC
tVFLL1,2,3
90%
VFL1,2,3
VSS
10%
Figure 13: Voltage Feedback Timing
11
IR22381QPBF/IR21381Q(PbF)
Figure 14: Shutdown Timing
Figure 15: Fault Duration with Pending Faultclear Waveform (See paragraph 1.4.5 on page 21)
Figure 16: Output source current
12
IR22381QPBF/IR21381Q(PbF)
Lead Assignments
Figure 17: Package pin out
Lead Definitions
Symbol VCC VSS HIN1,2,3 /N LIN1,2,3 FAULT/N SD DT DSB BRIN/N Description Low side supply voltage Logic Ground Logic inputs for high side gate driver outputs (HOP1,2,3/HOQ1,2,3/HON1,2,3) Logic input for low side gate driver outputs (LOP1,2,3/LOQ1,2,3/LON1,2,3) Fault output (latched and open drain) Shutdown input Programmable deadtime resistor pin Brake IGBT desaturation protection input Logic input for brake driver
13
IR22381QPBF/IR21381Q(PbF)
Lead Definitions continued
Symbol BR COM VB1,2,3 HOP1,2,3 HOQ1,2,3 HON1,2,3 DSH1,2,3 VS1,2,3 LOP1,2,3 LOQ1,2,3 LON1,2,3 DSL1,2,3 VFH1,2,3 VFL1,2,3 Description Brake driver output Brake and Low side drivers return High side gate driver floating supply High side driver sourcing output High side driver boost sourcing output High side driver sinking output IGBT desaturation protection input and high side voltage feedback input (see par. 1.4.3 on page 19) High voltage floating supply return Low side driver sourcing output Low side driver boost sourcing output Low side driver sinking output IGBT desaturation protection input and low side voltage feedback input (see par. 1.4.3 on page 19) High side voltage feedback logic output Low side voltage feedback logic output
14
IR22381QPBF/IR21381Q(PbF)
Functional block diagram
VB1
LAT CH
HIN1
HOQ1
LIN1
SCHMITT T RIGGER INPUT & SHOOT THROUGH PREVENTION
HIN1
100nsec minimum Deadtime
LEVEL SHIFTERS
SHUTDOWN
VFB
LOCAL DESAT PROTECTION SOFT SHUTDOWN VOLTAGE FEEDBACK UV DETECT
HIN1
di/dt control
HOP1 HON1 VS1
DSH1
DRIVER
VFH1
VB2
LAT CH LOCAL DESAT PROTECTION SOFT SHUTDOWN VOLTAGE FEEDBACK UV DETECT
VFH2
HOQ2
HIN2
HIN2
LIN2
SCHMITT T RIGGER INPUT & SHOOT THROUGH PREVENTION
100nsec minimum Deadtime
HIN2
di/dt control
HOP2 HON2 VS2
DSH2
LEVEL SHIFTERS
SHUTDOWN
DRIVER
VFB
VB3
HOQ3
HIN3
HIN3
LAT CH LOCAL DESAT PROTECTION SOFT SHUTDOWN VOLTAGE FEEDBACK UV DETECT
LIN3
SCHMITT T RIGGER INPUT & SHOOT THROUGH PREVENTION
100nsec minimum Deadtime
HIN3
di/dt control
HOP3 HON3 VS3
DSH3
LEVEL SHIFTERS
SHUTDOWN
DRIVER
VFB
VFH3
SD
SOFT SHUTDOWN
LOCAL DESAT PROTECTION SOFT SHUTDOWN VOLTAGE FEEDBACK
LOQ1
LIN1
DT
di/dt control
LOP1 LON1
DRIVER
VFL1 VFL2 VFL3
DSL1
LOCAL DESAT PROTECTION
LOP2
LIN2
CLEAR LOGIC
FAULT LOGIC
SOFT SHUTDOWN VOLTAGE FEEDBACK
di/dt control
LOP2 LON2
DRIVER
DSL2
FAULT
VCC
LOCAL DESAT PROTECTION SOFT SHUTDOWN
LOQ3
LIN3
di/dt control
LOP3 LON3
To Low Side Logic
UV DETECT
DRIVER
VOLTAGE FEEDBACK
DSL3
BRIN
VSS
SHUTDOWN
DESAT DETECTION
BRAKE DRIVER
BR
DSB
COM
15
IR22381QPBF/IR21381Q(PbF)
State diagram
Stable States
- - - - - FAULT Normal operation UNDERVOLTAGE VCC SHUTDOWN (SD) UNDERVOLTAGE VBS
Temporary States
- SOFT SHUTDOWN
System Variables
-
FAULT CLEAR indicates: LIN1=LIN2=LIN3=0 - HIN/N /LIN/BRIN/N - UV_VCC - UV_VBS - DSH/L, DSB - SD NOTE 1: a change of logic value of the signal labeled on lines (system variable) generates a state transition. NOTE 2: Exiting from UNDERVOLTAGE VBS state, the HO goes high only if a falling edge event happens in HIN/N.
16
IR22381QPBF/IR21381Q(PbF)
Logic Table
Output drivers status description HO/LO/BR status
0 1 SSD LO/HO/BR
HOP/LOP
HiZ 1 HiZ
HOQ/LOQ
HiZ 1 (after ton1) HiZ
HON/LON
0 HiZ SSD pulldown
BR 0 1 N/A
Output follows inputs
INPUTS
Operation
Normal Operation Anti Shoot Through Shut Down Under Voltage Soft SD (after DSL/H) Hard SD (after DSB) FAULT Fault Clear
OUTPUT
SD 0 0 0 0 1 0 0 X X X X FAULT/N 1 1 1 1 1 1 1 1 0 0 (after tFLTCLR)
Under Voltage
VCC No No No No X No Yes No No No No VBS No No No No X Yes X No No No No 0
Driver OUTPUTS
HO 1 0 0 0 0 0 0 SSD 0 0 HO LO 0 1 0 0 0 LO 0 SSD 0 0 0 BR BR BR BR BR BR BR 0 BR 0 0 BR
HIN/N 0 1 1 0 X X
(NOTE1)
LIN 0 1 0 1 X LIN X X X X
(NOTE2)
BRIN/N BRIN/N BRIN/N BRIN/N BRIN/N BRIN/N BRIN/N X BRIN/N X X BRIN/N
X X X X
X HIN/N
LIN1= LIN2= LIN3= 0
NOTE1: Unless in Anti Shoot Through condition. NOTE2: FAULT duration is at least tfault when LIN1=LIN2=LIN3=0. Device stays in FAULT condition in all other cases.
17
IR22381QPBF/IR21381Q(PbF)
Timing and logic state diagrams description
The following picture (Figure 18) shows the input/output logic diagram.
Figure 18: I/O timing diagram Referred to timing diagram of Figure 18: A. When the input signals are on together the outputs go off (anti-shoot through). B. The HO signal is on and the high side IGBT desaturates, the HO turn off softly. FAULT goes low. While in SSD, if LIN goes up, LO does not change (freeze). C. When FAULT is latched low (see FAULT section) it can be disabled by LIN1=LIN2=LIN3=0 condition. D. SD disable HO and LO outputs. E. The LO signal is on and the low side IGBT desaturates, the low side behaviour is the same as described in point B. F. As C. G. As D. H. As A. I. The BR signal is on and the brake IGBT desaturates. The driver goes in FAULT condition tuning off all the IGBTs (Hard shut down).
18
IR22381QPBF/IR21381Q(PbF) 1 FEATURES DESCRIPTION
forcing FAULT pin low (see FAULT section and Figure 20). This event disables both low side and floating drivers and the diagnostic signal holds until the under voltage condition is over. Fault condition is not latched and the FAULT pin is released once VCC becomes higher than UVVCC+. The undervoltage on the VBS works disabling only the floating driver. Undervoltage on VBS does not prevent the low side driver to activate its output nor generate diagnostic signals. VBS undervoltage condition (VBS < UVVBS-) latches the high side output stage in the low state. VBS must be reestablished higher than UVVBS+ to return in normal operating mode. To turn on the floating driver HIN must be re-asserted high (rising edge event on HIN is required). 1.4.2 4.2 Power devices desaturation Different causes can generate a power inverter failure: phase and/or rail supply short-circuit, overload conditions induced by the load, etc... In all these fault conditions a large current increase is produced in the IGBT. The IR22381/IR21381 fault detection circuit monitors the IGBT emitter to collector voltage (VCE) by means of an external high voltage diode. High current in the IGBT may cause the transistor to desaturate, i.e. VCE to increase. Once in desaturation, the current in power transistor can be as high as 10 times the nominal current. Whenever the transistor is switched off, this high current generates relevant voltage transients in the power stage that need to be smoothed out in order to avoid destruction (by over-voltages). The IR22381/IR21381 gate driver accomplish the transients control by smoothly turning off the desaturated transistor by means of the LON pin activating a so called Soft ShutDown sequence (SSD). 1.4.3 Desaturation detection: DSH/L and DSB pin function Figure 19 shows the structure of the desaturation sensing and soft shutdown block. This configuration is the same for both high and low side output stages.
1.1
Start-up sequence
Device starts in FAULT condition at power-up unless FAULT clear condition is forced (i.e. LIN1=LIN2=LIN3=0 for at least tFLTCLR - in this case FAULT is asserted for tfltclr, then resets). In FAULT condition driver outputs are insensitive to inputs: any noise on input pins is then rejected during system power-up. As soon as the controller awakes, a FAULT clear action can be taken to enter the normal operating condition.
1.2
Normal operation mode
After clearing FAULT condition and supplies are stable the device becomes fully operative (see grey blocks in the State Diagram). HIN/N1,2,3, LIN1,2,3 and BRIN/N produce driver outputs to switch accordingly, while the input logic checks the input signals preventing shoot-through events and including Dead-time (DT).
1.3
Shut down
The system controller can asynchronously command the Shutdown through the 3.3 V compatible CMOS I/O SD pin. This event is not latched.
1.4
Fault management
IR22381 is able to manage both the supply failure (undervoltage lockout on both low and high side circuits) and the desaturation of power transistors connected to its drivers outputs. 1.4.1 Undervoltage (UV) The Undervoltage protection function disables the output stage of each driver preventing the power device being driven with too low voltages. Both the low side (VCC supplied) and the floating side (VBS supplied) are controlled by a dedicate undervoltage function. Undervoltage event on the VCC (when VCC < UVVCC-) generates a diagnostic signal by
19
IR22381QPBF/IR21381Q(PbF)
Figure 19: high and low side output stage for channels 1, 2, 3
VB1 ____ HIN1
UV detect HIN1 Schmitt trigger input & shoot through prevention 100ns minimum deadtime Input latch Level Shifters Shutdown HIN1 Latch Local DESAT protection Soft ShutDown VFH1 HOLD Voltage feedback di/dt control DRIVER
HOQ1 HOP1 HON1 VS1 DSH1
LIN1
Shutdown
HOLD latch oneshot
LIN2 LIN3 _____ FAULT
Clear logic
Desat H1
LIN1
R
Fault duration (tfault) UV_VCC Desat H2 Desat H3 Desat L2 Desat L3 LIN1 Desat L1 Local DESAT protection Soft ShutDown Voltage feedback di/dt control DRIVER
Q VSS
S
LOQ1 LOP1 LON1
Soft Shutdown
UV detect VCC
FAULT logic
VFL1
DSL1
Hard Shutdown DESAT protection Shutdown
di/dt control DRIVER
BR
____ BRIN
COM DSB
Figure 20: Fault management diagram
20
IR22381QPBF/IR21381Q(PbF)
The external sensing diode should have BV>600V (or 1200V depending on application) and low stray capacitance (in order to minimize noise coupling and switching delays). The diode is biased by a dedicated circuit for IGBT driver outputs (see the active-bias section) and by a pull-up resistor for Brake output. When VCE increases, the voltage at DSH/L pin increases too. Being internally biased to the local supply, DSH/L or DSB voltage is automatically clamped. When DSH/L or DSB exceed the VDESAT+ threshold the comparator triggers (see Figure 19). Comparator output is filtered in order to avoid false desaturation detection by externally induced noise; pulses shorter than tDS are filtered out. To avoid detecting a false desaturation during IGBT turn on, the desaturation circuit is disabled by a Blanking signal (TBL, see Blanking block in Figure 19). Blanking time is the estimated maximum IGBT turn on time and must be not exceeded by proper gate resistance sizing. When the IGBT is not completely saturated after TBL, desaturation is detected and the driver will turn off. 1.4.4 SSD and Fault management Output bridge Desaturation event implies a large amount of current. For that reason, IR22381 turn off strategy is based on soft shutdown. Eligible desaturation signals coming from DSH/L inputs initiate the Soft Shutdown sequence (SSD). While in SSD, the SSD pull-down is activated (RON,SS for tss - see Figure 19) to turn off the IGBT through HON/LON. Figure 20 shows the fault management circuit. In this diagram Desat_H1,2,3 and Desat_L1,2,3 are the internal signals triggered by the desaturation event. IR22381 accomplishes output bridge turn off in the following way: - if the desaturated IGBT is a low side, all the low side IGBTs are softly turned off (SSD), while the high side IGBTs are kept in the state they were just before the desaturation event. - If the desaturated IGBT is a high side, it is soflty turned off simultaneously with all the low side IGBTs. While the remaining HS IGBTs are kept in the state they were just before the desaturation event. In any case, after the soft shutdown period (tSS), all IGBTs are hardly shut down (brake IGBT included). Desaturation event generates a FAULT signal (see Figure 11) that is latched until fault clear condition is verified. It must be noted that while in Soft Shut Down, both Under Voltage fault and external Shut Down (SD) are masked until the end of SSD. Desaturation protection is working independently by the other control pins and it is disabled only when the output status is off. Brake IGBT Brake desaturation causes a hard shutdown for all the IGBTs. Fault condition is asserted and hold until cleared by controller. 1.4.5 Fault Clear Fault is cleared by forcing low simultaneously LIN1, LIN2 and LIN3 for at least tFLTCLR. When LIN inputs are simultaneously low and a desaturation event happens, FAULT is activated for a minimum amount of time of tfault.
1.5
Active bias
For the purpose of sensing the power transistor desaturation the collector voltage is read by an external HV diode. The diode is normally biased by an internal pull up resistor connected to the local supply line (VB or VCC). When the transistor is "on" the diode is conducting and the amount of current flowing in the circuit is determined by the internal pull up resistor value. In the high side circuit, the desaturation biasing current may become relevant for dimensioning the bootstrap capacitor (see Figure 23). In fact, too low pull up resistor value may result in high current discharging significantly the bootstrap capacitor. For that reason typical pull up resistor are in the range of 100 k. This is the value of the internal pull up. While the impedance of DSH/DSL pins is very low when the transistor is on (low impedance path through the external diode down to the power transistor), the impedance is only controlled by the pull up resistor when the transistor is off. In that case relevant dV/dt applied by the power transistor during the commutation at the output results in a considerable current injected through the stray capacitance of the diode into the desaturation detection pin (DSH/L). This coupled noise may be easily reduced using an active bias for the sensing diode. An Active Bias structure is available DSH/L pin. The DSH/L pins present an active pull-up respectively to VB/VCC, and a pull-down respectively to VS/COM. The dedicated biasing circuit reduces the impedance on the DSH/L pin when the voltage exceeds the VDESAT threshold (see Figure 21). This low impedance helps in rejecting the noise providing the current inject by the parasitic capacitance. When the
21
IR22381QPBF/IR21381Q(PbF)
power transistor is fully on, the sensing diode gets forward biased and the voltage at the DSH/L pin decreases. At this point the biasing circuit deactivates, in order to reduce the bias current of the diode as shown in Figure 21. and one turn off stage for SSD operation (both connected to HON/LON). When the driver turns on the IGBT (see Figure 16), a first stage is constantly activated (HOP/LOP) while an additional stage is maintained active only for a limited time (tON1, HOQ/LOQ). This feature boost the total driving capability in order to accommodate both fast gate charge to the plateau voltage and dV/dt control in switching. At turn off, a single n-channel sinks up to 460mA (IO-) and offers a low impedance path to prevent the selfturn on due to the parasitic Miller capacitance in the power switch.
1.7
Figure 21: RDSH/L Active Biasing
Voltage FeedBack
1.6
Output stage
The structure is shown in Figure 19 and consists of two turn on stages (connected to HOP/LOP and HOQ/LOQ), one turn off stage for normal operation
Voltage feedback pins provide information about the state of the corresponding IGBT by means of sensing its collector. The VDESAT threshold discriminates whether the sensed IGBT can be considered on (DSH/L < VDESAT) or off (DSH/L > VDESAT). IGBT state information is then sent to VFH/L1,2,3 open collector outputs, which are tied to Vss ground. See Figure 22 for functional details.
Figure 22: Voltage feedback functional diagram
22
IR22381QPBF/IR21381Q(PbF)
2
Sizing tips
Bootstrap supply
Now we must consider the influencing factors contributing VBS to decrease: - - - - - - - IGBT turn on required Gate charge (QG); IGBT gate-source leakage current (ILK_GE); Floating section quiescent current (IQBS); Floating section leakage current (ILK) Bootstrap diode leakage current (ILK_DIODE); Desat diode bias when on (IDS- ) Charge required by the internal level shifters (QLS); typical 20nC - Bootstrap capacitor leakage current (ILK_CAP); - High side on time (THON).
2.1
The VBS1,2,3 voltage provides the supply to the high side drivers circuitry of the IR22381/IR21381. VBS supply sit on top of the VS voltage and so it must be floating. The bootstrap method to generate VBS supply can be used with IR22381/IR21381 high side drivers. The bootstrap supply is formed by a diode and a capacitor connected as in Figure 23.
ILK_CAP is only relevant when using an electrolytic capacitor and can be ignored if other types of capacitors are used. It is strongly recommend using at least one low ESR ceramic capacitor (paralleling electrolytic and low ESR ceramic may result in an efficient solution).
IR22381Q or IR21381Q
Then we have:
QTOT = QG + Q LS + ( I LK _ GE + I QBS +
+ I LK + I LK _ DIODE + I LK _ CAP + I DS - ) THON
Figure 23: bootstrap supply schematic This method has the advantage of being simple and low cost but may force some limitations on dutycycle and on-time since they are limited by the requirement to refresh the charge in the bootstrap capacitor. Proper capacitor choice can reduce drastically these limitations. The minimum size of bootstrap capacitor is:
C BOOT min =
An example follows:
QTOT V BS
using a 15A @ 100C IGBT (GB15XP120K):
* * * * * * * * * IQBS = 250 A ILK = 50 A QLS = 20 nC; QG = 58 nC ILK_GE = 250 nA ILK_DIODE = 100 A ILK_CAP = 0 IDS- = 150 A THON = 100 s. (See Static Electrical Charact.); (See Static Electrical Charact.); (Qge+Qgc Datasheet GB15XP120K); (Datasheet GB15XP120K); (with reverse recovery time <100 ns); (neglected for ceramic capacitor); (see Static Electrical Charact.);
Bootstrap capacitor sizing
To size the bootstrap capacitor, the first step is to establish the minimum voltage drop (VBS) that we have to guarantee when the high side IGBT is on. If VGEmin is the minimum gate emitter voltage we want to maintain, the voltage drop must be:
VBS VCC - VF - VGE min - VCEon
under the condition:
And:
* * * * VCC = 18 V VF = 1 V VCEonmax = 2.5 V VGEmin = 11.9 V
VGE min > VBSUV -
where VCC is the IC voltage supply, VF is bootstrap diode forward voltage, VCEon is emitter-collector voltage of low side IGBT and VBSUV- is the high-side supply undervoltage negative going threshold.
the maximum voltage drop VBS becomes
VBS VCC - VF - VGEmin - VCEon =
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IR22381QPBF/IR21381Q(PbF)
= 18V - 1V - 11.9V - 2.5V = 2.6V
And the bootstrap capacitor must be: constant. The minimum on time for charging the bootstrap capacitor or for refreshing its charge must be verified against this time-constant. c. Bootstrap Capacitor For high THON designs where is used an electrolytic tank capacitor, its ESR must be considered. This parasitic resistance forms a voltage divider with Rboot generating a voltage step on VBS at the first charge of bootstrap capacitor. The voltage step and the related speed (dVBS/dt) should be limited. As a general rule, ESR should meet the following constraint:
C BOOT
133 nC = 51 nF 2.6 V
NOTICE: Here above VCC has been chosen to be 18V as an example. IGBTs can be supplied with higher/lower supply accordingly to design requirements. Vcc variations due to low voltage power supply must be accounted in the above formulas.
Some important considerations
a. Voltage ripple There are three different cases making the bootstrap circuit get conductive (see Figure 23) ILOAD < 0; the load current flows in the low side IGBT displaying relevant VCEon
ESR VCC 3V ESR + RBOOT
Parallel combination of small ceramic and large electrolytic capacitors is normally the best compromise, the first acting as fast charge thank for the gate charge only and limiting the dVBS/dt by reducing the equivalent resistance while the second keeps the VBS voltage drop inside the desired VBS. d. Bootstrap Diode The diode must have a BV> 600V (or 1200V depending on application) and a fast recovery time (trr < 100 ns) to minimize the amount of charge fed back from the bootstrap capacitor to VCC supply.
VBS = VCC - VF - VCEon
In this case we have the lowest value for VBS. This represents the worst case for the bootstrap capacitor sizing. When the IGBT is turned off the Vs node is pushed up by the load current until the high side freewheeling diode get forwarded biased ILOAD = 0; the IGBT is not loaded while being on and VCE can be neglected
2.2
Gate resistances
V BS = VCC - VF
ILOAD > 0; the load current flows through the freewheeling diode
V BS = VCC - VF + VFP
In this case we have the highest value for VBS. Turning on the high side IGBT, ILOAD flows into it and VS is pulled up. To minimize the risk of undervoltage, bootstrap capacitor should be sized according to the ILOAD<0 case. b. Bootstrap Resistor A resistor (Rboot) is placed in series with bootstrap diode (see Figure 23) so to limit the current when the bootstrap capacitor is initially charged. We suggest not exceeding some Ohms (typically 5, maximum 10 Ohm) to avoid increasing the VBS time-
The switching speed of the output transistor can be controlled by properly size the resistors controlling the turn-on and turn-off gate current. The following section provides some basic rules for sizing the resistors to obtain the desired switching time and speed by introducing the equivalent output resistance of the gate driver (RDRp and RDRn). The examples always use IGBT power transistor. Figure 24 shows the nomenclature used in the following paragraphs. In addition, Vge* indicates the plateau voltage, Qgc and Qge indicate the gate to collector and gate to emitter charge respectively.
24
IR22381QPBF/IR21381Q(PbF)
IC
CRES
RGon = gate on-resistor RDRp = driver equivalent on-resistance IR22381Q/IR21381Q HOP/LOP and HOQ/LOQ pins can be used to configure gate charge circuit. Fast turn on can be configured using HOP and LOP pins (up to tON1 switching time). For slower turn on times HOQ and LOQ can be used. Current partitioning can be changed acting on the output resistors. In particular, shorting HOP to HOQ and LOP to LOQ, RDRp is defined by
VGE
t1,QGE VCE
t2,QGC dV/dt IC
90%
CRES VGE
CRESon
Vge*
CRESoff
10% 10%
t,Q tSW tDon tR
RDRp
Figure 24: Nomenclature 2.2.1 Sizing the turn-on gate resistor
ton1 Vcc Vcc t SW + t - 1 when t SW > ton1 t SW I o1+ I o 2+ on1 = Vcc when t SW ton1 I o1+
ton1 from "static Electrical
(IO1+ ,IO2+ and Characteristics").
- Switching-time
For the matters of the calculation included hereafter, the switching time tsw is defined as the time spent to reach the end of the plateau voltage (a total Qgc+Qge has been provided to the IGBT gate). To obtain the desired switching time the gate resistance can be sized starting from Qge and Qgc, Vcc, Vge* (see Figure 25):
Table 1 reports the gate resistance size for two commonly used IGBTs (calculation made using typical datasheet values and assuming Vcc=15V).
- Output voltage slope
Turn-on gate resistor RGon can be sized to control output slope (dVOUT/dt). While the output voltage has a non-linear behaviour, the maximum output slope can be approximated by:
I avg =
and
Qgc + Qge t sw
I avg dVout = dt C RESoff
inserting the rearranging: expression
*
RTOT =
* Vcc - V ge
yielding
Iavg
and
I avg
Vcc/Vb RDRp RGon COM/Vs Iavg CRES
RTOT =
Vcc - Vge dV C RESoff out dt
As an example, Table 2 shows the sizing of gate resistance to get dVout/dt=5V/ns when using two popular IGBTs, typical datasheet values and assuming Vcc=15V. NOTICE: Turn on time must be lower than TBL to avoid improper desaturation detection and SSD triggering.
Figure 25: RGon sizing where RTOT = RDRp + RGon
25
IR22381QPBF/IR21381Q(PbF)
Sizing the turn-off gate resistor
The worst case in sizing the turn-off resistor RGoff is when the collector of the IGBT in off state is forced to commutate by external events (i.e. the turn-on of the companion IGBT). In this case the dV/dt of the output node induces a parasitic current through CRESoff flowing in RGoff and RDRn (see Figure 26). If the voltage drop at the gate exceeds the threshold voltage of the IGBT, the device may self turn on causing large oscillation and relevant cross conduction. As a result, when is faster than the collector rise time (to be verified after calculation) the transfer function can be approximated by:
Vge Vde
= s ( RGoff + RDRn ) CRESoff
So that Vge = ( RGoff + RDRn ) C RESoff time domain. Then the condition:
dVde in the dt
Vth > Vge = (RGoff + RDRn ) CRESoff
dVout dt
HS Turning ON
dV/dt
must be verified to avoid spurious turn on. Rearranging the equation yields:
CRESoff RGoff OFF ON RDRn C IES
(1)
RGoff <
Vth CRESoff
dV dt
- RDRn
Figure 26: RGoff sizing: current path when Low Side is off and High Side turns on The transfer function between IGBT collector and IGBT gate then becomes:
In any case, the worst condition for a spurious turn on is with very fast steps on IGBT collector. In that case collector to gate transfer function can be approximated with the capacitor divider:
Vge = Vde
CRESoff
(CRESoff + CIES )
Vge Vde
=
s ( RGoff + RDRn ) CRESoff
1 + s ( RGoff + RDRn ) (CRESoff + CIES )
1 + RDRn ) (CRESoff + CIES )
which is driven only by IGBT characteristics. As an example, table 3 reports RGoff (calculated with the above mentioned equation (1)) for two popular IGBTs to withstand dVout/dt = 5V/ns. NOTICE: the above-described equations are intended being an approximated way for the gate resistances sizing. More accurate sizing may account more precise device modelling and parasitic component dependent on the PCB and power section layout and related connections.
Which yields to a high pass filter with a pole at:
1/ =
( RGoff
Table 1: RGon sizing driven by tsw constraint
IGBT GB15XP120K* GB05XP120K IRGB5B120KD Qge 12nC 3.7nC 3.7nC Qgc 46nC 14nC 13nC Vge* 9V 9.5V 9.5V tsw 500ns 400ns 500ns Iavg 116mA 44mA 33mA Rtot 77 124 164 RGon std commercial value Rtot - RDRp = 15 10 Rtot - RDRp = 65 68 Rtot - RDRp = 102 100 Tsw 465ns 408ns 502ns
Table 2: Table 2: RGon sizing driven by dVOUT/dt constraint
IGBT GB15XP120K* GB05XP120K IRGB120KD Qge 12nC 3.7nC 3.7nc Qgc 46nC 14nC 13nC Vge* 9V 9.5V 9.5V CRESoff 38pF 12pF 11pF Rtot 47 91 100 RGon std commercial value Rtot - RDRp = 4.5 4.7 Rtot - RDRp = 48.8 47 Rtot - RDRp = 57 56 dVout/dt 5V/ns 5.1V/ns 5V/ns
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IR22381QPBF/IR21381Q(PbF)
Table 3: RGoff sizing
IGBT Vth(min) CRESoff 38pF 12pF 11pF RGoff RGoff = 0 RGoff 55 RGoff 63 GB15XP120K* 5 GB05XP120K 5 IRG4PH20K(D) 5 * sized with 18V supply
3
PCB LAYOUT TIPS
Distance from H to L voltage
3.1
The IR22381/IR21381Q pin out lacks some pins (see Figure 17) maximizing the distance between floating (from DC- to DC+) and low voltage pins . It's strongly recommended to place components tied to floating voltage in the respective high voltage portions of the device (VB1,2,3, VS1,2,3) side.
Figure 27: gate drive loop
3.2
Ground plane 3.4 Supply capacitors
IR22381 output stages are able to quickly turn on IGBT with up to 460mA of output current. The supply capacitors must be placed as close as possible to the device pins (VCC and VSS for the ground tied supply, VB and VS for the floating supply) in order to minimize parasitic inductance/resistance.
Ground plane must not be placed under or nearby the high voltage floating side to minimize noise coupling.
3.3
Gate drive loops
Current loops behave like an antenna able to receive and transmit EM noise. In order to reduce EM coupling and improve the power switch turn on/off performances, gate drive loops must be reduced as much as possible. Figure 23 shows the high and low side gate loops. Moreover, current can be injected inside the gate drive loop via the IGBT collector-to-gate parasitic capacitance. The parasitic auto-inductance of the gate loop contributes to develop a voltage across the gate-emitter increasing the possibility of self turn-on effect. For this reason is strongly recommended to place the three gate resistances close together and to minimize the loop area (see Figure 27).
3.5
Routing and placement example
Figure 28 shows one of the possible layout solutions using a 3 layer PCB (low voltage signals not shown) on an ECONO PIM module. This example takes into account all the previous considerations. Placement and routing for supply capacitors and gate resistances in the high and low voltage side minimize respectively supply path and gate drive loop. The bootstrap diode is placed under the device to have the cathode as close as possible to bootstrap capacitor and the anode far from high voltage and close to VCC.
27
IR22381QPBF/IR21381Q(PbF)
a) TOP(Gate Drive)
b) BOTTOM (GND)
28
IR22381QPBF/IR21381Q(PbF)
c) MID (VCC/COM/DCP)
Figure 28: layout example: top (a), internal layer (b) and bottom (c) layer
29
IR22381QPBF/IR21381Q(PbF)
Case Outline
Qualification Level: Industrial level, MSL3, Lead-free. ESD Classification: Human Body Model (HBM): Class 2, per JESD22-A114-B Machine Model (MM): Class B, per EIA/JESD22-A115-A
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 This product has been qualified for the industrial market. Data and specifications are subject to change without notice. 08/11/05.
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