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Ordering number : ENN4922D
CMOS IC
LC72146, 72146M, 72146V
PLL Frequency Synthesizer for Electronic Tuning
Overview
The LC72146 is a PLL frequency synthesizer LSI circuit for electronic tuning in car stereo systems. The LC72146 supports the construction of high-performance, multifunctional electronic tuning systems for the VHF MW, and LW bands.
Features
* High-speed programmable dividers for -- 10 to 160 MHz on FMIN using pulse swallower -- 0.5 to 40.0 MHz on AMIN using pulse swallower and direct division * General-purpose counters -- HCTR for 0.4 to 25.0 MHz frequency measurement -- LCTR for 10 to 500 kHz frequency measurement and 1.0 Hz to 20 x 103 kHz period measurement * Reference frequencies: Twelve selectable reference frequencies (4.5 or 7.2 MHz crystal) 1, 3, 5, 9, 10, 3.125, 6.25, 12.5, 25, 30, 50 and 100 kHz
* Phase comparator -- Insensitive band control -- Unlock detection -- Sub-charge pump for high-speed locking -- Deadlock clear circuit * CCB input/output data interface * Power-on reset circuit * Built-in MOS transistor for a low-pass filter * Inputs/outputs (using five general-purpose input/output ports) -- Maximum of seven inputs (max) -- Maximum of seven outputs (max/four n-channel open-drain and three CMOS outputs) -- Time-base output for clock (8 Hz) * Operating ranges -- Supply voltage ..................................4.5 to 5.5 V -- Opetating temperature ......................-40 to 85C * Package -- DIP24S, MFP24S, SSOP24
* CCB is a trademark of SANYO ELECTRIC CO., LTD. * CCB is SANYO's original bus format and all the bus addresses are controlled by SANYO.
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
N2001TN (OT)/73096HA (OT)/11095TH (OT) No. 4922-1/22
LC72146, 72146M, 72146V
Package Dimensions
unit: mm 3067A-DIP24S
[LC72146]
21.0
unit: mm 3112A-MFP24S
[LC72146M]
24
13
7.62 6.4
24
13
5.4
1
0.9
12
12.5 0.15 0.63
0.25
1
3.3 3.9max (3.25)
12
0.51min
0.35
1.0
(0.71)
1.78
0.48
0.95
SANYO: DIP24S
0.1 1.5
(0.75)
1.7max
SANYO: MFP24S
unit: mm 3175B-SSOP24
[LC72146V]
SANYO: SSOP24
7.6
No. 4922-2/22
LC72146, 72146M, 72146V
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Symbol VDD max VIN1 max Maximum input voltage VIN2 max VIN3 max VO1 max Maximum output voltage VO2 max VO3 max IO1 max Maximum output current IO2 max IO3 max Allowable power dissipation Pd max VDD CE, CL, DI XIN, FMIN, AIN, AMIN, HCTR/I-6, LCTR/I-7, I/O-4, I/O-5 I/O-1 to I/O-3 DO XOUT, I/O-4, I/O-5, O-6, PD0, PF1, AIN I/O-1 to I/O-3, AOUT, O-7 I/O-4, I/O-5, O-6, O-7 DO, AOUT I/O-1 to I/O-3 DIP24S:Ta 85C MFP24S:Ta 85C SSOP24:Ta 85C Operating temperature Storage temperature Topr Tstg Conditions Ratings -0.3 to +7.0 -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to +15 -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to +15 0 to 3.0 0 to 6.0 0 to 10 350 220 150 -40 to +85 -55 to +125 Unit V V V V V V V mA mA mA mW mW mW C C
Allowable Operating Ranges at Ta = -40 to 85C, VSS = 0 V
Parameter Supply voltage Symbol VDD1 VDD2 VIH1 VIH2 VIL1 VIH3 VIL2 VO1 VO2 fIN1 fIN2 Input frequency fIN3 fIN4 fIN5 fIN6 Guaranteed oscillator element frequencies Xtal VIN1 VIN2-1 VIN2-2 VIN3-1 VIN3-2 Input amplitude VIN3-3 VIN3-4 VIN4-1 VIN4-2 VIN5-1 VIN5-2 VIN5-3 Data set up time Data hold time tSU tHD VDD VDD: Serial data retain voltage CE, CL, DI, I/O-1 to I/O-3 I/O-4, I/O-5, HCTR/I-6 and LCTR/I-7 CE, CL, DI and I/O-1 to I/O-5, HCTR/I-6, LCTR/I-7 LCTR/I-7, Pulse wave*1 LCTR/I-7, Pulse wave*1 DO I/O-1 to I/O-3, AOUT, O-7 XIN; Sine wave, capacitive coupling FMIN; Sine wave, capacitive coupling AMIN; Sine wave, capacitive coupling HCTR/I-6; Sine wave, capacitive coupling LCTR/I-7; Sine wave, capacitive coupling LCTR/I-7; Pulse wave, DC coupling*1 XIN, XOUT *2 XIN FMIN; 50 f < 130 MHz*3 FMIN; 10 f < 50 MHz*3, 130 f 160 MHz AMIN; 2 f < 25 MHz*3 AMIN; 25 f < 40 MHz*3 AMIN; 0.5 f < 2.5 MHz*3 AMIN; 2.5 f < 10 MHz*3 HCTR/I-6; 0.4 f < 25 MHz*4 HCTR/I-6; 8 f < 12 MHz*5 LCTR/I-7; 10 f < 400 kHz*4 LCTR/I-7; 400 f < 500 kHz*4 LCTR/I-7; 400 f < 500 kHz*5 DI, CL*6 DI, CL*6 Conditions min 4.5 2.0 2.2 2.2 0 2.2 0 0 0 1.0 10 0.5 0.4 10 1.0 4.0 200 40 70 40 70 40 70 40 70 40 20 70 0.45 0.45 6.5 VDD 0.8 VDD 0.8 6.5 13 8.0 160 40 25 500 20 x 103 8.0 1500 1500 1500 1500 1500 1500 1500 1500 1500 1500 1500 1500 typ max 5.5 Unit V V V V V V V V V MHz MHz MHz MHz kHz Hz MHz mVrms mVrms mVrms mVrms mVrms mVrms mVrms mVrms mVrms mVrms mVrms mVrms S S
Input high-level voltage Input low-level voltage Input high-leve lvoltage Input low-level voltage Output voltage
Continued on next page. No. 4922-3/22
LC72146, 72146M, 72146V
Continued from preceding page.
Parameter Clock low-level time Clock high-level time CE wait time CE setup time CE hold time Chip enable to data latch time Data output time Symbol tCL tCH tEL tES tEH tLC tDC CL*5 CL*5 CE, CL*5 CL, CE*5 CE, CL*5
*5
Conditions
min 0.45 0.45 0.45 0.45 0.45
typ
max
Unit s s s s s
0.45 0.2
s s
DO, CL; Depends on pull-up resistor
Note: 1. Period measurement 2. Recommended crystal oscillator CI values: CI 120 (For a 4.5 MHz crystal) CI 70 (For a 7.2 MHz crystal) 3. See the description of the structure of the programmable divider. 4. With the CTC bit in the serial data set to 0 5. With the CTC bit in the serial data set to 1 6. See the description of the serial data timing.
Electrical Characteristics at Ta = -40 to +85C, VSS = 0 V
Parameter Symbol Rf1 Rf2 Internal feedback resistance Rf3 Rf4 Rf5 Sub charge pump internal resistance Hysteresis R1S VHIS VOH1 VOH2 VOL1 VOL2 Output low-level voltage VOL3 I/O-1 to I/O-3 XIN FMIN AMIN HCTR/I-6 LCTR/I-7 AIN CE, CL, DI, LCTR/I-7 IO = 0.5 mA Output high-level voltage PD0, PD1, I/O-4, I/O-5, O-6 IO = 1 mA IO = 2 mA AIN: IO = 1 mA PD0, PD1, I/O-4, I/O-5, O-6, O-7 AIN: IO = 1 mA IO = 1 mA IO = 2.5 mA IO = 5 mA IO = 9 mA VOL4 VOL5 IIH1 IIH2 Input high-level current IIH3 IIH4 IIH5 IIH6 IIL1 IIL2 Input low-level current IIL3 IIL4 IIL5 IIL6 DO; IO = 5 mA AOUT; IO = 1 mA, AIN = 1.3 V CE, CL, DI; VI = 6.5 V I/O-1 to I/O-3; VI = 13 V I/O-4, I/O-5, HCTR/I-6, LCTR/I-7; VI = VDD XIN; VI = VDD FMIN, AMIN; VI = VDD HCTR/I-6, LCTR/I-7; VI = VDD CE, CL, DI; VI = 0 V I/O-1 to I/O5; VI = 0 V HCTR/I-6, LCTR/I-7; VI = 0 V XIN; VI = 0 V FMIN, AMIN; VI = 0 V HCTR/I-6, LCTR/I-7; VI = 0 V 2.0 4.0 8.0 2.0 4.0 8.0 IO = 0.5 mA IO = 1 mA IO = 2 mA 0.3 VDD - 0.5 VDD - 1.0 VDD - 2.0 VDD - 0.6 VDD - 0.3 0.5 1.0 2.0 0.6 0.2 0.5 1.0 1.8 1.0 0.5 5.0 5.0 5.0 11 22 44 5.0 5.0 5.0 11 22 44 Conditions min typ 1.0 500 500 250 250 100 0.1 VDD max Unit M k k k k V V V V V V V V V V V V V V V A A A A A A A A A A A A
Continued on next page.
No. 4922-4/22
LC72146, 72146M, 72146V
Continued from preceding page.
Parameter Output off leakage current High-level three state off leakage current Lowh-level three state off leakage current Input cacitance Pull-down transistor on resistance Symbol IOFF1 IOFF2 IOFFH IOFFL CIN Rpd1 Rpd2 IDD1 Supply current IDD2 IDD3 Conditions I/O-1 to I/O3, AOUT, O-7; VO = 13 V DO; VO = 6.5 V PD0, PD1, AIN; VO = VDD PD0, PD1, AIN; VO = 0 V FMIN FMIN AMIN VDD; Xtal = 7.2 MHz, fIN2 = 160 MHz, VIN2 = 70 mVrms, fIN4 = 25 MHz VIN4 = 40 mVrms VDD; PLL inhibited, crystal oscillator running (Xtal = 7.2 MHz) VDD; PLL inhibited, crystal oscillator stoped 0.5 1.5 10 mA A 10 15 mA 80 80 0.01 min typ max 5.0 5.0 200 Unit A A nA
0.01 6 200 200
200
nA pF
600 600
k k
Pin Assignment
HCTR/I-6 14 LCTR/I-7 13 AOUT AMIN 16 FMIN VDD 15 VSS VSS 18 PD0 20 PD1 19 XIN AIN 21
24
23
22
17
LC72146, 72146M, 72146V
Top View 1 XOUT 2 CE 3 DI 4 CL 5 DO 6 O-7 7 O-6 8 I/O-5 9 I/O-4 10 I/O-3 11 I/O-2 12 I/O-1
Block Diagram
19 PD1 XIN 24 XOUT 1 REFERENCE DIVIDER PHASE DETECTOR CHARGE PUMP 20 PD0
FMIN 17
SWALLOW COUNTER 1/16, 1/17, 4bits
14 HCTR/I-6
VSS 18 AMIN 16 12bits PROGRAMMABLE DIVIDER 13 LCTR/I-7
CE 2 DI 3 CL 4 DO 5 VDD 15 VSS 23 12 I/O-1 11 I/O-2 10 I/O-3 9 I/O-4 8 I/O-5 7 O-6 POWER ON RESET CCB I/F DATA SHIFT REGISTER LATCH
UNIVERSAL COUNTER 21 AIN 22 AOUT
6 O-7
No. 4922-5/22
LC72146, 72146M, 72146V Pin Functions
Number Symbol Type Function Equivalent circuit
24 1
XIN XOUT
Xtal OSC
Connection for crystal oscillator element (7.2 or 4.5 MHz)
17
FMIN
Local oscillator signal input
* Serial data input: FMIN is selected when DVS is set to 1. Input frequency range: 10 to 160 MHz * The signal is transmitted directly to the swallow counter * Divisor value range: 272 to 65535
16
AMIN
Local oscillator signal input
Serial data input: AMIN is selected when DVS is set to 0. Serial data input: when SNS is set to 1. Input frequency range: 2 to 40 MHz The signal is transmitted directly to the swallow counter. Divisor value range: 272 to 65535 Serial data input: when SNS is set to 0. Input frequency range: 0.5 to 10 MHz The signal is transmitted directly to the 12-bit programmable divider. * Divisor value range: 4 to 4095
* * * * * * * *
2
CE
Chip enable
* This pin must be set high to input serial data to the LC72146 DI pin or to output serial data from the DO pin.
S
4
CL
Clock
* Inputs the clock used for data synchronization when inputting serial data to the LC72146 DI pin or outputting serial data from the DO pin.
S
3
DI
Input data
* Input pin for serial data transmitted to the LC72146 from a controller.
S
5
DO
Output data
* Output pin for serial data transmitted from the LC72146 to a controller.
15
VDD
Power supply
* The LC72146 power supply connection. A voltage between 4.5 and 5.5 volts must be supplied when the PLL circuit is used. * The power on reset circuit operates when power is first applied.
18 23
VDD
Ground
* The LC72146 ground connection.
12 11 10
I/O-1 I/O-2 I/O-3
General-purpose I/O port
* * * *
General-purpose I/O ports Output mode circuit type: open drain Function after a power on reset: input port Can be set up to function as output ports by bits I/O-1 to I/O-3 in the serial data sent from the controller.
Continued on next page. No. 4922-6/22
LC72146, 72146M, 72146V
Continued from preceding page.
Number Symbol Type Function Equivalent circuit
9 8
I/O-4 I/O-5
General-purpose I/O port
* * * *
General-purpose I/O ports Output mode circuit type: complementary Function after a power on reset: input port Can be set up to function as output ports by bits I/O-4 and I/O-5 in the serial data sent from the controller.
7
O-6
Output port
* The LC72146 latches the OUT6 bit in the serial data and outputs it from pin O-6.
6
O-7
Output port
* The LC72146 latches the OUT7 bit in the serial data and outputs it from pin O-7. * Outputs a time base signal (8 Hz) when TBC is set to 1. * Function after a power on reset: open circuit
20 19
PD0 PD1
Charge pump output
* PLL charge pump output pin If the frequency generated by dividing the local oscillator frequency by N is higher than the reference frequency, a high level will be output from PD0, and if it is lower, a low level will be output. PD0 goes to the high-impedance state when the frequencies match. * PD1 operates identically.
21 22
AIN AOUT
* Connections to the n-channel MOS transistor used for the PLL active low-pass filter. Connections for the * A high-speed locking circuit can be formed by using low-pass filter these pins with the built-in sub charge pump. transistor * See the item on the structure of the charge pump for details.
14
HCTR/I-6
General-purpose counter
* HCTR is selected when CTS1 is set to 1. * Input frequency range: 0.4 to 25 MHz * The signal is passed through a divide-by-two circuit and then input to a general-purpose counter. This input also supports an integrating count function. * The result is output from the DO output pin starting with the MSB of the general-purpose counter. * See the item on the structure of the general-purpose counter for details. * When the H/I-6 bit in the serial data is set to 0: * This pin functions as an input port, and the value input is output from the DO pin.
Continued on next page.
No. 4922-7/22
LC72146, 72146M, 72146V
Continued from preceding page.
Number Symbol Type * * * * * * * * * Function LCTR is selected when CTS1 is set to 0. If the CTS0 bit in the serial data is set to 1: The circuit operates in frequency measurement mode. nput frequency range: 10 to 500 kHz The signal is directly transmitted to the general-purpose counter without passing through the divide-by-two circuit. If the CTS0 bit in the serial data is set to 0: The circuit operates in period measurement mode. nput frequency range: 1 Hz to 20 kHz The measurement period can be set to be either one or two periods of the input signal, and if two period measurement is selected, the input frequency range becomes 2 Hz to 40 kHz. The result is output from the DO output pin starting with the MSB of the general-purpose counter. See the item on the structure of the general-purpose counter for details. When the L/I-7 bit in the serial data is set to 0: This pin functions as an input port. The value input is output from the DO pin. Equivalent circuit
S
13
LCTR/I-7
General-purpose counter
* * * *
No. 4922-8/22
DI
Serial Data Input
DI P0 P1 P2 P3 P4 P5 P6 P7 (1) P-CTR P9 P10 P11 P12 P13 P14 P15 SNS DVS (2) PD-C PDC0 PDC1 R0 (3) R-CTR R1 R2 R3 (4) DO-C (5) Don't care DT0 DT1 P8 Address
(5) Don't care
*
I/O-1 I/O-2
(7) I/O-C I/O-4 I/O-5 (5) Don't care (14) TIME OUT1 OUT2 OUT3 (8) O-PORT OUT5 OUT6 OUT7 (9) U/I-C L/I-7 IL0 (4) DO-C ULD (10) Unlock UL1 XS CTP CTC DZ0 DZ1 TEST0 (15) TEST TEST2 (13) PD-L DLC TEST1 (6) U-CTR (11) XTAL (6) U-CTR (12) DZ-C UL0 IL1 H/I-6 OUT4 TBC
Functional Description
First Data In1
Address
00010010
10010010
First Data In2
I/O-3
* *
The LC72146 operating parameters are initialized by two 40-bit data words on the serial data input, DI, as shown in Figure 1 and Figure 2 and Table 1.
Figure 2 Figure 1 Input Data Word IN1 Input Data Word IN2
*
CTE CTS0 CTS1 GT0 GT1
LC72146, 72146M, 72146V
No. 4922-9/22
LC72146, 72146M, 72146V Table 1 Input Data Functions
No. Name Function Programmable divider ratio P15 is the MSB. The divider ratio, frequency range and LSB are determined by the setting of the DVS and SNS flags as shown in Table 2 and Table 3. P0 to P3 are ignored if P4 is the LSB. Table 2 Divider ratio settings DVS 1 0 (1) P0 to P15, DVS, SNS 0 Note: x = don't care Table 3 Frequency range settings DVS 1 0 0 Note: x = don't care Sub-charge pump control Bits PDC0 and PDC1 control the charge pump state as shown in Table 4. The sub-charge pump is connected to the gate of the low-pass filter transistor. This can be used in conjunction with PD0 and PD1 (main charge pump) to build a fast locking PLL. Table 4 Charge pump state selection (2) PDC0, PDC1 PDC1 0 1 1 PDC0 x 1 0 High impedance Operating (operates continuously) Operating (when PLL is unlocked) Charge pump state UL0, UL1, DLC SNS x 1 0 Input port FMIN AMIN AMIN Input frequency range (MHz) 10 to 160 2 to 40 0.5 to 10 SNS x 1 0 LSB P0 P0 P4 Divider ratio (N) 272 to 65535 272 to 65535 4 to 4095 Related bits
Note: x = don't care * See the "Charge Pump" on page 16 for details. Reference frequency select Bits R0 to R3 disable the PLL or select the reference frequency as shown in Table 5. Table 5 Reference frequency selection R3 0 0 0 0 0 0 0 (3) R0 to R3 0 1 1 1 1 1 1 1 1 R2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 R1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 R0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Reference frequency (kHz) 100 50 25 25 12.5 6.25 3.125 3.125 10 9 5 1 3 30 PLL inhibited and crystal oscillator stopped PLL inhibited
When the PLL is disabled, the programmable divider is stopped, AMIN and FMIN are pulled to ground, and the charge-pump outputs become high impedance.
Continued on next page. No. 4922-10/22
LC72146, 72146M, 72146V
Continued from preceding page.
No. Name Function DO and I/O-5 output control data Bits ULD, DT0, DT1, IL0 and IL1 control the mode of outputs DO and I/O-5 as shown in Table 6 and Table 7. Table 6 DO and I/O-5 output flag selection ULD 0 0 0 0 1 1 1 1 DT1 0 0 1 1 0 0 1 1 DT0 0 1 0 1 0 1 0 1 Unlock flag Open End-UC flag*1. IN. See table 7. Open Open End-UC flag IN. See table 7. Unlock flag*2. OUT5 flag*2. DO I/O-5 Related bits
Note: *1. End-UC flags that general-purpose counter operation has finished. *2. Applicable only if I/O-5 is set to be an output port. (4) ULD, DT0, DT1, IL0, IL1
DO
OUT5, I/O-1, I/O-2, I/O-5
Start
Finish (I-1 change)
CE : Hi
A02691
Figure 3 DO output state Table 7 IN state selection IL1 0 0 1 1 IL0 0 1 0 1 Open I-1 input I-2 input DO goes low when I1 changes. IN state
Note: 1. If I/O-1 or I/O-2 is set to be an output port, IN becomes open. 2. DO does not go low when the crystal oscillator has stopped. [When reference frequencies are as these: R3 = R2 = R1 = 1; R0 = 0] (5) * Don't care. Counter control Bits CTS0 and CTS1 select the counter input as shown in Table 8. Table 8 Counter input and measurement mode selection CTS1 1 0 0 CTS0, CTS1, CTE, GT0, GT1 (6) CTS0 x 1 0 Input HCTR LCTR LCTR Measurement mode Frequency Frequency Period
Note: x = don't care Bit CTE starts the counter when 1, and resets the counter, when 0. Bits GT0 and GT1 select the measurement time in frequency measurement mode or the number of periods to count in period measurement mode as shown in Table 9. Table 9 Measurement duration selection Frequency measurement GT1 0 0 1 1 GT0 0 1 0 1 Measurement duration (ms) 4 8 32 64 Wait time (ms) 3 to 4 Period measurement Cycles 1 H/I-6, L/I-7
7 to 8
2
CTP, CTC
When CTE is 0 the input is pulled down, and when CTP is 1 it is not. (Wait time: 1 to 2 ms.) CTP must be set to 1 at least 4 ms before CTE is set to 1. The input sensitivity can be reduced by setting CTC to 1. (Sensitivity: 10 to 30 mV rms)
Continued on next page. No. 4922-11/22
LC72146, 72146M, 72146V
Continued from preceding page.
No. (7) Name I/O-1 to I/O-5 Function Input/output port control Bits I/O-1 to I/O-5 set the direction of the ports. Each pin is an input when the corresponding bit is 0, and an output, when the bit is 1. All ports are set to be inputs after power-on reset. Output port data Bits OUT1 to OUT7 set the output values of the O-1 to O-7 output ports. Each output is open or high when the corresponding bit is 1, and low, when the bit is 0. A bit is ignored if the corresponding port is an input port or the unlock output. Counter input control Bits H/I-6 and L/I-7 select the operation of the HCTR/I-6 and LCTR/I-7 pins. When H/I-6 is 0, HCTR/I-6 is an input port, and when H/I-6 is 1, HCTR/I-6 is the HCTR input. When L/I-7 is 0, LCTR/I-7 is an input port, and when L/I-7 is 1, LCTR/I-7 is the LCTR input. PLL unlock detect control Bits UL0 and UL1 select the phase error threshold and extension (oE) used to detect the PLL unlocked state as shown in Table 10 and Figure 4. When the phase error is greater than the selected error, the PLL unlock detector output goes low. Table 10 Unlock detection and extension selection UL1 0 0 1 (10) UL0, UL1 1 UL0 0 1 0 1 Phase error Stopped 0 0.56 s 1.11 s Open oE output oE with 1 to 2 ms extension oE with 1 to 2 ms extension ULD, DT0, DT1 Detector output Related bits OUT1 to OUT5, ULD
(8)
OUT1 to OUT7
I/O-1 to I/O-5, ULD
(9)
H/I-6, L/I-7
CTS0, CTS1
oE Expansion DO I/O-5 Unlock state output 1 to 2 ms
Figure 4 Phase-error extension Crystal oscillator control Bit XS selects the oscillator frequency. When XS is 1, the frequency is 7.2 MHz, and when XS is 0, 4.5 MHz. 4.5 MHz is selected after power-on reset. Phase comparator control Bits DZ0 and DZ1 select the phase comparator insensitive band, or dead zone. Table 11 Insensitive band mode selection DZ1 0 (12) DZ0, DZ1 0 1 1 DZ0 0 1 0 1 Insensitive band (dead zone) mode DZA DZB DZC DZD
(11)
XS
DZA is selected after power-on reset. Charge pump control Bit DLC controls the charge pump operation. When DLC is 1, the charge pump outputs are forced to low, and when DLC is 0, the charge pump operates normally. This feature can be useful to remove the PLL from a deadlock state. The PLL can deadlock if its VCO control voltage Vtune becomes 0 V, halting the VCO. Setting DLC to 1 sets Vtune to VCC, restarting the VCO. Normal operating mode is selected after power-on reset. An 8 Hz 40% duty clock time base signal can be output from the O-7 by setting TBC to 1. When TBC is 1 the OUT7 data will be invalid. TBC is set to 0 by the power-on reset. Test data Bits TEST0 to TEST2 are used for in-factory device testing. Set them all to 0. They are set to zero after a power-on reset. OUT7
(13)
DLC
(14)
TBC TEST0 to TEST2
(15)
No. 4922-12/22
LC72146, 72146M, 72146V Serial Data Output The 40-bit data word output on DO has the format and functions as shown in Figure 5 and Table 12, respectively.
Address
DI
01010010
First Data OUT
C19
C18
C17
C16
C15
C14
C13
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
DO
(1) IN-PORT
(2) U-CTR
C0 : Data 0
I7
I6
I5
I4
I3
I2
I1
Figure 5 Output Data Word Out Table 12 Input Data Functions
No. Name Function Input port data Bits I1 to I7 reflect the data latched into each input port when the device changes to data output mode. I6 and I7 are zero when the corresponding port is a counter input. I1 to I5 correspond to the I/O-1 to I/O-5 ports, and I6 and I7, to the HCTR/I-6 and LCTR/I-7 inputs, respectively. Counter contents Bits C0 to C19 are the latched contents of the 20-bit binary counter. C19 is the MSB. C0 is the LSB. Related bits I/O-1 to I/O-5, H/I-6, L/I-7 OUT1 to OUT5 CTS0, CTS1, CTE
(1)
I1 to I7
(2)
C0 to C19
Serial Data Input/Output Mode Selection The LC72146 use the CCB (computer control bus) serial data format. The first eight bits form the address, shown in Figure 6, used to select the mode of operation as shown in Table 13. Table 13 Serial Data Input/Output Mode Selection
Input/output mode IN1 IN2 OUT Address B0 0 1 0 B1 0 0 1 B2 0 0 0 B3 1 1 1 A0 0 0 0 A1 0 0 0 A2 1 1 1 A3 0 0 0 32-bit control data input 32-bit control data input Output data. Data is output if the clock is active. Function
I/O mode determined
CE
CL
DI
B0
B1
B2
B3
A0
A1
A2
A3 First Data IN1/2
DO
Figure 6 Mode Selection Address Bits
First Data OUT
No. 4922-13/22
LC72146, 72146M, 72146V 1. Serial data input (IN1/IN2)
tSU * tHD * tEL * tES * tEH * tCL * tCH > 0.45 S tLC < 0.45 S tEL tES tEH
CE CL
tCL tSU tHD B0 B1 B2 B3 A0 A1 A2 A3 P0 P1 P2
tCH
DI
P3
CTS0 CTS1 GT0
GT1 tLC
Internal data
2. Serial data output (OUT)
tSU * tHD * tEL * tES * tEH * tCL * tCH > 0.45 S tDC * tDH < 0.2 S (*1) tEL tES tEH
CE CL
tCL tSU tHD B0 B1 B2 B3 A0 A1 A2 A3 tDC
tCH
DI
tDH I6 I5 I4 C3 C2 C1 C0
DO
(*2)
I7
(*2)
Note: 1. The data conversion time varies with the value of the pull-up resistor, since the DO pin is an n-channel open drain circuit. 2. The DO pin is normally open.
Programmable Divider The configuration of the programmable divider is shown in Figure 7. The input mode selection is shown in Table 14, and the input sensitivity, in Table 15.
4bits (A) FMIN Swallow (B) Counter AMIN fref fvco=fref x N Programmable Divider 12bits fvco/N
(C)
PD
oE
Figure 7 Programmable Divider Table 14 Programmable Divider Selection
DVS 1 0 0 Note: x = don't care SNS x 1 0 Divisor setting (NO) 272 to 65535 272 to 65535 4 to 4095 Input frequency range 10 to 160 MHz 2 to 40 MHz 0.5 to 10 MHz Input port FMIN AMIN AMIN
No. 4922-14/22
LC72146, 72146M, 72146V Table 15 Input Sensitivity (Target Sensitivity)
Minimum input sensitivity (f [MHz]) (A) FMIN 10 f < 50 70 mVrms 2 f < 25 40 mVrms 0.5 f < 2.5 40 mVrms 50 f < 130 40 mVrms 25 f < 40 70 mVrms 2.5 f < 10 70 mVrms 130 f < 160 70 mVrms --
(B) AMIN
(C) AMIN
--
CTC: Input sensitivity switching data. When CTC is 1 the input sensitivity is degraded.However, the actual values will be: HCTR 30 to 40 mVrms (frequency: 10.7 MHz) LCTR 10 to 15 mVrms (frequency: 450 kHz) CTP: The input pull-down resistor (when CTE is 0) can be disabled by setting CTP to 1. CTP must be set to 1 at least 4 ms before CTE is set to 1. CTP should be set to 0 if the counter is not used. When CTP is set to 1 wait time is reduced at 1 to 2 ms. The LC72146 includes a general-purpose 20-bit binary counter whose value can be read out from the DO pin, MBS first. When using this counter for frequency measurement, one of four measurement times (4, 8, 32, or 64 ms) is selected by GT0 and GT1. The frequency input to either the HCTR or the LCTR pin can be measured by determining the number of pulses input to the counter during the measurement period. This counter can be used to measure the period of the signal input to the LCTR pin by determining how many cycles of a reference signal (900 kHz) are input to the counter during one or two periods of the LCTR pin signal. The counter is started by setting the serial data CTE bit to 1. While serial data is latched in the LC72146 when CE falls from high to low, input to the HCTR or the LCTR pin must be provided within the waiting period that follows CE being set low. Next, after the measurement completes, the value of the counter must be read out during the period that CTE is 1. (The general-purpose counter is reset when CTE is set to 0.) It should be emphasized here that the counter should be reset before measurement by setting CTE to 0. Also note that although the signal input to the LCTR pin is input to the counter directly, the signal input to the HCTR pin is divided by two internally before being input to the counter. Accordingly, the value of the counter will be 1/2 the actual frequency input to the HCTR pin.
HCTR 1 2 (FIF) LCTR CTC, CTP One period/two period extraction circuit (T) Input signal switching gate S1 S2 S3 L S B 0 to 3 4 to 7
General-purpose counter (20-bit binary counter) M S B 8 to 11 12 to 1516 to 19
Check signal: 900 kHz
CTS1 CTS0 CTE
DO pin
4/8/32/64 ms
GT
C = FIF x GT C = (1/T) / 900kHz
GT1,GT0
Figure 8 General-Purpose Counter
No. 4922-15/22
LC72146, 72146M, 72146V
CTS1 S1 S2 S3 1 0 0 CTS0 -- 1 0 Input pin HCTR LCTR LCTR Measurement mode Frequency Frequency Period Frequency range 0.4 to 25.0 MHz 10 to 500 kHz 1.0 to 20 x 103 Hz Input sensitivity 40 mVrms* 40 mVrms* (pulse)
Note: * CTC = 0: 40 mVrms CTC = 1: 70 mVrms However, the frequency ranges will be as follows when CTC is 1. HCTR: 8 to 12 MHz, LCTR: 400 to 500 kHz
GT1 0 0 1 1
GT0 0 1 0 1
Frequency measurement mode Measurement time (ms) 4 8 32 64 Wait time (ms) 3 to 4
Period measurement mode One period
7 to 8
Two periods
CE Frequency Measurement time HCTR LCTR Signal input VDD LCTR VSS One period Period Measurement time 900 kHz (check signal) Wait time Measurement time At least 40 mVrms* (during frequency measurement) Note: * CTC = 0 : 40 mVrms CTC = 1 : 70 mVrms 2.2 V (min) However, the frequency ranges will be as follows when CTC is 1. HTCR : 8 to 12 MHz, LCTR : 400 to 500 kHz
0.8 V (max) (during period measurement)
Integrating Count
CTE = 1 CE CTE = 1 CTE = 0
Internal data latch (CTE)
GT
General-purpose counter end-UC (DO) Start Restart
(Integration) Reset
Count complete
Note: CTE: 0
Count complete
* General-purpose counter reset * General-purpose counter start 1 * Restarts on a new 1 setting In integrated count mode, the count value is accumulated in the general-purpose counter. Care is required to handle counter overflow. Counter values: 0H to FFFFFH (1,048,575) To implement the integrating count operation leave CTE set to 1. When the serial data (IN1) is transmitted again, the general-purpose counter will start to measure the input again and the result will be added to the count.
No. 4922-16/22
LC72146, 72146M, 72146V Charge Pump The charge pump configuration is shown in Figure 9.
PD1 DLC
(MAIN)
fvco/N
Phase Detector fref
PD0
(MAIN)
DZ0
DZ1 PDS
A IN A OUT
Clock UL0 UL1
Unlock Detector and Subcharge Pump Cont.
R1S Unlock (SUB) R1S = 100 (typ)
PDC0
PDC1
DO, I/O-5 pin
Figure 9 Charge Pump
PDC1 0 1 1 PDC0 -- 1 0 PDS (sub-charge pump state) High impedance Charge pump operates (normal operation) Charge pump operates (when unlocked) DLC 0 1 PD1, PD0, PDS Normal operation Forced to low
When unlock is detected following a channel change, PDS (the sub-charge pump) operates. The value of R1 changes to R1M // R1S (R1S 100 ), as shown in Figure 10, decreasing the low-pass filter time-constant and accelerating PLL locking.
R1M PDO PDS R1S
VCC
V tune
Figure 10 Charge Pump Connections
No. 4922-17/22
LC72146, 72146M, 72146V The unlock detection data UL1 must be set to 1. The unlock detection range will be set to 0.56 s or 1.11 s. If a phase difference in excess of these values is detected the circuit will go to the unlock state and the sub-charge pump will operate. When the circuit approaches the lock state and the phase difference falls under the unlock detection range, the sub-charge pump operation will stop, i.e., the sub-charge pump will go to the high impedance state. Note: 1. Notes on the phase comparator dead zone
DZ1 0 0 1 1 DZ0 0 1 0 1 Dead zone mode DZA DZB DZC DZD Charge pump ON/ON ON/ON OFF/OFF OFF/OFF Dead zone - -0 s -0 s +0 s + +0 s
Cases where the charge pump is in the ON/ON state require special care during system design since the charge pump outputs correction pulses even when the PLL is locked and it is easy for the loop to become unstable. The following problems may occur in the ON/ON state. x Sidebands may be generated by reference frequency leakage. y Sidebands may be generated by low frequency leakage due to the correction pulse envelope. The settings that have a dead zone (the OFF/OFF settings) provide good loop stability, but it is hard to achieve a good S/N ratio with these settings. Inversely, the settings with no dead zone (the ON/ON settings) allow a high S/N ratio to be achieved but it is hard to achieve good loop stability with these settings. Therefore, it can be effective to select either the DZA or DXB setting, i.e., a setting which has no dead zone, when an S/N ratio of between 90 and 100 dB or higher is required in FM mode, or when the AM stereo pilot margin needs to be increased. However, in cases where such a high FM S/N ratio is not required and where an adequate AM stereo pilot margin can be achieved or AM stereo is not used, either the DZC or DZD setting, i.e., a setting which has a dead zone, should be selected. Dead Zone Definition The phase comparator compares fp with a reference frequency (fr) as shown in Figure 11. Figure 12 shows the characteristics of an ideal phase comparator, which outputs an output voltage (A) that is proportional to the phase difference o. However, in an actual IC, a region (dead zone) in which minute phase differences cannot be detected occurs due to internal circuit delays and other factors. To implement an end product with a high S/N ration, the dead zone should be as small as possible. However, there are cases where a larger dead zone can make a popularly-priced model easier to use. This is because it is possible for RF leakage from the mixer to the VCO to modulate the VCO in popularly-priced models when a strong RF input is applied. When the dead zone is small an output that compensates for this problem is generated, and this output may itself modulate the VCO and generate beating with the RF frequency.
No. 4922-18/22
LC72146, 72146M, 72146V
RF V MIX Leakage Reference Divider Programmable Divider fr fp Phase Detector LPF VCO (A) (B) o (ns) Dead Zone
Figure 11
Figure 12
2. FMIN, AMIN, HCTR and LCTR These inputs should each be capacitively coupled using a 50 to 100 pF capacitor. Also, these capacitors should be mounted as close as possible to their respective inputs. 3. IF counting using HCTR or LCTR The LC72146 can perform IF count tuning when connected to an SD (station detector) signal from an IF IC. IF counting should start when the SD signal becomes active. Note on IF counting: The SD (station detect) signal must be used in conjunction with IF counting. When using the general-purpose counter for IF counting, be sure to determine whether or not there is an SD signal from the IF IC. The IF counter buffer should be turned on and IF counting performed only if there is an SD signal. Autosearch techniques that use only the IF counter are not recommended, since it is possible for IF buffer leakage output to cause incorrect stops at points where there is no station. 4. Using the DO pin In modes other than data output mode, the DO pin is also used for counter completion, unlock detection, and for checking for changes in the input pin. (In these cases the DO pin will change from the high to the low level.) The state of the input pin can be input to the controller directly through the DO pin. 5. Power supply pins Capacitors must be inserted between the power supply VDD and VSS pins for noise exclusion. These capacitors must be placed as close as possible to the VDD and VSS pins. 6. VCO setup Applications must be designed so that the VCO (local oscillator) does not stop, even if the control voltage (Vtune) goes to 0 V. If it is possible for the oscillator to stop, the application must be use the control data (DLC) to temporarily force Vtune to VCC to prevent deadlock from occuring. (Deadlock clear circuit) Pin States at Power On and Reset
Power On Reset XOUT XIN Power On Reset
State
State
DI CL DO O L F F F O: Open L: Low F: Floating F F O-7 O-6 I-5 I-4 I-3 I-2 I-1 O-7 O-6 I/O-5 I/O-4 I/O-3 I/O-2 I/O-1
LC72146, 72146M, 72146V
CE
VSS AOUT AIN PD0 PD1 VSS FMIN AMIN VDD HCTR/I-6 HCTR/I-7 I-6 I-7 F F
No. 4922-19/22
LC72146, 72146M, 72146V Application System Example
- com CE DI CL DO (TB) XOUT CE DI CL DO O-7 O-6 I/O-5 I/O-4 I/O-3 I/O-2 I/O-1 XIN VSS AOUT AIN PD0 PD1 VSS FMIN AMIN VDD HCTR/I-6 HCTR/I-7
FMVCC FMVCO AMVCC AMVCO
SO
end-UC Unlock ST/MON SD
SI
LC72146, 72146M, 72146V
FM IF VCC ST/MON SD STRQ AM VCC IF ST/MON SD STRQ
Note on Clock Time Base Usage A resistor of at least 100 k must be used as the clock time base output pin (O-7) pull-up resistor. Also, the use of a Schmitt circuit is recommended in the controller (microprocessor) input circuit to prevent chattering. Forming a loop filter with the built-in low-pass filter transistor will also serve to prevent degradation of the VCO C/N characteristics. Since the grounding points for the clock time base output pin and the low-pass filter transistor are a common point within the IC, current fluctuations in the clock time base output pin must be kept to a minimum to limit influencing the low-pass filter.
LC72146 VDO Microprocessor Rt 100k S Time base output Schmitt input
VCC
Vt Loop filter
No. 4922-20/22
LC72146, 72146M, 72146V Serial Data Timing
When CL is stopped at the low level
CE
VIH
VIL
tCH CL VIH VIL
tCL VIH VIL tEL tES tEH VIH
DI
VIH VIL tSU
VIH VIL tHD tLC Old New
Internal data latch
When CL is stopped at the high level
CE
VIH
VIL
tCL CL VIH VIL
tCH VIH VIL tEL tES tEH VIH
DI
VIH VIL tSU
VIH VIL tHD tDC tDH
DO tLC Internal data latch Old New
No. 4922-21/22
LC72146, 72146M, 72146V
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of November, 2001. Specifications and information herein are subject to change without notice. PS No. 4922-22/22

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