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PRELIMINARY
W130
Spread Spectrum Desktop/Notebook System Clock
Features
* Maximized EMI suppression using Cypress's Spread Spectrum technology * Six copies of CPU Clock * Eight copies of PCI Clock (synchronous w/CPU clock) * Two copies of 14.318-MHz IOAPIC Clock * Two copies of 48-MHz USB Clock * Three buffered copies of 14.318-MHz reference input * Input is a 14.318-MHz XTAL or reference signal * Selectable 100-MHz or 66-MHz CPU Clocks * Power management control input pins * Test mode and output three-state capability CPU0:5 Clock Skew: ...................................................175 ps PCI_F, PCI1:7 Clock Skew: ......................................... 500 ps CPU to PCI Clock Skew: .............. 1.5 to 4.0 ns (CPU Leads) Logic inputs have 250-k pull-up resistors except SEL100/66#. Table 1. Pin Selectable Frequency SEL 100/66# 0 0 0 0 1 1 Supply Voltages: ....................................... VDDQ3 = 3.3V5% VDDQ2 = 2.5V5% CPU Clock Jitter: ........................................................ 200 ps 1 1 SEL1 0 0 1 1 0 0 1 1 SEL0 0 1 0 1 0 1 0 1 CPU HI-Z 66.6 66.6 66.6 X1/2 100 100 100 PCI HI-Z 33.3 33.3 33.3 X1/6 33.3 33.3 33.3 SPREAD#=0 Don't Care 0.9% Center -1% Down -0.5% Down Don't Care 0.9% Center -1% Down -0.5% Down
Key Specifications
Block Diagram
VDDQ3 REF0 X1 X2 XTAL OSC PLL Ref Freq VDDQ2 APIC0 APIC1 VDDQ2 CPU_STOP# Stop Clock Control 100/66#_SEL SEL0 SEL1 SPREAD# PLL 1 /2//3 CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 VDDQ3 PCI_F Stop Clock Control PCI_STOP# VDDQ3 PCI4 PCI5 PCI6 PCI7 PWR_DWN# Power Power Down Down Control Control VDDQ3 PLL2 48MHz 48MHz PCI1 PCI2 PCI3 REF1 REF2
Pin Configuration
REF0 REF1 GND X1 X2 GND PCI_F PCI1 VDDQ3 PCI2 PCI3 GND PCI4 PCI5 VDDQ3 PCI6 PCI7 GND VDDQ3 GND VDDQ3 48MHz 48MHz GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDQ3 REF2 VDDQ2 APIC0 APIC1 VDDQ2 CPU0 CPU1 CPU2 CPU3 GND VDDQ2 CPU4 CPU5 GND VDDQ3 GND PCI_STOP# CPU_STOP# PWRDWN# SPREAD# SEL0 SEL1 SEL100/66#
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 October 27, 1999, rev. **
PRELIMINARY
Pin Definitions
Pin Name CPU0:5 Pin No. 42, 41, 40, 39, 36, 35 8, 10, 11, 13, 14, 16, 17 7 Pin Type O Pin Description
W130
CPU Clock Outputs 0 through 5: These six CPU clock outputs are controlled by the CPU_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ2. PCI Bus Clock Outputs 1 through 7: These seven PCI clock outputs are controlled by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ3. Fixed PCI Clock Output: Unlike PCI1:7 outputs, this output is not controlled by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ3. CPU_STOP# Input: When brought LOW, clock outputs CPU0:5 are stopped LOW after completing a full clock cycle (2-3 CPU clock latency). When brought HIGH, clock outputs CPU0:5 start beginning with a full clock cycle (2-3 CPU clock latency). PCI_STOP# Input: The PCI_STOP# input enables the PCI 1:7 outputs when HIGH and causes them to remain at logic 0 when LOW. The PCI_STOP signal is latched on the rising edge of PCI_F. Its effects take place on the next PCI_F clock cycle. SPREAD# Input: When brought LOW this pin activates Spread Spectrum clocking. I/O APIC Clock Outputs: Provides 14.318-MHz fixed frequency. The output voltage swing is controlled by VDDQ2. 48-MHz Outputs: Fixed clock outputs at 48 MHz. Output voltage swing is controlled by voltage applied to VDDQ3. Fixed 14.318-MHz Outputs 0 through 2: Used for various system applications. Output voltage swing is controlled by voltage applied to VDDQ3. Frequency Selection Input: Selects power-up default CPU clock frequency as shown in Table 1 on page 1. Crystal Connection or External Reference Frequency Input: Connect to either a 14.318-MHz crystal or reference signal. Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. Power Down Control: When this input is LOW, device goes into a low-power condition. All outputs are held LOW while in power-down. CPU and PCI clock outputs are stopped LOW after completing a full clock cycle (2-3 CPU clock cycle latency). When brought HIGH, CPU, SDRAM and PCI outputs start with a full clock cycle at full operating frequency (3 ms maximum latency). Power Connection: Power supply for core logic, PLL circuitry, PCI output buffers, reference output buffers, and 48-MHz output buffers. Connected to 3.3V supply. Power Connection: Power supply for APIC0:1and CPU0:5 output buffers. Connected to 2.5V supply. Ground Connection: Connect all ground pins to the common system ground plane.
PCI1:7
O
PCI_F
O
CPU_STOP#
30
I
PCI_STOP#
31
I
SPREAD# APIC0:1 48MHz REF0:2 SEL100/66# SEL1, SEL0 X1 X2 PWR_DWN#
28 45, 44 22, 23 1, 2, 47 25, 26, 27 4 5 29
I O O O I I I I
VDDQ3 VDDQ2 GND
9, 15, 19, 21, 33, 48 37,43,46 3, 6, 12, 18, 20, 24, 32, 34, 38
P P G
2
PRELIMINARY
Spread Spectrum Clocking
The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 1. As shown in Figure 1, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is: dB = 6.5 + 9*log10(P) + 9*log10(F)
W130
Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. The output clock is modulated with a waveform depicted in Figure 2. This waveform, as discussed in "Spread Spectrum Clock Generation for the Reduction of Radiated Emissions" by Bush, Fessler, and Hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is -0.5%, 0.9%, or -1.0% of the selected frequency. Figure 2 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices. Spread Spectrum clocking is activated or deactivated by SPREAD# input (pin 28).
5d B/d iv
E M I Reduc tion S S FTG Ty pic a l C loc k
Amplitude (dB)
S pread S pectrum E nabled
NonS pread S pectrum
-S S %
F re q ue n c y S p an (M H z)
+SS%
Figure 1. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
MAX (+0.5%)
FREQUENCY
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
10%
20%
30%
40%
50%
60%
70%
80%
90%
MIN (-0.5%)
Figure 2. Typical Modulation Profile
3
100%
PRELIMINARY
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions Parameter VDD, VIN TSTG TA TB ESDPROT Description Voltage on any pin with respect to GND Storage Temperature Operating Temperature Ambient Temperature under Bias Input ESD Protection
W130
above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating -0.5 to +7.0 -65 to +150 0 to +70 -55 to +125 2 (min.) Unit V C C C kV
DC Electrical Characteristics: TA = 0C to +70C, VDDQ3 = 3.3V5%, VDDQ2 = 2.5V5%
Parameter Supply Current IDDQ3 IDDQ2 3.3V Supply Current 2.5V Supply Current CPU0:5 = 100 MHz Outputs Loaded[1] CPU0:5 = 100 MHz Outputs Loaded[1] GND - 0.3 2.0 95 75 mA mA Description Test Condition Min. Typ. Max. Unit
Logic Inputs VIL VIH IIL IIH IIL IIH VOL VOH VOH IOL Input Low Voltage Input High Voltage Input Low Current[2] Input High Current[2] Input Low Current (SEL100/66#) Input High Current (SEL100/66#) Output Low Voltage Output High Voltage Output High Voltage Output Low Current CPU0:5, APIC0:1 CPU0:5 PCI_F, PCI1:7 APIC0:1 REF0:2 48MHz IOH Output High Current CPU0:5 PCI_F, PCI1:7 IOAPIC REF0:2 48MHz IOL = 1 mA IOH = -1 mA IOH = -1 mA VOL = 1.25V VOL = 1.5V VOL = 1.25V VOL = 1.5V VOL = 1.5V VOL = 1.25V VOL = 1.5V VOL = 1.25V VOL = 1.5V VOL = 1.5V 3.1 2.2 27 20.5 40 25 25 25 31 40 27 27 57 53 85 37 37 55 55 87 44 44 97 139 140 76 76 97 189 155 94 94 0.8 VDD + 0.3 -25 10 -5 5 50 V V A A A A mV V V mA mA mA mA mA mA mA mA mA mA
Clock Outputs
Notes: 1. All clock outputs loaded with 6" 60 transmission lines with 22-pF capacitors. 2. W130 logic inputs have internal pull-up devices, except SEL100/66# (pull-ups not full CMOS level).
4
PRELIMINARY
DC Electrical Characteristics: TA = 0C to +70C, VDDQ3 = 3.3V5%, VDDQ2 = 2.5V5% (continued)
Parameter Crystal Oscillator VTH CLOAD CIN,X1 CIN COUT LIN X1 Input Threshold Voltage[3] Load Capacitance, as seen by External Crystal X1 Input Capacitance
[5] [4]
W130
Description
Test Condition VDDQ3 = 3.3V Pin X2 unconnected Except X1 and X2
Min.
Typ. 1.65 14 28
Max.
Unit V pF pF
Pin Capacitance/Inductance Input Pin Capacitance Output Pin Capacitance Input Pin Inductance 5 6 7 pF pF nH
Notes: 3. X1 input threshold voltage (typical) is VDD/2. 4. The W130 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF; this includes typical stray capacitance of short PCB traces to crystal. 5. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
AC Electrical Characteristics
TA = 0C to +70C, VDDQ3 = 3.3V5%,VDDQ2 = 2.5V 5%, fXTL = 14.31818 MHz AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output; Spread Spectrum clocking is disabled. CPU Clock Outputs, CPU0:5 (Lump Capacitance Test Load = 20 pF) CPU = 66.6 MHz Parameter tP tH tL tR tF tD tJC Description Period High Time Low Time Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Test Condition/Comments Measured on rising edge at 1.25V Duration of clock cycle above 2.0V Duration of clock cycle below 0.4V Measured from 2.0V to 0.4V Measured on rising and falling edge at 1.25V Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.25V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 15 15 5.2 5.0 1 1 45 4 4 55 200 15.5 CPU = 100 MHz Typ. Max. Unit 10.5 ns ns ns 4 4 55 200 V/ns V/ns % ps 10 3.0 2.8 1 1 45 Min. Typ. Max. Min.
Output Rise Edge Rate Measured from 0.4V to 2.0V
tSK fST
Output Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance
175 3
175 3
ps ms
Zo
15
5
PRELIMINARY
PCI Clock Outputs, PCI1:7 and PCI_F (Lump Capacitance Test Load = 30 pF CPU = 66.6/100 MHz Parameter tP tH tL tR tF tD tJC tSK tO fST Description Period High Time Low Time Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Output Skew CPU to PCI Clock Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Measured on rising edge at 1.5V Duration of clock cycle above 2.4V Duration of clock cycle below 0.4V Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output. Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 30 1.5 Min. 30 12 12 1 1 45 4 4 55 250 500 4 3 Typ. Max.
W130
Unit ns ns ns V/ns V/ns % ps ps ns ms
Zo
APIC0:1 Clock Output (Lump Capacitance Test Load = 20 pF) CPU = 66.6/100MHz Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Frequency generated by crystal oscillator Measured from 0.4V to 2.0V Measured from 2.0V to 0.4V Measured on rising and falling edge at 1.25V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 15 1 1 45 Min. Typ. 14.31818 4 4 55 1.5 Max. Unit MHz V/ns V/ns % ms
Zo
REF0:2 Clock Output (Lump Capacitance Test Load = 20 pF) CPU = 66.6/100 MHz Parameter f tR tF tD fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Frequency generated by crystal oscillator Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 40 0.5 0.5 45 Min. Typ. 14.318 2 2 55 3 Max. Unit MHz V/ns V/ns % ms
Zo
6
PRELIMINARY
48-MHz Clock Output (Lump Capacitance Test Load = 20 pF) CPU = 66.6/100 MHz Parameter f fD m/n tR tF tD fST Description Frequency, Actual Deviation from 48 MHz PLL Ratio Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Determined by PLL divider ratio (see m/n below) (48.008 - 48)/48 (14.31818 MHz x 57/17 = 48.008 MHz) Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 40 0.5 0.5 45 Min. Typ. 48.008 +167 57/17 2 2 55 3 Max.
W130
Unit MHz ppm V/ns V/ns % ms
Zo
Ordering Information
Ordering Code W130 Document #: 38-00851 Package Name H Package Type 48-pin SSOP (300 mils)
7
PRELIMINARY
Package Diagram
48-Pin Small Shrink Outline Package (SSOP, 300 mils)
W130
Summary of nominal dimensions in inches: Body Width: 0.296 Lead Pitch: 0.025 Body Length: 0.625 Body Height: 0.102
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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