View AT91SAM7A3_318236.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Features
* Incorporates the ARM7TDMI (R) ARM(R) Thumb(R) Processor
- High-performance 32-bit RISC Architecture - High-density 16-bit Instruction Set - Leader in MIPS/Watt Embedded ICE In-circuit Emulation, Debug Communication Channel Support 256 Kbytes of Internal High-speed Flash, Organized in 1024 Pages of 256 Bytes - Single Cycle Access at Up to 30 MHz in Worst Case Conditions - Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed - Page Programming Time: 4 ms, Including Page Auto-erase, Full Erase Time: 10 ms - 10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities 32K Bytes of Internal High-speed SRAM, Single-cycle Access at Maximum Speed Memory Controller (MC) - Embedded Flash Controller, Abort Status and Misalignment Detection - Memory Protection Unit Reset Controller (RSTC) - Based on Three Power-on Reset Cells - Provides External Reset Signal Shaping and Reset Sources Status Clock Generator (CKGR) - Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and One PLL Power Management Controller (PMC) - Power Optimization Capabilities, including Slow Clock Mode (Down to 500 Hz), Idle Mode, Standby Mode and Backup Mode - Four Programmable External Clock Signals Advanced Interrupt Controller (AIC) - Individually Maskable, Eight-level Priority, Vectored Interrupt Sources - Four External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected Debug Unit (DBGU) - 2-wire UART and Support for Debug Communication Channel interrupt, Programmable ICE Access Prevention Periodic Interval Timer (PIT) - 20-bit Programmable Counter plus 12-bit Interval Counter Windowed Watchdog (WDT) - 12-bit key-protected Programmable Counter - Provides Reset or Interrupt Signal to the System - Counter May Be Stopped While the Processor is in Debug Mode or in Idle State Real-time Timer (RTT) - 32-bit Free-running Counter with Alarm - Runs Off the Internal RC Oscillator Two Parallel Input/Output Controllers (PIO) - Sixty-two Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os - Input Change Interrupt Capability on Each I/O Line - Individually Programmable Open-drain, Pull-up resistor and Synchronous Output Shutdown Controller (SHDWC) - Programmable Shutdown Pin and Wake-up Circuitry Four 32-bit Battery Backup Registers for a Total of 16 Bytes One 8-channel 20-bit PWM Controller (PMWC) One USB 2.0 Full Speed (12 Mbits per Second) Device Port - On-chip Transceiver, 2-Kbyte Configurable Integrated FIFOs Nineteen Peripheral Data Controller (PDC) Channels Two CAN 2.0B Active Controllers, Supporting 11-bit Standard and 29-bit Extended Identifiers - 16 Fully Programmable Message Object Mailboxes, 16-bit Time Stamp Counter Two 8-channel 10-bit Analog-to-Digital Converter
* *
* * * * *
AT91 ARM(R) Thumb(R)-based Microcontrollers AT91SAM7A3 Summary Preliminary
*
* * *
* *
* * * * * * *
6042AS-ATARM-23-Dec-04
Note: This is a summary document. A complete document is available on our Web site at www.atmel.com.
Preliminary
* Three Universal Synchronous/Asynchronous Receiver Transmitters (USART) * * *
- Individual Baud Rate Generator, IrDA Infrared Modulation/Demodulation - Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support Two Master/Slave Serial Peripheral Interfaces (SPI) - 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects Three 3-channel 16-bit Timer/Counters (TC) - Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel - Double PWM Generation, Capture/Waveform Mode, Up/Down Capability Two Synchronous Serial Controllers (SSC) - Independent Clock and Frame Sync Signals for Each Receiver and Transmitter - IS Analog Interface Support, Time Division Multiplex Support - High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer One Two-wire Interface (TWI) - Master Mode Support Only, All Two-wire Atmel EEPROM's Supported Multimedia Card Interface (MCI) - Compliant with Multimedia Cards and SD Cards - Automatic Protocol Control and Fast Automatic Data Transfers with PDC, MMC and SDCard Compliant IEEE 1149.1 JTAG Boundary Scan on All Digital Pins Required Power Supplies: - Embedded 1.8V Regulator, Drawing up to 100 mA for the Core and the External Components, Enables 3.3V Single Supply Mode - 3.3 VDDIO I/O Lines and Flash Power Supply - 1.8V VDDCORE Core Power Supply - 3V to 3.6V VDDANA Analog Power Supply - 3V to 3.6V VDDBU Backup Power Supply 5V-tolerant I/Os Fully Static Operation: 0 Hz to 60 MHz at 1.65V and 85C Worst Case Conditions Available in a 100-lead LQFP Package
* * * *
* * *
Description
The AT91SAM7A3 is a member of a series of 32-bit ARM7(R) microcontrollers with an integrated CAN controller. It features a 256-Kbyte high-speed Flash and 32-Kbyte SRAM, a large set of peripherals, including two 2.0B full CAN controllers, and a complete set of system functions minimizing the number of external components. The device is an ideal migration path for 8-bit microcontroller users looking for additional performance and extended memory. The embedded Flash memory can be programmed in-system via the JTAG-ICE interface. Built-in lock bits protect the firmware from accidental overwrite. The AT91SAM7A3 integrates a complete set of features facilitating debug, including a JTAG In-Circuit-Emulation interface, misalignment detector, interrupt driven debug communication channel for user configurable trace on a console, and JTAG boundary scan for board level debug and test. By combining a high-performance 32-bit RISC processor with a high-density 16-bit instruction set, Flash and SRAM memory, a wide range of peripherals including CAN controllers, 10-bit ADC, Timers and serial communication channels, on a monolithic chip, the AT91SAM7A3 is ideal for many compute-intensive embedded control applications in the automotive, medical and industrial world.
2
AT91SAM7A3 Preliminary
6042AS-ATARM-23-Dec-04
AT91SAM7A3 Preliminary
Block Diagram
Figure 1. AT91SAM7A3 Block Diagram
TDI TDO TMS TCK JTAGSEL TST FIQ IRQ0-IRQ3 DRXD DTXD PCK0-PCK3 PLLRC XIN XOUT GNDBU VDDBU FWKUP WKUP0 WKUP1 SHDW VDDBU VDDIO VDDCORE NRST
PIO
JTAG SCAN System Controller AIC
PDC
ICE
ARM7TDMI Processor
1.8 V Voltage Regulator
VDDIN GND VDDOUT
DBGU
PDC
FLASH 256K Bytes Memory Controller SRAM 32K Bytes
Embedded Flash Controller Memory Protection Unit Address Decoder Abort Status Misalignment Detection
PLL OSC
GPBR
PMC
RCOSC
RTT Shutdown Controller
Peripheral Bridge Peripheral Data Controller
19 channels
POR POR POR PIT
TWI
APB
FIFO
Transceiver
Reset Controller
USB Device
DDM DDP
WDT PIOA
RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 SCK1 RTS1 CTS1 RXD2 TXD2 SCK2 RTS2 CTS2 NPCS00 NPCS01 NPCS02 NPCS03 MISO0 MOSI0 SPCK0 NPCS10 NPCS11 NPCS12 NPCS13 MISO1 MOSI1 SPCK1 MCCK MCCDA MCDA0-MCDA3 AD00 AD01 AD02 AD03 AD04 AD05 AD06 AD07 ADTRG0 ADVREFP VDDANA GNDANA AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 ADTRG1
CAN0 CAN1
PDC
PIOB
USART0
PDC PDC
PWMC
USART1
PDC PDC
PDC
USART2
PDC PDC
PDC PDC
SSC1
PDC
SPI0
PDC PDC
PIO
SSC0
TWD TWCK CANRX0 CANTX0 CANRX1 CANTX1 PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 TF0 TK0 TD0 RD0 RK0 RF0 TF1 TK1 TD1 RD1 RK1 RF1 TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 TCLK3 TCLK4 TCLK5 TIOA3 TIOB3 TIOA4 TIOB4 TIOA5 TIOB5 TCLK6 TCLK7 TCLK8 TIOA6 TIOB6 TIOA7 TIOB7 TIOA8 TIOB8
Timer Counter TC0 TC1
PDC PDC
SPI1
PIO
TC2 Timer Counter TC3 TC4 TC5
MCI
PDC
ADC0
PDC
Timer Counter TC6
ADC1
TC7 TC8
Preliminary
6042AS-ATARM-23-Dec-04
3
Preliminary
Signal Description
Table 1. Signal Description
Signal Name Function Power VDDIN VDDIO VDDBU VDDANA VDDOUT VDDCORE VDDPLL GND GNDANA GNDBU GNDPLL 1.8V Voltage Regulator Power Supply I/O Lines and Flash Power Supply Backup I/O Lines Power Supply Analog Power Supply 1.8V Voltage Regulator Output 1.8V Core Power Supply 1.8V PLL Power Supply Ground Analog Ground Backup Ground PLL Ground Power Power Power Power Power Power Power Ground Ground Ground Ground Clocks, Oscillators and PLLs XIN XOUT PLLRC PCK0 - PCK3 SHDW WKUP0 - WKUP1 FWKUP Main Oscillator Input Main Oscillator Output PLL Filter Programmable Clock Output Shut-Down Control Wake-Up Inputs Force Wake Up Input Output Input Output Output Input Input ICE and JTAG TCK TDI TDO TMS JTAGSEL Test Clock Test Data In Test Data Out Test Mode Select JTAG Selection Reset/Test NRST TST Microcontroller Reset Test Mode Select Debug Unit DRXD DTXD Debug Receive Data Debug Transmit Data Input Output I/O Input Low Pull-down resistor Input Input Output Input Input No pull-up resistor Pull-down resistor No pull-up resistor No pull-up resistor Driven at 0V only. Do not tie over VDDBU Accept between 0V and VDDBU Accept between 0V and VDDBU 2.7V to 3.6V 3V to 3.6V 3V to 3.6V 3V to 3.6V 1.85V typical 1.65V to 1.95V 1.65V to 1.95V Type Active Level Comments
4
AT91SAM7A3 Preliminary
6042AS-ATARM-23-Dec-04
AT91SAM7A3 Preliminary
Table 1. Signal Description (Continued)
Signal Name Function AIC IRQ0 - IRQ3 FIQ External Interrupt Inputs Fast Interrupt Input PIO PA0 - PA31 PB0 - PB29 Parallel IO Controller A Parallel IO Controller B I/O I/O Multimedia Card Interface MCCK MCCDA MCDA0 - MCDA3 Multimedia Card Clock Multimedia Card A Command Multimedia Card A Data Output I/O I/O USB Device Port DDM DDP USB Device Port Data USB Device Port Data + USART SCK0 - SCK1 - SCK2 TXD0 - TXD1 - TXD2 RXD0 - RXD1 RXD2 RTS0 - RTS1 - RTS2 CTS0 - CTS1 - CTS2 Serial Clock Transmit Data Receive Data Request To Send Clear To Send I/O I/O Input Output Input Synchronous Serial Controller TD0 - TD1 RD0 - RD1 TK0 - TK1 RK0 - RK1 TF0 - TF1 RF0 - RF1 Transmit Data Receive Data Transmit Clock Receive Clock Transmit Frame Sync Receive Frame Sync Output Input I/O I/O I/O I/O Timer/Counter TCLK0 - TCLK8 TIOA0 - TIOA8 TIOB0 - TIOB8 External Clock Input I/O Line A I/O Line B Input I/O I/O PWM Controller PWM0 - PWM7 PWM Channels Output Analog Analog Pulled-up input at reset Pulled-up input at reset Input Input Type Active Level Comments
Preliminary
6042AS-ATARM-23-Dec-04
5
Preliminary
Table 1. Signal Description (Continued)
Signal Name Function SPI MISO0-MISO1 MOSI0-MOSI1 SPCK0-SPCK1 NPCS00-NPCS10 NPCS01 - NPCS03 NPCS11 - NPCS13 Master In Slave Out Master Out Slave In SPI Serial Clock SPI Peripheral Chip Select 0 SPI Peripheral Chip Select I/O I/O I/O I/O Output Two-wire Interface TWD TWCK Two-wire Serial Data Two-wire Serial Clock I/O I/O Analog-to-Digital Converter AD00-AD07 AD10-AD17 ADVREFP ADTRG0 - ADTRG1 Analog Inputs Analog Positive Reference ADC Trigger Analog Analog Input CAN Controller CANRX0-CANRX1 CANTX0-CANTX1 CAN Inputs CAN Outputs Input Output Digital pulled-up inputs at reset Low Low Type Active Level Comments
6
AT91SAM7A3 Preliminary
6042AS-ATARM-23-Dec-04
AT91SAM7A3 Preliminary
Package and Pinout
100-lead LQFP Mechanical Overview
Figure 2 shows the orientation of the 100-lead LQFP package. A detailed mechanical description is given in the section Mechanical Characteristics of the product datasheet.
Figure 2. 100-lead LQFP Pinout (Top View)
75 76 51 50
100 1 25
26
Pinout
Table 2. Pinout in 100-lead LQFP Package
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 GND NRST TST PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 VDDIO GND VDDCORE PB2 PB1 PB0 PA0 PA1 PA2 PA3 GND 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VDDBU FWKUP WKUP0 WKUP1 SHDW GNDBU PA4 PA5 PA6 PA7 PA8 PA9 VDDIO GND VDDCORE PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 VDDCORE GND VDDIO PA28 PA29 PA30 PA31 JTAGSEL TDI TMS TCK TDO GND VDDPLL XOUT XIN GNDPLL 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 PLLRC VDDANA ADVREFP GNDANA PB14/AD00 PB15/AD01 PB16/AD02 PB17/AD03 PB18/AD04 PB19/AD05 PB20/AD06 PB21/AD07 VDDIO PB22/AD10 PB23/AD11 PB24/AD12 PB25/AD13 PB26/AD14 PB27/AD15 PB28/AD16 PB29/AD17 DDM DDP VDDOUT VDDIN
Preliminary
6042AS-ATARM-23-Dec-04
7
Preliminary
Power Considerations
Power Supplies
The AT91SAM7A3 has seven types of power supply pins: * * * * VDDIN pin. It powers the voltage regulator; voltage ranges from 2.7V to 3.6V, 3.3V nominal. If the voltage regulator is not used, VDDIN should be connected to GND. VDDIO pin. It powers the I/O lines, the Flash and the USB transceivers; voltage ranges from 3.0V to 3.6V, 3.3V nominal. VDDOUT pin. It is the output of the 1.8V voltage regulator. VDDCORE pins. They power the logic of the device; voltage ranges from 1.65V to 1.95V, 1.8V typical. It might be connected to the VDDOUT pin with decoupling capacitor. VDDCORE is required for the device, including its embedded Flash, to operate correctly. VDDPLL pins. They power the PLL; voltage ranges from 1.65V to 1.95V, 1.8V typical. They can be connected to the VDDOUT pin with decoupling capacitor. VDDBU pin. It powers the Slow Clock oscillator and the Real Time Clock, as well as a part of the System Controller; ranges from 3.0V and 3.6V, 3.3V nominal. VDDANA pin. It powers the ADC; ranges from 3.0V and 3.6V, 3.3V nominal.
* * *
Separated ground pins are provided for VDDPLL, VDDIO, VDDBU and VDDANA. The ground pins are respectively GNDPLL, GND, GNDBU and GNDANA.
Voltage Regulator
The AT91SAM7A3 embeds a voltage regulator that consumes less than 120 A static current and draws up to 100 mA of output current. Adequate output supply decoupling is mandatory for VDDOUT to reduce ripple and avoid oscillations. The best way to achieve this is to use two capacitors in parallel: one external 470 pF (or 1 nF) NPO capacitor must be connected between VDDOUT and GND as close to the chip as possible. One external 3.3 F (or 4.7 F) X7R capacitor must be connected between VDDOUT and GND. Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip. For example, two capacitors can be used in parallel: 100 nF NPO and 4.7 F X7R.
8
AT91SAM7A3 Preliminary
6042AS-ATARM-23-Dec-04
AT91SAM7A3 Preliminary
Typical Powering Schematics
3.3V Single Supply The AT91SAM7A3 supports a 3.3V single supply mode. The internal regulator is connected to the 3.3V source and its output feeds VDDCORE and VDDPLL. Figure 3 shows the power schematics to be used for USB bus-powered systems. Figure 3. 3.3V System Single Power Supply Schematics
VDDBU VDDANA DC/DC Converter USB Connector up to 5.5V 3.3V VDDOUT VDDIO VDDIN Voltage Regulator
VDDCORE VDDPLL
Preliminary
6042AS-ATARM-23-Dec-04
9
Preliminary
I/O Lines Considerations
JTAG Port Pins
TMS, TDI and TCK are schmitt trigger inputs. TMS and TCK are 5V-tolerant, TDI is not. TMS, TDI and TCK do not integrate any resistors and have to be pulled-up externally. TDO is an output, driven at up to VDDIO. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. The JTAGSEL pin integrates a permanent pull-down resistor so that it can be left unconnected for normal operations.
Test Pin
The TST pin is used for manufacturing tests and integrates a pull-down resistor so that it can be left unconnected for normal operations. Driving this line at a high level leads to unpredictable results. The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components or asserted low externally to reset the microcontroller. There is no constraint on the length of the reset pulse, and the reset controller can guarantee a minimum pulse length. This allows connection of a simple push-button on the NRST pin as system user reset, and the use of the NRST signal to reset all the components of the system. All the I/O lines PA0 to PA31 and PB0 to PB29 are 5V-tolerant and all integrate a programmable pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the PIO Controllers. 5V-tolerant means that the I/O lines can drive voltage level according to VDDIO, but can be driven with a voltage at up to 5.5V. However, driving an I/O line with a voltage over VDDIO while the programmable pull-up resistor is enabled can lead to unpredictable results. Care should be taken, especially at reset, as all the I/O lines default as inputs with pull-up resistor enabled at reset.
Reset Pin
PIO Controller A and B Lines
Shutdown Logic Pins
The SHDW pin is an open drain output. It can be tied to VDDBU with an external pull-up resistor. The FWUP, WKUP0 and WKUP1 pins are input-only. They can accept voltages only between 0V and VDDBU. It is recommended to tie these pins either to GND or to VDDBU with an external resistor.
I/O Line Drive Levels
All the I/O lines can draw up to 2 mA.
10
AT91SAM7A3 Preliminary
6042AS-ATARM-23-Dec-04
AT91SAM7A3 Preliminary
Processor and Architecture
ARM7TDMI Processor
* * RISC Processor Based on ARMv4T Von Neumann Architecture - - - * - - - Runs at up to 60 MHz, providing 0.9 MIPS/MHz ARM high-performance 32-bit Instruction Set Thumb high code density 16-bit Instruction Set Instruction Fetch (F) Instruction Decode (D) Execute (E) Two instruction sets
Three-stage pipeline architecture
Debug and Test Features *
Integrated embedded in-circuit emulator - - - Two watchpoint units Test access port accessible through a JTAG protocol Debug communication channel Two-pin UART Debug communication channel interrupt handling Chip ID Register
*
Debug Unit - - -
*
IEEE1149.1 JTAG Boundary-scan on all digital pins Bus Arbiter - Handles requests from the ARM7TDMI and the Peripheral Data Controller Three internal 1Mbyte memory areas One 256 Mbyte embedded peripheral area Source, Type and all parameters of the access leading to an abort are saved Facilitates debug by detection of bad pointers Alignment checking of all data accesses Abort generation in case of misalignment Remaps the Internal SRAM in place of the embedded non-volatile memory Allows handling of dynamic exception vectors Individually programmable size between 1K Bytes and 1M Bytes Individually programmable protection against write and/or user access Peripheral protection against write and/or user access Embedded Flash interface, up to three programmable wait states Address Decoder Provides Selection Signals for - -
Memory Controller
* *
*
Abort Status Registers - -
*
Misalignment Detector - -
*
Remap Command - -
*
16-area Memory Protection Unit - - -
*
Embedded Flash Controller -
Preliminary
6042AS-ATARM-23-Dec-04
11
Preliminary
- - - - Read-optimized interface, buffering and anticipating the 16-bit requests, reducing the required wait states Password-protected program, erase and lock/unlock sequencer Automatic consecutive programming, erasing and locking operations Interrupt generation in case of forbidden operation
Peripheral Data Controller
* *
Handles data transfer between peripherals and memories Nineteen Channels - - - - - - Two for each USART Two for the Debug Unit Two for each Serial Synchronous Controller Two for each Serial Peripheral Interface One for the Multimedia Card Interface One for each Analog-to-Digital Converter One Master Clock cycle needed for a transfer from memory to peripheral Two Master Clock cycles needed for a transfer from peripheral to memory
*
Low bus arbitration overhead - -
*
Next Pointer management for reducing interrupt latency requirements
12
AT91SAM7A3 Preliminary
6042AS-ATARM-23-Dec-04
AT91SAM7A3 Preliminary
Memory
Embedded Memories
* 256 Kbytes of Flash Memory - - - - - - * - 1024 pages of 256 bytes. Fast access time, 30 MHz single cycle access in worst case conditions. Page programming time: 4 ms, including page auto-erase Full erase time: 10 ms 10,000 write cycles, 10-year data retention capability 16 lock bits, each protecting 64 pages Single-cycle access at full speed
32 Kbytes of Fast SRAM
Memory Mapping
Internal RAM The AT91SAM7A3 embeds a high-speed 32-Kbyte SRAM bank. After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0020 0000. After Remap, the SRAM also becomes available at address 0x0. The AT91SAM7A3 features one bank of 256 Kbytes of Flash. The Flash is mapped to address 0x0010 0000. It is also accessible at address 0x0 after the reset and before the Remap Command. Figure 4. Internal Memory Mapping
0x0000 0000
0x000F FFFF
Internal Flash
Flash Before Remap SRAM After Remap Internal Flash
1M Bytes
0x0010 0000 1M Bytes
0x001F FFFF
0x0020 0000 256M Bytes
0x002F FFFF 0x0030 0000
Internal SRAM
1M Bytes
Undefined Areas (Abort)
253M Bytes
0x0FFF FFFF
Preliminary
6042AS-ATARM-23-Dec-04
13
Preliminary
Embedded Flash
Flash Organization The Flash block of the AT91SAM7A3 is organized in 1024 pages of 256 bytes. It reads as 65,536 32-bit words. The Flash block contains a 256-byte write buffer, accessible through a 32-bit interface. Embedded Flash Controller The Embedded Flash Controller (EFC) manages accesses performed by the masters of the system. It enables reading the Flash and writing the write buffer. It also contains a User Interface mapped within the Memory Controller on the APB. The User Interface allows: * * * * * programming of the access parameters of the Flash (number of wait states, timings, etc.) starting commands such as full erase, page erase, page program, NVM bit set, NVM bit clear, etc. getting the end status of the last command getting error status programming interrupts on the end of the last commands or on errors
The Embedded Flash Controller also provides a dual 32-bit Prefetch Buffer that optimizes 16-bit access to the Flash. This is particularly efficient when the processor is running in Thumb mode. Lock Regions The Embedded Flash Controller manages 16 lock bits to protect 16 regions of the Flash against inadvertent Flash erasing or programming commands. The AT91SAM7A3 has 16 lock regions. Each lock region contains 64 pages of 256 bytes. Each lock region has a size of 16 kbytes. The 16 NVM bits are software programmable through the EFC User Interface. The command "Set Lock Bit" enables the protection. The command "Clear Lock Bit" unlocks the lock region.
14
AT91SAM7A3 Preliminary
6042AS-ATARM-23-Dec-04
AT91SAM7A3 Preliminary
System Controller
The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset.
Figure 5. System Controller Block Diagram
System Controller
irq0-irq1-irq2-irq3 fiq periph_irq[2..27] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq MCK periph_nreset dbgu_rxd wdt_fault WDRPROC jtag_nreset
Boundary Scan TAP Controller
nirq nfiq
Advanced Interrupt Controller
proc_nreset int PCK debug
ARM7TDMI
ice_nreset dbgu_irq force_ntrst
Debug Unit
force_ntrst dbgu_txd
VDDIO POR VDDCORE POR
NRST
periph_nreset ice_nreset jtag_nreset flash_poe proc_nreset
Reset Controller
proc_nreset rstc_irq
Embedded Flash
VDDBU POR
SLCK
VDDCORE Powered Real-Time Timer
rtt_irq MCK proc_nreset
SLCK periph_nreset FWKUP WKUP0 WKUP1 SHDW
Memory Controller
Shutdown Controller VDDBU Powered RCOSC
SLCK
4 General-Purpose Backup Regs
XIN XOUT
MAIN OSC
MAINCK periph_clk[2..27] pck[0-3] UDPCK periph_clk[27] periph_nreset periph_irq[27]
PLLRC
PLL
int periph_nreset MCK debug periph_nreset SLCK debug idle proc_nreset periph_nreset periph_clk[2..3] dbgu_rxd
PLLCK
Power Management Controller
PCK UDPCK MCK pmc_irq idle
USB Device Port
Periodic Interval Timer Watchdog Timer
pit_irq periph_clk[4..26] periph_nreset
wdt_irq wdt_fault WDRPROC periph_irq{2..3] irq0-irq1-irq2-irq3
periph_irq[4..26]
Embedded Peripherals
PIOs Controller
fiq dbgu_txd in out enable
PA0-PA31 PB0-PB29
Preliminary
6042AS-ATARM-23-Dec-04
15
Preliminary
System Controller Mapping
The System Controller peripherals are all mapped to the highest 4K bytes of address space, between addresses 0xFFFF F000 and 0xFFFF FFFF. Each peripheral has an address space of 256 or 512 Bytes, representing 64 or 128 registers. Figure 6 shows the mapping of the System Controller and of the Memory Controller Figure 6. System Controller Mapping
Address
0xFFFF F000
Peripheral
Peripheral Name
Size
AIC
0xFFFF F1FF 0xFFFF F200
Advanced Interrupt Controller
512 Bytes/128 registers
DBGU
0xFFFF F3FF 0xFFFF F400
Debug Unit
512 Bytes/128 registers
PIOA
0xFFFF F5FF 0xFFFF F600
PIO Controller A
512 Bytes/128 registers
PIOB
0xFFFF F5FF 0xFFFF F800
PIO Controller B
512 Bytes/128 registers
Reserved
0xFFFF FBFF 0xFFFF FC00
PMC
0xFFFF FCFF 0xFFFF FD00 0xFFFF FD0F 0xFFFF FD10 0xFFFF FC1F 0xFFFF FD20 0xFFFF FC2F 0xFFFF FD30 0xFFFF FC3F 0xFFFF FD40 0xFFFF FD4F 0xFFFF FD60 0xFFFF FC6F 0xFFFF FD70 0xFFFF FD80
Power Management Controller Reset Controller Shutdown Controller Real-time Timer Periodic Interval Timer Watchdog Timer
256 Bytes/64 registers 16 Bytes/4 registers 16 Bytes/4 registers 16 Bytes/4 registers 16 Bytes/4 registers 16 Bytes/4 registers
RSTC SHDWC RTT PIT WDT Reserved Reserved GPBR Reserved
General Purpose Backup Registers
16 Bytes/4 registers
0xFFFF FF00
MC
0xFFFF FFFF
Memory Controller
256 Bytes/64 registers
16
AT91SAM7A3 Preliminary
6042AS-ATARM-23-Dec-04
AT91SAM7A3 Preliminary
Reset Controller
The Reset Controller is based on three power-on reset cells. It gives the status of the last reset, indicating whether it is a general reset, a wake-up reset, a software reset, a user reset or a watchdog reset. In addition, it controls the internal resets and the NRST pin output. It shapes a signal on the NRST line, guaranteeing that the length of the pulse meets any requirement. The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL with the following characteristics: - - - - RC Oscillator ranges between 22 KHz and 42 KHz Main Oscillator frequency ranges between 3 and 20 MHz Main Oscillator can be bypassed PLL output ranges between 80 and 220 MHz
Clock Generator
It provides SLCK, MAINCK and PLLCK. Figure 7. Clock Generator Block Diagram
Clock Generator
Embedded RC Oscillator XIN XOUT
Slow Clock SLCK
Main Oscillator
Main Clock MAINCK
PLLRC
PLL and Divider
PLL Clock PLLCK Control
Status
Power Management Controller
Preliminary
6042AS-ATARM-23-Dec-04
17
Preliminary
Power Management Controller
The Power Management Controller uses the Clock Generator outputs to provide: - - - - - the Processor Clock PCK the Master Clock MCK the USB Clock UDPCK all the peripheral clocks, independently controllable four programmable clock outputs
The Master Clock (MCK) is programmable from a few hundred Hz to the maximum operating frequency of the device. The Processor Clock (PCK) switches off when entering processor idle mode, thereby reducing power consumption while waiting an interrupt. Figure 8. Power Management Controller Block Diagram
Processor Clock Controller Master Clock Controller SLCK MAINCK PLLCK Prescaler /1,/2,/4,...,/64 Peripherals Clock Controller ON/OFF Idle Mode MCK PCK int
periph_clk[2..26]
Programmable Clock Controller SLCK MAINCK PLLCK Prescaler /1,/2,/4,...,/64
pck[0..3]
USB Clock Controller ON/OFF PLLCK Divider /1,/2,/4
UDPCK
Advanced Interrupt Controller
* *
Controls the interrupt lines (nIRQ and nFIQ) of the ARM Processor Individually maskable and vectored interrupt sources - - - - - Source 0 is reserved for the Fast Interrupt Input (FIQ) Source 1 is reserved for system peripherals (ST, PMC, DBGU, etc.) Other sources control the peripheral interrupts or external interrupts Programmable edge-triggered or level-sensitive internal sources Programmable positive/negative edge-triggered or high/low level-sensitive external sources Drives the normal interrupt nIRQ of the processor Handles priority of the interrupt sources Higher priority interrupts can be served during service of a lower priority interrupt Optimizes interrupt service routine branch and execution
*
8-level Priority Controller - - -
*
Vectoring -
18
AT91SAM7A3 Preliminary
6042AS-ATARM-23-Dec-04
AT91SAM7A3 Preliminary
- - * * * - - - One 32-bit vector register per interrupt source Interrupt vector register reads the corresponding current interrupt vector Easy debugging by preventing automatic operations Permits redirecting any interrupt source on the fast interrupt Provides processor synchronization on events without triggering an interrupt
Protect Mode Fast Forcing General Interrupt Mask
Debug Unit
*
Comprises - - - - One two-pin UART One interface for the Debug Communication Channel (DCC) support One set of chip ID registers One interface allowing ICE access prevention USART-compatible user interface Programmable baud rate generator Parity, framing and overrun error Automatic Echo, Local Loopback and Remote Loopback Channel Modes Offers visibility of COMMRX and COMMTX signals from the ARM Processor Identification of the device revision, sizes of the embedded memories, set of peripherals Chip ID is 0x170A0940 (Version 0)
*
Two-pin UART - - - -
* *
Debug Communication Channel Support - - - Chip ID Registers
Period Interval Timer Watchdog Timer
* * * *
20-bit programmable counter plus 12-bit interval counter 12-bit key-protected Programmable Counter running on prescaled SLCK Provides reset or interrupt signals to the system Counter may be stopped while the processor is in debug state or in idle mode 32-bit free-running counter with alarm Programmable 16-bit prescaler for SCLK accuracy compensation Software programmable assertion of the SHDW open-drain pin De-assertion programmable with the pins WKUP0, WKUP1 and FWKUP The PIO Controllers A and B respectively control 32 and 30 programmable I/O Lines Fully programmable through Set/Clear Registers Multiplexing of two peripheral functions per I/O Line For each I/O Line (whether assigned to a peripheral or used as general purpose I/O) - - Input change interrupt Half a clock period Glitch filter
Real-time Timer
* *
Shutdown Controller
* *
PIO Controllers A and B
* * * *
Preliminary
6042AS-ATARM-23-Dec-04
19
Preliminary
- - - * Multi-drive option enables driving in open drain Programmable pull up on each I/O line Pin data status register, supplies visibility of the level on the pin at any time
Synchronous output, provides Set and Clear of several I/O lines in a single write
20
AT91SAM7A3 Preliminary
6042AS-ATARM-23-Dec-04
AT91SAM7A3 Preliminary
Peripherals
Peripheral Mapping
Each User Peripheral is allocated 16K bytes of address space. Figure 9. User Peripherals Mapping
Address
0xF000 0000
Peripheral
Peripheral Name
Size
Reserved
0xFFF7 FFFF
0xFFF8 0000
0xFFF8 3FFF
CAN0
CAN Controller 0
16K Bytes
0xFFF8 4000
0xFFF8 7FFF 0xFFF8 8000
CAN1
CAN Controller 1
16K Bytes
Reserved
0xFFF9 FFFF
0xFFFA 0000
0xFFFA 3FFF
TC0, TC1, TC2
Timer/Counter 0, 1 and 2
16K Bytes
0xFFFA 4000
0xFFFA 7FFF
TC3, TC4, TC5
Timer/Counter 3, 4 and 5
16K Bytes
0xFFFA 8000
0xFFFA BFFF
TC6, TC7, TC8
Timer/Counter 6, 7 and 8
16K Bytes
0xFFFA C000
0xFFFA FFFF
MCI
Multimedia Card Interface
16K Bytes
0xFFFB 0000
0xFFFB 3FFF 0xFFFB 4000
UDP
USB Device Port
16K Bytes
Reserved
0xFFFB 7FFF
0xFFFB 8000
0xFFFB BFFF 0xFFFB C000
TWI
Two-Wire Interface
16K Bytes
Reserved 0xFFFC 0000
0xFFFB FFFF
USART0
0xFFFC 3FFF
Universal Synchronous Asynchronous Receiver Transmitter 0 Universal Synchronous Asynchronous Receiver Transmitter 1 Universal Synchronous Asynchronous Receiver Transmitter 1 PWM Controller Serial Synchronous Controller 0
16K Bytes
0xFFFC 4000
0xFFFC 7FFF
USART1
16K Bytes
0xFFFC 8000
USART2
16K Bytes
0xFFFC BFFF
0xFFFC C000 PWMC
0xFFFC FFFF
16K Bytes
0xFFFD 0000
0xFFFD 3FFF
SSC0
16K Bytes
0xFFFD 4000
0xFFFD 7FFF
SSC1
Serial Synchronous Controller 1
16K Bytes
0xFFFD 8000
0xFFFD BFFF
ADC0
Analog-to-Digital Converter 0
16K Bytes
0xFFFD C000
0xFFFD FFFF
ADC1
Analog-to-Digital Converter 1
16K Bytes
0xFFFE 0000
0xFFFE 3FFF
SPI0
Serial Peripheral Interface 0
16K Bytes
0xFFFE 4000
0xFFFE 7FFF 0xFFFE 8000
SPI1
Serial Peripheral Interface 1
16K Bytes
Reserved
0xFFFE FFFF
Preliminary
6042AS-ATARM-23-Dec-04
21
Preliminary
Peripheral Multiplexing on PIO Lines
The AT91SAM7A3 features two PIO controllers, PIOA and PIOB, which multiplex the I/O lines of the peripheral set. PIO Controllers A and B control respectively 32 and 30 lines. Each line can be assigned to one of two peripheral functions, A or B. Some of them can also be multiplexed with Analog Input of both ADC Controllers. Table 3 on page 23 and Table 4 on page 24 define how the I/O lines of the peripherals A, B or Analog Input are multiplexed on the PIO Controllers A and B. The two columns "Function" and "Comments" have been inserted for the user's own comments; they may be used to track how pins are defined in an application. Note that some peripheral functions that are output only may be duplicated within both tables. At reset, all I/O lines are automatically configured as input with the programmable pullup enabled, so that the device is maintained in a static state as soon as a reset occurs.
22
AT91SAM7A3 Preliminary
6042AS-ATARM-23-Dec-04
AT91SAM7A3 Preliminary
PIO Controller A Multiplexing
Table 3. Multiplexing on PIO Controller A
PIO Controller A I/O Line PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 Peripheral A TWD TWCK RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 RXD2 TXD2 NPCS00 NPCS01 NPCS02 NPCS03 MISO0 MOSI0 SPCK0 PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 CANRX0 CANTX0 CANRX1 CANTX1 DRXD DTXD TCLK3 TCLK6 TCLK7 TCLK8 MCDA1 MCDA2 MCDA3 MCDA0 MCCDA MCCK PCK0 PCK1 PCK2 PCK3 IRQ0 IRQ1 TCLK4 TCLK5 NPSC10 NPCS11 NPCS12 NPCS13 MISO1 MOSI1 SPCK1 Peripheral B ADTRG0 ADTRG1 Comment Function Application Usage Comments
Preliminary
6042AS-ATARM-23-Dec-04
23
Preliminary
PIO Controller B Multiplexing
Table 4. Multiplexing on PIO Controller B
PIO Controller B I/O Line PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 Peripheral A IRQ2 IRQ3 TF0 TK0 TD0 RD0 RK0 RF0 FIQ TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 TIOA3 TIOB3 TIOA4 TIOB4 TIOA5 TIOB5 TIOA6 TIOB6 TIOA7 TIOB7 TIOA8 TIOB8 RTS1 CTS1 SCK1 RTS2 CTS2 SCK2 Peripheral B PWM5 PWM6 PWM7 PCK0 PCK1 PCK2 PCK3 CANTX1 TF1 TK1 RK1 RF1 TD1 RD1 PWM0 PWM1 PWM2 PWM3 PWM4 NPCS11 NPCS12 NPCS13 AD00 AD01 AD02 AD03 AD04 AD05 AD06 AD07 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 Comment Function Application Usage Comments
24
AT91SAM7A3 Preliminary
6042AS-ATARM-23-Dec-04
AT91SAM7A3 Preliminary
Peripheral Identifiers
The AT91SAM7A3 embeds a wide range of peripherals. Table 5 defines the Peripheral Identifiers of the AT91SAM7A3. Unique peripheral identifiers are defined for both the AIC and the PMC. Table 5. Peripheral Identifiers
Peripheral ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Peripheral Mnemonic AIC SYSIRQ(1) PIOA PIOB CAN0 CAN1 US0 US1 US2 MCI TWI SPI0 SPI1 SSC0 SSC1 TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7 TC8 ADC0(1) ADC1(1) PWMC UDP AIC AIC AIC AIC Parallel I/O Controller A Parallel I/O Controller B CAN Controller 0 CAN Controller 1 USART 0 USART 1 USART 2 Multimedia Card Interface Two-wire Interface Serial Peripheral Interface 0 Serial Peripheral Interface 1 Synchronous Serial Controller 0 Synchronous Serial Controller 1 Timer/Counter 0 Timer/Counter 1 Timer/Counter 2 Timer/Counter 3 Timer/Counter 4 Timer/Counter 5 Timer/Counter 6 Timer/Counter 7 Timer/Counter 8 Analog-to Digital Converter 0 Analog-to Digital Converter 1 PWM Controller USB Device Port Advanced Interrupt Controller Advanced Interrupt Controller Advanced Interrupt Controller Advanced Interrupt Controller IRQ0 IRQ1 IRQ2 IRQ3 Peripheral Name Advanced Interrupt Controller External Interrupt FIQ
Note:
1. Setting SYSIRQ and ADC bits in the clock set/clear registers of the PMC has no effect. The System Controller and ADC are continuously clocked.
Preliminary
6042AS-ATARM-23-Dec-04
25
Preliminary
Serial Peripheral Interface
* Supports communication with external serial devices - - - - * - - - - - - Four chip selects with external decoder allow communication with up to 15 peripherals Serial memories, such as DataFlash(R) and 3-wire EEPROMs Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors External co-processors 8- to 16-bit programmable data length per chip select Programmable phase and polarity per chip select Programmable transfer delays per chip select between consecutive transfers and between clock and data Programmable delay between consecutive transfers Selectable mode fault detection Maximum frequency at up to Master Clock
Master or slave serial peripheral bus interface
Two-wire Interface
* * * *
Master Mode only Compatibility with standard two-wire serial memories One, two or three bytes for slave address Sequential read/write operations Programmable Baud Rate Generator 5- to 9-bit full-duplex synchronous or asynchronous serial communications - - - - - - - - - 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode Parity generation and error detection Framing error detection, overrun error detection MSB- or LSB-first Optional break generation and detection By 8 or by 16 over-sampling receiver frequency Hardware handshaking RTS-CTS Receiver time-out and transmitter timeguard Optional Multi-drop Mode with address generation and detection
USART
* *
* * * *
RS485 with driver control signal ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards - - - NACK handling, error counter with repetition and iteration limit Communication at up to 115.2 Kbps Remote Loopback, Local Loopback, Automatic Echo IrDA modulation and demodulation Test Modes
Serial Synchronous Controller
* *
Provides serial synchronous communication links used in audio and telecom applications Contains an independent receiver and transmitter and a common clock divider
26
AT91SAM7A3 Preliminary
6042AS-ATARM-23-Dec-04
AT91SAM7A3 Preliminary
* * * Offers a configurable frame sync and data length Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal Three 16-bit Timer Counter Channels Wide range of functions including: - - - - - - - * - - Frequency Measurement Event Counting Interval Measurement Pulse Generation Delay Timing Pulse Width Modulation Up/down Capabilities Three external clock inputs Five internal clock inputs as defined in Table 6.
Timer Counter
* *
Each channel is user-configurable and contains:
Table 6. Timer Counter Clock Assignment
TC Clock input TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 Clock MCK/2 MCK/8 MCK/32 MCK/128 MCK/1024
- -
Two multi-purpose input/output signals Two global registers that act on all three TC Channels
PWM Controller
* *
Eight channels, one 20-bit counter per channel Common clock generator, providing thirteen different clocks - - A Modulo n counter providing eleven clocks Two independent linear dividers working on modulo n counter outputs Independent enable/disable commands Independent clock selection Independent period and duty cycle, with double buffering Programmable selection of the output waveform polarity Programmable center or left aligned output waveform
*
Independent channel programming - - - - -
USB Device Port
* * *
USB V2.0 full-speed compliant,12 Mbits per second. Embedded USB V2.0 full-speed transceiver Six endpoints
Preliminary
6042AS-ATARM-23-Dec-04
27
Preliminary
- - - - * * - Endpoint 0: 8 bytes Endpoint 1 and 2: 64 bytes ping-pong Endpoint 3: 64 bytes Endpoint 4 and 5: 512 bytes ping-pong Ping-pong Mode (two memory banks) for isochronous and bulk endpoints
Embedded 2,376-byte dual-port RAM for endpoints Suspend/resume logic Compatibility with MultiMedia card specification version 2.2 Compatibility with SD Memory card specification version 1.0 Cards clock rate up to Master Clock divided by 2 Embeds power management to slow down clock rate when not used Supports up to sixteen slots (through multiplexing) - One slot for one MultiMedia card bus (up to 30 cards) or one SD memory card
Multimedia Card Interface
* * * * *
* *
Supports stream, block and multi-block data read and write Supports connection to Peripheral Data Controller - Minimizes processor intervention for large buffer transfers
CAN Controller
* * *
Fully compliant with CAN 2.0B active controllers Bit rates up to 1Mbit/s 16 object-oriented mailboxes, each with the following properties: - - - - - - - - - - - - CAN specification 2.0 Part A or 2.0 Part B programmable for each message Object-configurable as receive (with overwrite or not) or transmit Local tag and mask filters up to 29-bit identifier/channel 32-bit access to data registers for each mailbox data object Uses a 16-bit time stamp on receive and transmit messages Hardware concatenation of ID unmasked bit fields to speed up family ID processing 16-bit internal timer for Time Stamping and Network synchronization Programmable reception buffer length up to 16 mailbox object Priority management between transmission mailboxes Autobaud and listening mode Low power mode and programmable wake-up on bus activity or by the application Data, remote, error and overload frame handling
Analog-to-Digital Converter
* * * * * *
8-channel ADC 10-bit 384K samples/sec Successive Approximation Register ADC -2/+2 LSB Integral Non Linearity, -1/+2 LSB Differential Non Linearity Integrated 8-to-1 multiplexer, offering eight independent 3.3V analog inputs Individual enable and disable of each channel External voltage reference for better accuracy on low-voltage inputs
28
AT91SAM7A3 Preliminary
6042AS-ATARM-23-Dec-04
AT91SAM7A3 Preliminary
* Multiple trigger sources - - - * - * Hardware or software trigger External pins: ADTRG0 and ADTRG1 Timer Counter 0 to 5 outputs: TIOA0 to TIOA5 Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels
Sleep Mode and conversion sequencer
All analog inputs are shared with digital signals
Preliminary
6042AS-ATARM-23-Dec-04
29
Preliminary
Ordering Information
Table 7. Ordering Information
Ordering Code AT91SAM7A3-AJ Package 100-lead LQFP Temperature Operating Range Industrial (-40C to 85C)
30
AT91SAM7A3 Preliminary
6042AS-ATARM-23-Dec-04
AT91SAM7A3 Preliminary
Document Details
Title Literature Number AT91SAM7A3 Summary 6042S
Revision History
Version A Publication Date: 23-Dec-04
Preliminary
6042AS-ATARM-23-Dec-04
31
Preliminary
Atmel Corporation
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
Atmel Operations
Memory
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314
RF/Automotive
Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759
Regional Headquarters
Europe
Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500
Microcontrollers
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60
Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom
Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80
Asia
Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369
ASIC/ASSP/Smart Cards
Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743
Japan
9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
Literature Requests
www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
(c) Atmel Corporation 2004. All rights reserved. Atmel(R), logo and combinations thereof and DataFlash(R) are the registered trademarks, and Everywhere You Are TM is the trademark of Atmel Corporation or its subsidiaries. ARM (R), Thumb (R), ARM7TDMI(R), ARM7(R) and ARM Powered (R) are registered trademarks of ARM, Ltd. Other terms and product names may be the trademarks of others.
Printed on recycled paper.
6042AS-ATARM-23-Dec-04

▲Up To Search▲

Price & Availability of AT91SAM7A3

	To Download AT91SAM7A3 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .