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PRELIMINARY
CY62256V
32K x 8 Static RAM
Features
* Low voltage range: -- 2.7V - 3.6V (62256V) -- 2.3V - 2.7V (62256V25) * * * * * -- 1.6V - 2.0V (62256V18) Low active power and standby power Easy memory expansion with CE and OE features TTL-compatible inputs and outputs Automatic power-down when deselected CMOS for optimum speed/power ers. These devices have an automatic power-down feature, reducing the power consumption by over 99% when deselected. The CY62256V family is available in the standard 450-mil-wide (300-mil body width) SOIC, TSOP, and reverse TSOP packages. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH.
Functional Description
The CY62256V family is composed of three high-performance CMOS static RAM's organized as 32,768 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and three-state driv-
Logic Block Diagram
Pin Configurations
SOIC Top View A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3
C62256V-2
INPUTBUFFER A10 A9 A8 A7 A6 A5 A4 A3 A2 CE WE OE
C62256V-1
I/O0 I/O1 I/O2
512x512 ARRA Y
I/O3 I/O4 I/O5
COLUMN DECODER
POWER DOWN
I/O6 I/O7
A11 A10 A9 A8 A7 A6 A5 VCC WE A4 A3 A2 A1 OE
7 6 5 4 3 2 1 28 27 26 25 24 23 22
8 9 10 11 12 13 14 15 16 17 18 19 20 21
TSOP I Reverse Pinout Top View (not to scale)
A12 A13 A14 I/O0 I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 I/O7 CE A0
C62256V-4
OE A1 A2 A3 A4 WE VCC A5 A6 A7 A8 A9 A10 A11
22 23 24 25 26 27 28 1 2 3 4 5 6 7
21 20 19 18 17 16 15 14 13 12 11 10 9 8
TSOP I Top View (not to scale)
A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A14 A13 A12
C62256V-3
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 March 1996 - Revised April 1998
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................... -65C to + 150C Ambient Temperature with Power Applied .................................................. 0C to + 70C Supply Voltage to Ground Potential (Pin 28 to Pin 14)................................................-0.5V to + 4.6V DC Voltage Applied to Outputs in High Z State[1] ....................................... -0.5V to VCC + 0.5V DC Input Voltage .................................... -0.5V to VCC + 0.5V
[1]
CY62256V
Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... >200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 1.6V to 3.6V 1.6V to 3.6V
Note: 1. VIL (min.) = -2.0V for pulse durations of less than 20 ns.
Product Portfolio
Power Dissipation ( LL Devices) Product Min. CY62256V CY62256V25 CY62256V18 2.7V 2.3V 1.6V Vcc Range Typ. 3.0 2.5V 1.8V Max. 3.6V 2.7V 2.0V 70 ns 100 ns 200 ns Speed Operating(Icc) Typical 11 mA 9 mA 5 mA Maximum 30 mA 15 mA 10 mA Standby (ISB2) Typical 0.1 uA 0.1 uA 0.1 uA Maximum 5 uA 4 uA 3 uA
Electrical Characteristics Over the Operating Range
CY62256V-70 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current-- TTL Inputs Automatic CE Power-Down Current-- CMOS Inputs GND < VI < VCC GND < VO < VCC, Output Disabled VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC - 0.3V VIN > VCC - 0.3V or VIN < 0.3V, f=0 Com'l Com'l Com'l Ind'l Std/L /LL Std/L /LL Std/ L LL LL Test Conditions VCC = Min., IOH = -1.0 mA VCC = Min., IOL = 2.1 mA 2.2 -0.5 -1 -1 11 100 0.1 Min. 2.4 0.4 VCC +0.3V 0.8 +1 +1 30 300 50 5 10 Typ.[2] Max. Unit V V V V uA uA mA uA uA uA uA
Electrical Characteristics Over the Operating Range
CY62256V25-100 Parameter VOH VOL VIH VIL IIX Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current GND < VI < VCC Test Conditions VCC = Min., IOH = -0.1 mA VCC = Min., IOL = 0.1 mA 1.7 -0.3 -1 Min. 2 0.4 Vcc + 0.3V 0.7 +1 Typ.[2] Max. Unit V V V V uA
2
PRELIMINARY
Electrical Characteristics Over the Operating Range (continued)
CY62256V
CY62256V25-100 Parameter IOZ ICC ISB1 Description Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current-- TTL Inputs Automatic CE Power-Down Current -- CMOS Inputs Test Conditions GND < VO < VCC, Output Disabled VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC - 0.3V VIN > VCC - 0.3V or VIN < 0.3V, f=0 Com'l Com'l Stnd/L /LL Stnd/L /LL Stnd/L LL Ind'l LL 0.1 Min. -1 14 75 Typ.[2] Max. +1 23 225 Unit uA mA uA
ISB2
Com'l
40 4 8
uA uA uA
Electrical Characteristics Over the Operating Range
CY62256V18-200 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current-- TTL Inputs Automatic CE Power-Down Current-- CMOS Inputs GND < VI < VCC GND < VO < VCC, Output Disabled VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Com'l Stnd/L /LL Stnd/L /LL Stnd/L LL Ind'l LL 0.1 Test Conditions VCC = Min., IOH = -0.1 mA VCC = Min., IOL = 0.1 mA 0.7*Vcc -0.5 -1 -1 10 56 Min. 0.8*Vcc 0.2 VCC +0.3V 0.2*Vcc +1 +1 17 165 Typ.[2] Max. Unit V V V V uA uA mA uA
Max. VCC, CE > VIH, Com'l VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC - 0.3V VIN > VCC - 0.3V or VIN < 0.3V, f=0 Com'l
ISB2
30 3 6
uA uA uA
Capacitance[3]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.0V Max. 6 8 Unit pF pF
Notes: 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = Vcc Typ., TA = 25C, and tAA=70ns. 3. Tested initially and after any design or process changes that may affect these parameters.
3
PRELIMINARY
AC Test Loads and Waveforms
R1 Vcc OUTPUT 50 pF INCLUDING JIG AND SCOPE Equivalent to: R2 Vcc 10% GND < 5 ns
C62256V-5
CY62256V
ALL INPUT PULSES 90% 90% 10% < 5 ns
C62256V-6
THEVENIN EQUIVALENT Rth V th
OUTPUT
AC Test Load Vcc R1 R2 RTH VTH 3.3 V 1103 1554 645 1.75V 2.5V 16.6K 15.4K 8K 1.2V 1.8V 13.6K 11.4K 6.2K 0.82V
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR Description VCC for Data Retention Data Retention Current Coml Stnd/L LL Ind. tCDR[3] tR[3] Chip Deselect to Data Retention Time Operation Recovery Time LL VCC = 1.6 CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V 0 tRC Conditions[4] Min. 1.4 30 0.1 3 6 Typ.[2] Max. Unit V uA uA uA ns ns
Data Retention Waveform
DATA RETENTION MODE VCC 1.8V tCDR CE
C62256V-7
VDR > 1.4V
1.8V tR
4
PRELIMINARY
Switching Characteristics Over the Operating Range[5]
CY62256V-70 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD WRITE CYCLE tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE
[8,9]
CY62256V
CY62256V25-100 CY62256V18-200 Min. 100 Max. Min. 200 100 10 10 100 75 5 10 50 10 10 50 0 0 100 100 90 90 0 0 80 60 0 200 180 180 0 0 160 100 0 50 10 10 100 200 75 75 200 125 200 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z[6] OE HIGH to High Z CE LOW to Low Z CE HIGH to High Z
[6, 7] [6] [6, 7]
Min. 70
Max.
70 10 70 35 5 25 10 25 0 70 70 60 60 0 0 50 30 0 25 10
CE LOW to Power-Up CE HIGH to Power-Down Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE LOW to High Z
[6, 7]
WE HIGH to Low Z[6]
Notes: 4. No input may exceed VCC+0.3V. 5. Test conditions assume signal transition time of 5 ns or less timing reference levels of Vcc/2, input pulse levels of 0 to Vcc, and output loading of the specified IOL/IOH and 100-pF load capacitance. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage.
Switching Waveforms
Read Cycle No. 1[10, 11]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
C62256V-8
[10, 11]
5
PRELIMINARY
Switching Waveforms (continued)
Read Cycle No. 2 [11, 12]
t RC
CY62256V
CE tACE OE tDOE t LZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT t PU 50%
t HZOE tHZCE DATA VALID t PD
HIGH IMPEDANCE
DATA OUT
ICC 50% ISB
C62256V-9
Write Cycle No. 1 (WE Controlled)
[8, 13, 14]
tWC ADDRESS
CE tAW WE tSA t PWE tHA
OE tSD DATA I/O NOTE 15 t HZOE DATAINVALID
C62256V-10
tHD
Notes: 8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 10. Device is continuously selected. OE, CE = VIL. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE transition LOW.
6
PRELIMINARY
Switching Waveforms (continued)
Write Cycle No. 2 (CE Controlled) [8, 13, 14]
tWC ADDRESS CE tSA tAW WE tSD DATA I/O DATAINVALID t HD tHA tSCE
CY62256V
C62256V-11
Write Cycle No. 3 (WE Controlled, OE LOW)
[ 9, 14]
tWC ADDRESS
CE tAW tSA WE tSD DATA I/O NOTE 15 t HZWE
Notes: 13. Data I/O is high impedance if OE = VIH. 14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 15. During this period, the I/Os are in output state and input signals should not be applied.
t HA
t HD
DATA INVALID tLZWE
C62256V-12
7
PRELIMINARY
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.2 0.0 SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 2.5 2.0 1.6 1.4
Vcc=2.5V Vcc=3.0V
CY62256V
NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 1.4
Vcc=3.0V
STANDBY CURRENT vs. AMBIENT TEMPERATURE 3.0 2.5 2.0 1.5
1.2 1.0 0.8
Vcc=2.5V
0.6 TA =25C
Vcc=1.8V
1.0 0.5 0.0 25 125 -0.5 ISB
0.4
-55
-55
25
105
AMBIENT TEMPERATURE (C) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (C) OUTPUT SINK CURRENT 14 vs. OUTPUT VOLTAGE 12 10 8 6
1.5 1.0 0.5 0.0 1.65 TA =25C
1.2 1.0
Vcc=1.8V
Vcc=2.5 V
4 2
0.8 0.6 2.1 2.6 3.1 3.6 SUPPLY VOLTAGE (V)
TA =25C
-55
25
125
0 0.0
1.0
2.0
3.0
AMBIENT TEMPERATURE (C) OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE -14 -12 -10 -8
Vcc=2.5V
OUTPUT VOLTAGE (V)
-6
TA =25C
-4 0 0.0 0.5 1.0 1.5 2 2.5
OUTPUT VOLTAGE (V)
8
PRELIMINARY
Typical DC and AC Characteristics (continued)
TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 1.5 30.0 25.0 1.0 20.0 15.0 0.5 10.0 5.0 0.0 0.0 1.0 2.0 3.0 4.0 0.0 0 200 400 600 800 1000 0.50 1 10 0.75 TA =25C Vcc =3V TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 1.25
Vcc=1.8V
CY62256V
NORMALIZED I CC vs.CYCLE TIME
Vcc=3.0V
1.00 TA =25C VIN =0.5V
20
30
SUPPLY VOLTAGE (V)
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
9
PRELIMINARY
Truth Table
CE H L L L WE X H L H OE X L X H Inputs/Outputs High Z Data Out Data In High Z Read Write Deselect, Output Disabled Mode Deselect/Power-Down Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
CY62256V
Ordering Information
Speed (ns) 70 Ordering Code CY62256V -70SNC CY62256V L-70SNC CY62256V LL-70SNC CY62256V -70ZRC CY62256V L-70ZRC CY62256V LL-70ZRC CY62256V -70ZC CY62256V L-70ZC CY62256V LL-70ZC CY62256V -70ZI CY62256V L-70ZI CY62256V LL-70ZI CY62256V -70SNI CY62256VL -70SNI CY62256VLL -70SNI CY62256V -70ZRI CY62256V L-70ZRI CY62256V LL-70ZRI 100 CY62256V25-100SNC CY62256V25L-100SNC CY62256V25LL-100SNC CY62256V25-100ZRC CY62256V25L-100ZRC CY62256V25LL-100ZRC CY62256V25-100ZC 100 200 CY62256V25L-100ZC CY62256V25LL-100ZC CY62256V18-200SNC CY62256V18L-200SNC CY62256V18LL-200SNC CY62256V18-200ZRC CY62256V18L-200ZRC CY62256V18LL-200ZRC CY62256V18-200ZC CY62256V18LL-200ZC 200 CY62256V18L-200ZC Z28 28-Lead Thin Small Outline Package Commercial
Shaded area contains advanced information.
Package Name S22
Package Type 28-Lead 450-Mil (300-Mil Body Width) SOIC
Operating Range Commercial
ZR28
28-Lead Reverse Thin Small Outline Package
Z28
28-Lead Thin Small Outline Package
Z28
28-Lead Thin Small Outline Package
Industrial
S22
28-Lead 450-Mil (300-Mil Body Width) SOIC
ZR28
28-Lead Reverse Thin Small Outline Package
S22
28-Lead 450-Mil (300-Mil Body Width) SOIC
Commercial
ZR28
28-Lead Reverse Thin Small Outline Package
Z28 Z28 S22
28-Lead Thin Small Outline Package 28-Lead Thin Small Outline Package 28-Lead 450-Mil (300-Mil Body Width) SOIC Commercial Commercial
ZR28
28-Lead Reverse Thin Small Outline Package
Z28
28-Lead Thin Small Outline Package
Document #: 38-00519-A
10
PRELIMINARY
Package Diagrams
28-Lead 450-Mil (300-Mil Body Width) SOIC S22
CY62256V
28-Lead Reverse Thin Small Outline Package ZR28
11
PRELIMINARY
Package Diagrams (continued)
28-Lead Thin Small Outline Package Z28
CY62256V
(c) Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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