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| Integrated Circuit Systems, Inc. ICS9179-19 Advance Information Advance Information Zero Delay Buffer Features * * * * * * * * Spread Spectrum Clock Compatible Distributes one clock input to ten outputs Operating frequency 33MHz to 150MHz External feedback input (FBIN) terminal is used to synchronize the outputs to the clock input No external RC network required Operates at 3.3V Plastic 28-pin 209mil SSOP package Slew rate 1.5V/ns into 30pF. General Description The ICS9179-19 generates low skew clock buffers required for high speed microprocessor systems such as today's Intel Pentium III or AMD K7. Outputs can be enabled or disabled separately via OE. The device is a buffer with low output to output skew. This is a zero delay buffer device, using an internal PLL. This buffer can be used for phase synchronization to a master clock. With the wide PLL loop BW, this buffer is compatible to Spread Spectrum input clocks from clock generator products. Block Diagram FB_OUT CLK0 CLK1 FBIN CLKIN CLK2 PLL CLK3 CLK4 CLK5 CLK6 CLK7 CLK8 CLK9 OE Pin Configuration OE GND CLK0 CLK1 VDD CLK_IN FB_IN GND CLK2 CLK3 VDD GND CLK4 CLK5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GND CLK6 CLK7 VDD GND VDDF FB_OUT GND VDD CLK8 CLK9 AGND VDDA VDD 28 Pin SSOP 9179-19 Rev - 10/31/00 ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. ICS9179-19 ICS9179-19 Advance Information Pin Descriptions PIN NUMBER 1 2, 8, 12, 21, 24, 28 5, 11, 15, 20, 25 6 7 16 17 22 23 27, 26, 19, 18, 14, 13, 10, 9, 4, 3 PIN NAME OE2 GND VDD CLK_IN FBIN AVDD AGND FBOUT1 VDDF CLK (9:0) TYPE IN PWR PWR IN IN PWR PWR OUT PWR OUT DESCRIPTION Output Enable Ground for output buffers Power Supply (3.3V) Clock input Feedback input Analog power supply (3.3V) Ground for analog PLL stages Feedback output Power supply for feedback circuit (3.3V) Buffered clock outputs Notes: 1. Weak pull-down on all outputs 2. Weak pull-ups on these inputs 2 ICS9179-19 Advance Information Absolute Maximum Ratings Supply Voltage (AVDD) . . . . . . . . . . . . . . . . . . . Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . AVDD < (VDD + 0.7V) 4.3 V GND -0.5 V to VDD +0.5 V 0C to +70C -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics at 3.3V VDD = 3.0 - 3.6V, TA = 0 - 70 C unless otherwise stated Recommended operating condition Symbol VDD VIH VIL VI TA Parameter Power Supply Voltage High-level Input Voltage Low-level Input Voltage Input Voltage Operating free-air temperature 0 0 Min. 3 2 0.8 VCC 70 Typ. 3.3 Max. 3.6 Unit V V V V C Electrical Characteristics Over Operating free-air Temperature Range Symbol VIK VOH Param eter Input clamp voltage Output High Voltage Test Conditions V DD=3V,Ii=-18m A V DD=MIN to MAX,Ii=-100uA V DD=3V,Ii=-6mA V DD=3V,Ii=-12m A V DD=MIN to MAX,Ii=100uA VOL Ii AICC ICC Output Low Voltage Input current Analog Supply Current Quiescent Supply Current (test mode) ICC Cin Co Power Supply Current Input Capacitance Output Capacitance V DD=3V,Ii=6mA V DD=3V,Ii=12m A V DD=3.6V,Vi=VDD or GND V DD=3.3V @ 133MHz V DD=MAX, AVDD=LOW,CLKIN=LOW Oex=HIGH,all outputs unloaded V DD = 3.3 to 3.6V @ 100MHz all outputs unloaded V DD=3.3V,Vi=VDD or GND V DD=3.3V,Vi=VDD or GND 4 8 VDD-0.2 2.4 2.1 0.2 0.55 0.8 5 Min. Typ. Max. -1.2 Unit V V V V V V V uA mA mA TBD mA pF pF Note: For conditions shown as MIN or MAX, use the appropriate value specified under recom mended operating condidion 3 ICS9179-19 Advance Information Timing requirements over recommended ranges of supply voltage and operating free-air temperature Symbol Fclk Parameter Input clock frequency Test Conditions Min. 25 Max. 175 Unit MHz Input clock frequency 40 60 % duty cycle Stabilization time After power up 1 ms Note: Time required for the PLL circuit to obtain phase lock of its feedback signal to its reference In order for phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be Until phase lock is obtained, the specifications for parameters given in the switching characteristics table are not Switching characteristics over recommended ranges of supply voltage and operating free-air temperature C L=25pF,RL=500ohms 1 VCC=3.3V 0.165V Symbol Parameter Tpe Phase error Phase error-jitter Tpe 3 Tsk(0)2 TO(OUTPUT) FBIN FBIN Any CLK or Output-Output Skew Any CLKOUT or FBOUT FBOUT Any CLK or Jitter(pk-pk) CLKIN=66M Hz to 100M Hz FBOUT Any CLK or Jitter(cycle-cycle) CLKIN=66M Hz to 100M Hz FBOUT Any CLK or Duty cycle CLKIN>30M Hz FBOUT Output rise time Any CLK or (0.4V to 2V) FBOUT Output fall time Any CLK or (2V to 0.4V) FBOUT Propagation Delay Any CLK or for Buffer M ode CLK_IN FBOUT AVCC=0, Vt=1.5V 4 CLK_IN=33 + 166M Hz Any CLK JittterSSC From(INPUT) 60M Hz Notes: 1. Guaranteed by design and characterization. Not subject to 100% test. 2. The Tsk specification is only valid for equal loading of all outputs. 3. Phase error does not include jitter. The total phase error is -230 ps to 230 ps for the 5% VCC range. 4. JitterSSC = Spread Spectrum Clock induce tracking error 4 ICS9179-19 Advance Information PARAMETER MEASUREMENT INFORMATION From Output Under Test 25 pF 500 Figure 1. Load Circuit for Outputs Notes: Figure 2. Voltage Waveforms 1. CL includes probe and jig capacitance. Propagation Delay Times 2. All input pulses are supplied by generators having the following characteristics: PRR 133 MHz, Z O = 5 0 W, Tr 1.2 ns, Tf 1.2 ns. 3. The outputs are measured one at a time with one transition per measurement. CLK_IN FB_IN Tpe (phase error) FB_OUT Any CLK Tsk(o) Any CLK Any CLK Tsk(o) Figure 3. Phase Error and Skew Calculations 5 ICS9179-19 Advance Information SYMBOL In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX 0.05 1.65 0.22 2.00 1.85 0.38 .002 .065 .009 .079 .073 .015 A A1 A2 b c D E E1 e L N VARIATIONS N 28 0.09 0.25 SEE VARIATIONS 7.40 8.20 5.00 5.60 0.65 BASIC 0.55 0.95 SEE VARIATIONS 0 8 .0035 .010 SEE VARIATIONS .291 .323 .197 .220 0.0256 BASIC .022 .037 SEE VARIATIONS 0 8 D mm. MIN 9.90 MAX 10.50 MIN .390 D (inch) MAX .413 6/1/00 Rev B MO-150 JEDEC Doc.# 10-0033 Ordering Information ICS9179yF-19-T Example: ICS XXXX y F - PPP - T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. 6 |
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