View IDT70V9289L_322097.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HIGH-SPEED 3.3V 64K x18/x16 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
Features:

IDT70V9389/289L

True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access - Commercial: 6/7.5/9/12ns (max.) - Industrial: 9ns (max.) Low-power operation - IDT70V9389/289L Active: 500mW (typ.) Standby: 1.5mW (typ.) Flow-Through or Pipelined output mode on either port via the FT/PIPE pins Counter enable and reset features Dual chip enables allow for depth expansion without additional logic

Full synchronous operation on both ports - 3.5ns setup to clock and 0ns hold on all control, data, and address inputs - Data input, address, and control registers - Fast 6.5ns clock to data out in the Pipelined output mode - Self-timed write allows fast cycle time - 10ns cycle time, 100MHz operation in Pipelined output mode Separate upper-byte and lower-byte controls for multiplexed bus and bus matching compatibility LVTTL- compatible, single 3.3V (0.3V) power supply Industrial temperature range (-40C to +85C) is available for selected speeds Available in a 128-pin Thin Quad Flatpack (TQFP) and 100-pin Thin Quad Flatpack (TQFP)
Functional Block Diagram
R/WL
UBL CE0L
UBR
R/WR
CE1L
LBL OEL
1 0 0/1
1 0 0/1
CE0R
CE1R
LBR OER
FT/PIPEL
0/1
1b 0b
ba
1a 0a
0a 1a
a
0b 1b b
0/1
FT/PIPER
I/O9L-I/O17L(2) I/O Control I/O0L-I/O8L(1) I/O Control
I/O9R-I/O17R(1)
I/O0R-I/O8R(1)
A15L A0L CLKL Counter/ Address Reg. MEMORY ARRAY Counter/ Address Reg.
A15R A0R CLKR
ADSL CNTENL CNTRSTL
ADSR CNTENR CNTRSTR
4856 drw 01
NOTE: 1. I/O0X - I/O7X for IDT70V9289. 2. I/O8X - I/O15X for IDT70V9289.
APRIL 2003
1
(c)2003 Integrated Device Technology, Inc. DSC-4856/3
IDT70V9389/289L High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
The IDT70V9389/289 is a high-speed 64K x 18 (64K x 16) bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times.
Description:
With an input data register, the IDT70V9389/289 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 500mW of power.
Pin Configuration(1,2,3)
03/28/03
1 28 1 27 1 26 1 25 1 24 1 23 1 22 1 21 1 20 1 19 1 18 1 17 1 16 1 15 1 14 1 13 1 12 1 11 1 10 1 09 1 08 1 07 1 06 1 05 1 04 1 03
A 10R A 11R A 12R A 13R A 14R A 15R NC NC LB R UB R CE 0R CE 1R CNTRS TR V DD V SS R/WR O ER FT/PIP ER V SS I/O 17R I/O 16R I/O 15R I/O 14R V DD V DD I/O 13R
NC NC NC NC A9R A8R A7R A6R A5R A4R A3R A2R A1R A0R NC CNTENR CLKR ADSR
VSS VDD
ADSL CLKL CNTENL NC A0L A1L A2L A3L A4L A5L A6L A7L A8L A9L NC NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
70V9389PRF PK-128-1(4) 128-Pin TQFP Top View(5)
A10L A11L A12L A13L A14L A15L NC NC L BL UBL CE 0L CE 1L C NTRSTL VDD VSS R/WL O EL FT/PIP EL VSS I/O 17L I/O 16L I/O 15L I/O 14L VDD VSS I/O 13L
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
I/O12R I/O11R
VSS
NC I/O10R I/O9R I/O8R I/O7R
VDD
I/O6R I/O5R I/O4R
VSS
I/O3R
VDD
I/O2R I/O1R I/O0R
VSS VDD
I/O0L I/O1L
VSS
I/O2L I/O3L
VSS
I/O4L I/O5L I/O6L I/O7L
VDD
I/O8L I/O9L I/O10L NC
VDD
I/O11L I/O12L
4856 drw 02
NOTES: 1. All VDD pins must be connected to power supply. 2. All VSS pins must be connected to ground. 3. Package body is approximately 14mm x 20mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking.
6.42 2
IDT70V9389/289L High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
Pin Configurations(1,2,3)(con't.)
INDEX
A9L A10L A11L A12L A13L A14L A15L LBL UBL CE0L CE1L CNTRSTL R/WL OEL VDD FT/PIPEL I/O17L I/O16L VSS I/O15L I/O14L I/O13L I/O12L I/O11L I/O10L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 2 74 3 73 4 72 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
A8L A7L A6L A5L A4L A3L A2L A1L A0L CNTENL CLKL ADSL VSS VSS ADSR CLKR CNTENR A0R A1R A2R A3R A4R A5R A6R A7R
03/28/03
70V9389PF PN100-1(4) 100-Pin TQFP Top View (5)
51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A8R A9R A10R A11R A12R A13R A14R A15R LBR UBR CE0R CE1R CNTRSTR R/WR VSS OER FT/PIPER I/O17R VSS I/O16R I/O15R I/O14R I/O13R I/O12R I/O11R
4856 drw 02a
,
NOTES: 1. All VDD pins must be connected to power supply. 2. All VSS pins must be connected to ground. 3. Package body is approximately 14mm x 14mm x 1.4mm 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking.
I/O9L I/O8L VDD I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L VSS I/O1L I/O0L VSS I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R VDD I/O7R I/O8R I/O9R I/O10R
6.42 3
IDT70V9389/289L High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
Pin Configurations(1,2,3)(con't.)
A 10R A 11R A 12R A 13R A 14R A 15R NC NC LB R UB R CE 0R CE 1R CNTRS TR V DD V SS R/WR O ER FT/PIP ER V SS I/O 15R I/O 14R I/O 13R I/O 12R V DD V DD I/O 11R 12 8 12 7 12 6 12 5 12 4 12 3 12 2 12 1 12 0 11 9 11 8 11 7 11 6 11 5 11 4 11 3 11 2 11 1 11 0 10 9 10 8 10 7 10 6 10 5 10 4 10 3
03/28/03
NC NC NC NC A9R A8R A7R A6R A5R A4R A3R A2R A1R A0R NC CNTENR CLKR ADSR
VSS VDD
ADSL CLKL CNTENL NC A0L A1L A2L A3L A4L A5L A6L A7L A8L A9L NC NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
70V9289PRF PK-128-1(4) 128-Pin TQFP Top View(5)
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
I/O10R I/O9R
VSS
NC I/O8R NC NC I/O7R
VDD
I/O6R I/O5R I/O4R
VSS
I/O3R
VDD
I/O2R I/O1R I/O0R
VSS VDD
I/O0L I/O1L
VSS
I/O2L I/O3L
VSS
I/O4L I/O5L I/O6L I/O7L
VDD
NC NC I/O8L NC
VDD
I/O9L I/O10L
4856 drw 02b
NOTES: 1. All VDD pins must be connected to power supply. 2. All VSS pins must be connected to ground. 3. Package body is approximately 14mm x 20mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking.
A 10L A 11L A 12L A 13L A 14L A 15L NC NC LBL UBL CE0L CE1L CNTRS TL VDD VSS R/WL O EL FT/PIPEL VSS I/O 15L I/O 14L I/O 13L I/O 12L VDD VSS I/O 11L
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
6.42 4
IDT70V9389/289L High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
Pin Configurations(1,2,3)(con't.)
Index
A9L A10L A11L A12L A13L A14L A15L NC NC LBL UBL CE0L CE1L CNTRSTL VDD R/WL OEL FT/PIPEL VSS I/O15L I/O14L I/O13L I/O12L I/O11L I/O10L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 2 74 3 73 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
A8L A7L A6L A5L A4L A3L A2L A1L A0L CNTENL CLKL ADSL VSS ADSR CLKR CNTENR A0R A1R A2R A3R A4R A5R A6R A7R A8R
03/28/03
IDT70V9289PF PN100-1(4) 100-Pin TQFP Top View(5)
51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A9R A10R A11R A12R A13R A14R A15R NC NC LBR UBR CE0R CE1R . CNTRSTR VSS R/WR OER FT/PIPER VSS I/O15R I/O14R I/O13R I/O12R I/O11R I/O10R
4856 drw 02c
NOTES: 1. All VDD pins must be connected to power supply. 2. All VSS pins must be connected to ground. 3. Package body is approximately 14mm x 14mm x 1.4mm 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking.
I/O9L I/O8L VDD I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L VSS I/OIL I/O0L VSS I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R VDD I/O7R I/O8R I/O9R NC
6.42 5
IDT70V9389/289L High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
Pin Names
Left Port CE0L, CE1L R/WL OEL A0L - A15L I/O0L - I/O17L CLKL UBL LBL ADSL CNTENL CNTRSTL FT/PIPEL
(1)
Right Port CE0R, CE1R R/WR OER A0R - A15R I/O0R - I/O17R CLKR UBR LBR ADSR CNTENR CNTRSTR FT/PIPER VDD VSS
(1)
Names Chip Enables (3) Read/Write Enable Output Enable Address Data Input/Output Clock Upper Byte Select(2) Lower Byte Select(2) Address Strobe Enable Counter Enable Counter Reset Flow-Through / Pipeline Power (3.3V) Ground (0V)
4856 tbl 01
NOTE: 1. I/O0X - I/O15X for IDT70V9289. 2. LB and UB are single buffered regardless of state of FT/PIPE. 3. CEo and CE1 are single buffered when FT/PIPE = VIL, CEo and CE1 are double buffered when FT/PIPE = VIH, i.e. the signals take two cycles to deselect.
Truth Table I--Read/Write and Enable Control(1,2,3)
OE X X X X X X L L L H CLK X CE0(5) H X L L L L L L L L CE1(5) X L H H H H H H H H UB(4) X X H L H L L H L L LB(4) X X H H L L H L L L R/W X X X L L L H H H X Upper Byte I/O9-17(6) High-Z High-Z High-Z DIN High-Z DATAIN DATAOUT High-Z DATAOUT High-Z Lower Byte I/O0-8(7) High-Z High-Z High-Z High-Z DATAIN DATAIN High-Z DATAOUT DATAOUT High-Z Deselected-Power Down Deselected-Power Down Both Bytes Deselected Write to Upper Byte Only Write to Lower Byte Only Write to Both Bytes Read Upper Byte Only Read Lower Byte Only Read Both Bytes Outputs Disabled
4856 tbl 02
MODE
NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. ADS, CNTEN, CNTRST = X. 3. OE is an asynchronous input signal. 4. LB and UB are single buffered regardless of state of FT/PIPE. 5. CEo and CE1 are single buffered when FT/PIPE = VIL. CEo and CE1 are double buffered when FT/PIPE = VIH, i.e. the signals take two cycles to deselect. 6. I/O8 - I/O15 for IDT70V9289. 7. I/O0 - I/O7 for IDT70V9289.
6.42 6
IDT70V9389/289L High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
Truth Table II--Address Counter Control(1,2)
External Address X An An X Previous Internal Address X X Ap Ap Internal Address Used 0 An Ap Ap + 1 MODE CLK ADS X L(4) H H CNTEN X X H L(5) CNTRST L(4) H H H I/O(3) DI/O(0) DI/O(n) DI/O(p) DI/O(p+1) Counter Reset to Address 0 External Address Loaded into Counter External Address Blocked--Counter disabled (Ap reused) Counter Enabled--Internal Address generation
4856 tbl 03
NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. CE0, LB, UB, and OE = VIL; CE1 and R/W = VIH. 3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle. 4. ADS and CNTRST are independent of all other signals including CE0, CE1, UB and LB. 5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0, CE1, UB and LB.
Recommended Operating Temperature and Supply Voltage(1)
Grade Commercial Industrial Ambient Temperature(2) 0OC to +70OC -40OC to +85OC GND 0V 0V VDD 3.3V + 0.3V 3.3V + 0.3V
4856 tbl 04
Recommended DC Operating Conditions
Symbol VDD VSS VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 3.0 0 2.0 -0.3
(1)
Typ. 3.3 0
____ ____
Max. 3.6 0 VDD+0.3V 0.8
(2)
Unit V V V V
4856 tbl 05
NOTES: 1. This is the parameter TA. This is the "instant on" case temperature.
NOTES: 1. VIL > -1.5V for pulse width less than 10 ns. 2. VTERM must not exceed VDD +0.3V.
Absolute Maximum Ratings(1)
Symbol VTERM(2) Rating Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Junction Temperature DC Output Current Commercial & Industrial -0.5 to +4.6 Unit V
Capacitance(1)
Symbol CIN
(TA = +25C, f = 1.0MHZ)
Parameter Input Capacitance
(3)
Conditions(2) VIN = 3dV VOUT = 3dV
Max. 9 10
Unit pF pF
4856 tbl 07
TBIAS(3) TSTG TJN IOUT
-55 to +125 -65 to +150 +150 50
o
C C C
COUT
Output Capacitance
o
o
mA
4856 tbl 06
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VDD +0.3V for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > VDD + 0.3V. 3. Ambient Temperature Under DC Bias. No AC Conditions. Chip Deselected.
NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V. 3. COUT also references CI/O.
6.42 7
IDT70V9389/289L High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 3.3V 0.3V)
70V9389/289L Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current(1) Output Leakage Current Output Low Voltage Output High Voltage VDD = 3.6V, VIN = 0V to VDD CE = VIH or CE1 = VIL, VOUT = 0V to VDD IOL = +4mA IOH = -4mA Test Conditions Min.
___ ___ ___
Max. 5 5 0.4
___
Unit A A V V
4856 tbl 08
2.4
NOTE: 1. At VDD < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating Temperature Supply Voltage Range(3) (VDD = 3.3V 0.3V)
70V9389/289L6 Com'l Only Symbol IDD Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports - CMOS Level Inputs) Full Standby Current (One Port - CMOS Level Inputs) Test Condition CEL and CER= VIL, Outputs Disabled, f = fMAX(1) CEL = CER = VIH f = fMAX(1) Version COM'L IND COM'L IND L L L L L L L L L L
____ ____ ____ ____
70V9389/289L7 Com'l Only Typ.(4) 200
____
70V9389/289L9 Com'l & Ind Typ.(4) 175 180 40 50 110 110 0.4 0.4 100 100 Max. 230 240 65 70 145 155 2 2 140 155
70V9389/289L12 Com'l Only Typ.(4) 150
____
Typ.(4) 220
____
Max. 280
____
Max. 250
____
Max. 200
____
Unit mA
ISB1
60
____
85
____
50
____
75
____
30
____
50
____
mA
ISB2
COM'L CE"A" = VIL and CE"B" = VIH(5) Active Port Outputs Disabled, IND f=fMAX(1) Both Ports CEL and CER > VDD - 0.2V, VIN > VDD - 0.2V or VIN < 0.2V, f = 0(2) CE"A" < 0.2V and CE"B" > VDD - 0.2V(5) VIN > VDD - 0.2V or VIN < 0.2V, Active Port, Outputs Disabled, f = fMAX(1) COM'L IND COM'L IND
145
____
185
____
130
____
165
____
95
____
130
____
mA
ISB3
0.4
____
2
____
0.4
____
2
____
0.4
____
2
____
mA
ISB4
145
180
130
160
90
____
125
____
mA
NOTES: 1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of GND to 3V. 2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. VDD = 3.3V, TA = 25C for Typ, and are not production tested. IDD DC(f=0) = 90mA (Typ). 5. CEX = VIL means CE0X = VIL and CE1X = VIH CEX = VIH means CE0X = VIH or CE1X = VIL CEX < 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V CEX > VDD - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V "X" represents "L" for left port or "R" for right port.
4856 tbl 09
6.42 8
IDT70V9389/289L High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns Max. 1.5V 1.5V Figures 1, 2, and 3
4856 tbl 10
3.3V
3.3V
590 DATAOUT 435 30pF DATAOUT 435
590
5pF*
4856 drw 03
4856 drw 04
Figure 1. AC Output Test load.
Figure 2. Output Test Load (For tCKLZ, tCKHZ, tOLZ, and tOHZ). *Including scope and jig.
8 7 6 5 tCD1, tCD2 (Typical, ns) 4 3 2 1 0 -1
- 10pF is the I/O capacitance of this device, and 30pF is the AC Test Load Capacitance
20 40 60 80 100 120 140 160 180 200 Capacitance (pF)
4856 drw 05
.
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6.42 9
IDT70V9389/289L High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing)(3) (VDD = 3.3V 0.3V, TA = 0C to +70C)
70V9389/289L6 Com'l Only Symbol tCYC1 tCYC2 tCH1 tCL1 tCH2 tCL2 tR tF tSA tHA tSC tHC tSB tHB tSW tHW tSD tHD tSAD tHAD tSCN tHCN tSRST tHRST tOE tOLZ tOHZ tCD1 tCD2 tDC tCKHZ tCKLZ Clock Cycle Time (Flow-Through) Clock Cycle Time (Pipelined)(2) Clock High Time (Flow-Through) Clock Low Time (Flow-Through) Clock High Time (Pipelined)(2) Clock Low Time (Pipelined) Clock Rise Time Clock Fall Time Address Setup Time Address Hold Time Chip Enable Setup Time Chip Enable Hold Time Byte Enable Setup Time Byte Enable Hold Time R/W Setup Time R/W Hold Time Input Data Setup Time Input Data Hold Time ADS Setup Time ADS Hold Time CNTEN Setup Time CNTEN Hold Time CNTRST Setup Time CNTRST Hold Time Output Enable to Data Valid Output Enable to Output Low-Z(1) Output Enable to Output High-Z
(1) (2) (2)
70V9389/289L7 Com'l Only Min. 22 12 7.5 7.5 5 5
____ ____
70V9389/289L9 Com'l & Ind Min. 25 15 12 12 6 6
____ ____
70V9389/289L12 Com'l Only Min. 30 20 12 12 8 8
____ ____
Parameter
(2)
Min. 19 10 6.5 6.5 4 4
____ ____
Max.
____ ____ ____ ____ ____ ____
Max.
____ ____ ____ ____ ____ ____
Max.
____ ____ ____ ____ ____ ____
Max.
____ ____ ____ ____ ____ ____
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
(2)
3 3
____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____
3 3
____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____
3 3
____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____
3 3
____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____
3.5 0 3.5 0 3.5 0 3.5 0 3.5 0 3.5 0 3.5 0 3.5 0
____
4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0
____
4 1 4 1 4 1 4 1 4 1 4 1 4 1 4 1
____
4 1 4 1 4 1 4 1 4 1 4 1 4 1 4 1
____
6.5
____
7.5
____
9
____
12
____
2 1
____ ____
2 1
____ ____
2 1
____ ____
2 1
____ ____
7 15 6.5
____
7 18 7.5
____
7 20 9
____
7 25 12
____
Clock to Data Valid (Flow-Through)(2) Clock to Data Valid (Pipelined)
(2)
Data Output Hold After Clock High Clock High to Output High-Z
(1)
2 2 2
2 2 2
2 2 2
2 2 2
9
____
9
____
9
____
9
____
Clock High to Output Low-Z(1)
Port-to-Port Delay tCWDD tCCS Write Port Clock High to Read Data Delay Clock-to-Clock Setup Time
____ ____
24 9
____ ____
28 10
____ ____
35 15
____ ____
40 15
ns ns
4856 tbl 11
NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characterization, but is not production tested. 2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both the Left and Right ports when FT/PIPE = VIH. Flow-through parameters (tCYC1, tCD1) apply when FT/PIPE = VIL for that port. 3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPER, and FT/PIPEL.
6.42 10
IDT70V9389/289L High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
Timing Waveform of Read Cycle for Flow-Through Output (FT/PIPE"X" = VIL)(3,7)
tCYC1 tCH1 CLK
CE0
tCL1
tSC CE1 tSB
UB, LB
tHC
tSC
tHC
tHB tSB tHB
R/W
tSW tHW tSA tHA An + 1 tCD1 tDC Qn tCKLZ
(1)
ADDRESS
(5)
An
An + 2
An + 3 tCKHZ (1)
DATAOUT
Qn + 1
(1)
Qn + 2 tOLZ (1) tDC
tOHZ
OE
(2)
tOE
.. 4856 drw 06
Timing Waveform of Read Cycle for Pipelined Operation (FT/PIPE"X" = VIH)(3,7)
tCYC2 tCH2 CLK
CE0
tCL2
tSC CE1 tSB
UB, LB
tHC
tSC
(4)
tHC
tHB
tSB
(6)
tHB
R/W
tSW tSA
tHW tHA An + 1 (1 Latency) tCD2 Qn tCKLZ
(1)
ADDRESS
(5)
An
An + 2 tDC Qn + 1
An + 3
DATAOUT
Qn + 2 tOLZ (1)
(6)
tOHZ(1)
OE
(2)
tOE
4856 drw 07 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 3. ADS = VIL, CNTEN and CNTRST = VIH. 4. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, UB = VIH, or LB = VIH following the next rising edge of the clock. Refer to Truth Table 1. 5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 6. If UB or LB was HIGH, then the Upper Byte and/or Lower Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state). 7. "X' here denotes Left or Right port. The diagram is with respect to that port.
6.42 11
IDT70V9389/289L High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
Timing Waveform of a Bank Select Pipelined Read(1,2)
tCH2 CLK tSA ADDRESS(B1) tSC
CE0(B1)
tCYC2 tCL2
tHA A0 tHC tSC tCD2 tHC tCD2 Q0 tDC tCKHZ(3) Q1 tDC A3 A4 tCD2 Q3 tCKLZ
(3)
A1
A2
A3
A4
A5
A6
DATAOUT(B1) tSA ADDRESS(B2) tHA A0 A1
tCKHZ (3) A5 A6
A2
tSC tHC
CE0(B2)
tSC
tHC tCD2 tCKHZ Q2
(3)
tCD2 tCKLZ (3)
4856 drw 08
DATAOUT(B2) tCKLZ(3)
Q4
Timing Waveform with Port-to-Port Flow-Through Read(4,5,7)
CLK "A" tSW tHW R/W "A" tSA ADDRESS "A" tHA
NO MATCH
MATCH
tSD DATAIN "A"
VALID
tHD
tCCS CLK "B"
(6)
tCD1 R/W "B" tSW tSA ADDRESS "B" tHW tHA
NO MATCH
MATCH
tCWDD DATAOUT "B" tDC
(6)
tCD1
VALID VALID
tDC
4856 drw 09
NOTES: 1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT70V9389 or IDT70V9289 for this waveform, and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation. 2. UB, LB, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH. 3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 4. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to. 6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case. 7. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite from Port "A".
6.42 12
IDT70V9389/289L High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3)
tCYC2 tCH2 tCL2 CLK
CE0
tSC CE1 tSB
UB, LB
tHC
tHB
tSW tHW R/W tSW tHW
ADDRESS
(4)
An tSA tHA
An +1
An + 2
An + 2 tSD tHD Dn + 2
An + 3
An + 4
DATAIN
(2)
tCD2 Qn READ
tCKHZ
(1)
tCKLZ
(1)
tCD2 Qn + 3
DATAOUT
NOP
(5)
WRITE
READ
4856 drw 10
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(3)
tCH2 CLK
CE0
tCYC2 tCL2
tSC tHC CE1 tSB
UB, LB
tHB
tSW tHW R/W tSW tHW
ADDRESS DATAIN
(4)
An tSA tHA
An +1
An + 2 tSD tHD
An + 3
An + 4
An + 5
(2)
tCD2 Qn tOHZ(1)
Dn + 2
Dn + 3
tCKLZ(1)
tCD2 Qn + 4
DATAOUT
OE
READ
WRITE
READ
4856 drw 11
NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation". 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42 13
IDT70V9389/289L High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(3)
tCH1 CLK tCYC1 tCL1
CE0
tSC CE1 tSB
UB, LB
tHC
tHB
tSW tHW R/W tSW tHW
ADDRESS
(4)
tSA DATAIN
(2)
An tHA
An +1
An + 2
An + 2 tSD tHD Dn + 2
An + 3
An + 4
tCD1 Qn tDC READ
tCD1 Qn + 1 tCKHZ (5) NOP
(1)
tCD1
tCD1 Qn + 3 tDC READ
DATAOUT
tCKLZ WRITE
(1)
4856 drw 12
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(3)
tCYC1 tCH1 tCL1 CLK
CE0
tSC CE1 tSB
UB, LB
tHC
tHB
tSW tHW R/W ADDRESS
(4)
tSW tHW An tSA tHA An +1 An + 2 tSD tHD Dn + 2
(2)
An + 3
An + 4
An + 5
DATAIN tCD1 Qn tOHZ
OE
(1)
Dn + 3
tDC
tOE tCD1
(1)
tCD1 Qn + 4 tDC
DATAOUT
tCKLZ
READ
WRITE
READ
4856 drw 13
NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation". 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42 14
IDT70V9389/289L High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
Timing Waveform of Pipelined Read with Address Counter Advance(1)
tCH2 CLK tSA ADDRESS An tSAD tHAD
ADS
tCYC2 tCL2
tHA
tSAD tHAD
CNTEN
tSCN tHCN tCD2
DATAOUT
Qx - 1(2)
Qx tDC
Qn
Qn + 1
Qn + 2(2)
Qn + 3
READ EXTERNAL ADDRESS
READ WITH COUNTER
COUNTER HOLD
READ WITH COUNTER
4856 drw 14
Timing Waveform of Flow-Through Read with Address Counter Advance(1)
tCH1 CLK tSA ADDRESS tHA tCYC1 tCL1
An tSAD tHAD
ADS
tSAD tHAD tSCN tHCN
CNTEN
tCD1 DATAOUT Qx(2) tDC READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD READ WITH COUNTER
4856 drw 15
Qn
Qn + 1
Qn + 2
Qn + 3(2)
Qn + 4
NOTES: 1. CE0, OE, UB, and LB = VIL; CE1, R/W, and CNTRST = VIH. 2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data output remains constant for subsequent clocks.
6.42 15
IDT70V9389/289L High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance (Flow-Through or Pipelined Outputs)(1)
tCH2 CLK tSA ADDRESS tHA tCYC2 tCL2
An
INTERNAL(3) ADDRESS tSAD tHAD
ADS
An(7)
An + 1
An + 2
An + 3
An + 4
CNTEN(7)
tSD tHD DATAIN Dn WRITE EXTERNAL ADDRESS Dn + 1 Dn + 1 Dn + 2 Dn + 3 Dn + 4
WRITE WRITE WITH COUNTER COUNTER HOLD
WRITE WITH COUNTER
4856 drw 16
Timing Waveform of Counter Reset (Pipelined Outputs)(2)
tCH2 CLK tSA tHA ADDRESS(4) INTERNAL(3) ADDRESS R/W
ADS CNTEN
tCYC2 tCL2
An Ax (6) tSW tHW
An + 1
An + 2
0
1
An
An + 1
tSAD tHAD tSCN tHCN tSRST tHRST
CNTRST
tSD
tHD D0 Q0 Q1 READ ADDRESS n READ ADDRESS n+1 Qn
DATAIN DATAOUT(5) COUNTER RESET
(6)
WRITE ADDRESS 0
READ ADDRESS 0
READ ADDRESS 1
NOTES: 4856 drw 17 1. CE0, UB, LB, and R/W = VIL; CE1 and CNTRST = VIH. 2. CE0, UB, LB = VIL; CE1 = VIH. 3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH. 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle. ADDR0 will be accessed. Extra cycles are shown here simply for clarification. 7. CNTEN = VIL advances Internal Address from `An' to `An +1'. The transition shown indicates the time required for the counter to advance. The `An +1' Address is written to during this cycle.
6.42 16
IDT70V9389/289L High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
Functional Description
The IDT70V9389/289 provides a true synchronous Dual-Port Static RAM interface. Registered inputs provide minimal set-up and hold times on address, data, and all critical control inputs. All internal registers are clocked on the rising edge of the clock signal, however, the self-timed internal write pulse is independent of the LOW to HIGH transition of the clock signal. An asynchronous output enable is provided to ease asynchronous bus interfacing. Counter enable inputs are also provided to staff the operation of the address counters for fast interleaved memory applications. CE0 = VIH or CE1 = VIL for one clock cycle will power down the internal circuitry to reduce static power consumption. Multiple chip enables allow easier banking of multiple IDT70V9389/289's for depth expansion configurations. When the Pipelined output mode is enabled, two cycles are required with CE0 = VIL and CE1 = VIH to re-activate the outputs.
Depth and Width Expansion
The IDT70V9389/289 features dual chip enables (refer to Truth Table I) in order to facilitate rapid and simple depth expansion with no requirements for external logic. Figure 4 illustrates how to control the varioius chip enables in order to expand two devices in depth. The IDT70V9389/289 can also be used in applications requiring expanded width, as indicated in Figure 4. Since the banks are allocated at the discretion of the user, the external controller can be set up to drive the input signals for the various devices as required to allow for 36/32-bit or wider applications.
A16
IDT70V9389/289 CE0 IDT70V9389/289 CE0
CE1 Control Inputs
VDD Control Inputs
CE1
VDD
IDT70V9389/289 CE1
IDT70V9389/289 CE1
CE0 Control Inputs Control Inputs
CE0 CNTRST CLK ADS CNTEN R/W LB, UB OE
4856 drw 18
Figure 4. Depth and Width Expansion with IDT70V9389/289
6.42 17
IDT70V9389/289L High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
Ordering Information
IDT XXXXX Device Type A Power 99 Speed A Package A Process/ Temperature Range Blank I (1) PRF PF
Commercial (0C to +70C) Industrial (-40C to +85C) 128-pin TQFP (PK128-1) 100-pin TQFP (PN100-1)
6 7 9 12
Commercial Only Commercial Only Commercial & Industrial Commercial Only
Speed in nanoseconds
L
Low Power
70V9389 70V9289
1152K (64K x 18-Bit) Synchronous Dual-Port RAM 1024K (64K x 16-Bit) Synchronous Dual-Port RAM
4856 drw 19
NOTE: 1. Industrial temperature range is available. For specific speeds, packages and powers contact your sales office.
IDT Clock Solution for IDT70V9389/289 Dual-Port
Dual-Port I/O Specitications IDT Dual-Port Part Number Voltage I/O Input Capacitance Dual-Port Clock Specifications Input Duty Cycle Requirement Maximum Frequency Jitter Tolerance IDT PLL Clock Devices IDT2305 IDT2308 IDT2309 IDT Non-PLL Clock Devices FCT3805 FCT3805D/E FCT3807 FCT3807D/E
4856 tbl12
70V9389/289
3.3
LVTTL
9pF
40%
100
150ps
6.42 18
IDT70V9389/289L High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
Datasheet Document History
9/30/99: 11/12/99: 06/23/00: Initial Public Release Replaced IDT logo Page 3 Changed information in Truth Table II Page 4 Increased storage temperature parameters Clarified TA parameter Page 5 DC Electrical parameters-changed wording from "open" to "disabled" Changed 200mV to 0mV in notes Consolidated multiple devices into one datasheet Changed naming conventions from VCC to VDD and from GND to Vss Page 3 & 5 Added PN-100 TQFP pin configuration Page 1 & 18 Added PN-100 TQFP availability and ordering information Page 2 - 5 Added date revision to pin configurations Page 7 Added junction temperature to Absolute Maximum Ratings Table Added Ambient Temperature footnote Page 8, 10 & 18 Added 6ns speed grade Page 8 Added updated DC power numbers to the DC Electrical Characteristics Table Page 10 Added 6ns speed AC timing numbers and changed tOE to be equal to tCD2 in the AC Electrical Characteristics Table Page 18 Added IDT Clock Solution Table Page 1& 19 Removed "Preliminary" status
04/09/03:
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
6.42 19
for Tech Support: 831-754-4613 DualPortHelp@idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.

▲Up To Search▲

Price & Availability of IDT70V9289L

	To Download IDT70V9289L Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .