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Integrated Circuit Systems, Inc.
ICS83905
LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER
FEATURES
* 6 LVCMOS / LVTTL outputs * Outputs able to drive 12 series terminated lines * Crystal oscillator interface * Crystal input frequency range: 10MHz to 40MHz * Output skew: 80ps (maximum) * RMS phase jitter @ 25MHz, (100Hz - 1MHz): 0.26ps (typical) (VDD = VDDO = 2.5V) Phase noise: Offset Noise Power 100Hz .............. -129.7 dBc/Hz 1kHz .............. -144.4 dBc/Hz 10kHz .............. -147.3 dBc/Hz 100kHz .............. -157.3 dBc/Hz * 5V tolerant enable inputs * Synchronous output enables * Operating power supply modes: Full 3.3V, 2.5V and 1.8V, mixed 3.3V core/2.5V output operating supply, mixed 3.3V core/1.8V output operating supply, mixed 2.5V core/1.8V output operating supply
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GENERAL DESCRIPTION
The ICS83905 is a low skew, 1-to-6 LVCMOS / LVTTL Fanout Buffer and a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions from ICS. The low impedance LVCMOS/ LVTTL outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 6 to 12 by utilizing the ability of the outputs to drive two series terminated lines.
ICS
The ICS83905 is characterized at full 3.3V, 2.5V, and 1.8V, mixed 3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating supply mode. Guaranteed output and part-to-part skew characteristics along with the 1.8V output capabilities makes the ICS83905 ideal for high performance, single ended applications that also require a limited output voltage.
PIN ASSIGNMENTS
XTAL_OUT ENABLE 2 ENABLE 1 XTAL_IN
* 0C to 70C ambient operating temperature * Lead-Free package fully RoHS compliant
BCLK5 VDDO BCLK4 GND GND
ICS83905
20-Lead VFQFN
4mm x 4mm x 0.9mm body package
GND GND BCLK0 VDDO BCLK1
1 2 3 4 5
20 19 18 17 16 15 14 13 12 11 6
GND
K Package Top View
7
GND
8
BCLK2
9 10
VDD BCLK3
BLOCK DIAGRAM
BCLK0
XTAL_OUT ENABLE 2 GND BCLK0 VDDo BCLK1 GND BCLK2
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
XTAL_IN ENABLE 1 BCLK5 VDDO BCLK4 GND BCLK3 VDD
BCLK1 XTAL_IN BCLK2
XTAL_OUT
ICS83905
16-Lead SOIC 3.9mm x 9.9mm x 1.38mm body package M Pacakge Top View
ENABLE 1
BCLK3
BCLK4
16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm body package G Pacakge Top View
83905AM
SYNCHRONIZE
BCLK5
ENABLE 2
SYNCHRONIZE
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REV. B MAY 16, 2005
Integrated Circuit Systems, Inc.
ICS83905
LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER
Type Description Cr ystal oscillator interface. XTAL_OUT is the output. Cr ystal oscillator interface. XTAL_IN is the input. Clock enable. LVCMOS / LVTTL interface levels. See Table 3. Clock outputs. LVCMOS / LVTTL interface levels. Power supply ground. Core supply pin. Output supply pin. No connect.
TABLE 1. PIN DESCRIPTIONS
Name XTAL_OUT XTAL_IN ENABLE 1, ENABLE 2 BCLK0, BCLK1, BCLK2, BCLK3, BCLK4, BCLK5 GND VDD VDDO n/c Input Input Output Power Power Power Unused Output
TABLE 2. PIN CHARACTERISTICS
Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance (per output) VDDO = 3.465V VDDO = 2.625V VDDO = 2V VDDO = 3.3V 5% ROUT Output Impedance VDDO = 2.5V 5% VDDO = 1.8V 0.2V 7 7 10 Test Conditions Minimum Typical 4 19 18 16 Maximum Units pF pF pF pF
TABLE 3. CLOCK ENABLE FUNCTION TABLE
Control Inputs ENABLE 1 0 0 1 1 ENABLE 2 0 1 0 1 LOW LOW Toggling Toggling Outputs BCLK0:BCLK4 BCLK5 LOW Toggling LOW Toggling
BCLK5
BCLK0:4 ENABLE2
ENABLE1
FIGURE 1. ENABLE TIMING DIAGRAM
83905AM
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REV. B MAY 16, 2005
Integrated Circuit Systems, Inc.
ICS83905
LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 78.8C/W (0 mps) 89C/W (0 lfpm) 38.5C/W (0 mps) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Character-
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA 16 Lead SOIC package 16 Lead TSSOP package 20 Lead VFQFN package Storage Temperature, TSTG
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current ENABLE 1:2 = 00 ENABLE 1:2 = 00 Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 10 5 Units V V mA mA
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V5%, TA = 0C TO 70C
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current ENABLE 1:2 = 00 ENABLE 1:2 = 00 Test Conditions Minimum 2.375 2.375 Typical 2. 5 2.5 Maximum 2.625 2.625 8 4 Units V V mA mA
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current ENABLE 1:2 = 00 ENABLE 1:2 = 00 Test Conditions Minimum 1.6 1.6 Typical 1.8 1.8 Maximum 2.0 2.0 5 3 Units V V mA mA
TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current ENABLE 1:2 = 00 ENABLE 1:2 = 00 Test Conditions Minimum 3.135 2.375 Typical 3.3 2. 5 Maximum 3.465 2.625 10 4 Units V V mA mA
83905AM
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REV. B MAY 16, 2005
Integrated Circuit Systems, Inc.
ICS83905
LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER
Test Conditions Minimum 3.135 1.6 ENABLE 1:2 = 00 ENABLE 1:2 = 00 Typical 3.3 1.8 Maximum 3.465 2.0 10 3 Units V V mA mA
TABLE 4E. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current
TABLE 4F. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current ENABLE 1:2 = 00 ENABLE 1:2 = 00 Test Conditions Minimum 2.375 1.6 Typical 2.5 1.8 Maximum 2.625 2.0 8 3 Units V V mA mA
TABLE 4G. LVCMOS/LVTTL DC CHARACTERISTICS, TA = 0C
Symbol VIH Parameter Input High Voltage ENABLE 1, ENABLE 2
TO
70C
Minimum 2 1.7 0.65*VDD -0.3 -0.3 -0.3 2.6 2 1.8 VDDO - 0.3 0.5 0.4 0.45 0.35 Typical Maximum VDD + 0.3 VDD + 0.3 VDD + 0.3 0. 8 0. 7 0.35*VDD Units V V V V V V V V V V V V V V
Test Conditions VDD = 3.3V 5% VDD = 2.5V 5% VDD = 1.8V 0.2V VDD = 3.3V 5% VDD = 2.5V 5% VDD = 1.8V 0.2V VDDO = 3.3V 5%; NOTE 1 VDDO = 2.5V 5%; IOH = -1mA VDDO = 2.5V 5%; NOTE 1 VDDO = 1.8V 0.2V; NOTE 1 VDDO = 3.3V 5%; NOTE 1 VDDO = 2.5V 5%; IOL = 1mA VDDO = 2.5V 5%; NOTE 1 VDDO = 1.8V 0.2V; NOTE 1
VIL
Input Low Voltage
ENABLE 1, ENABLE 2
VOH
Output High Voltage
VOL
Output Low Voltage
NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement section, "Load Test Circuit" diagrams.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level
83905AM
Test Conditions
Minimum 10
Typical Fundamental
Maximum 40 50 7 1
Units MHz pF mW
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REV. B MAY 16, 2005
Integrated Circuit Systems, Inc.
ICS83905
LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER
Test Conditions Using External Crystal Minimum Typical Maximum Units 10 DC 48 40 100 52 80 25MHz @ (Integration Range: 100Hz-1MHz) 20% to 80% ENABLE 1 ENABLE 2 200 0.13 800 4 4 4 4 MH z MH z % ps ps ps cycles cycles cycles cycles
TABLE 6A. AC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol Parameter fMAX odc Output Frequency Output Duty Cycle Output Skew; NOTE 2, 4 RMS Phase Jitter (Random) Output Rise/Fall Time Output Enable Time; NOTE 3
Using External Clock Source; NOTE 1
tsk(o) tjit(O)
tR/tF
tEN tDIS
Output Disable Time; ENABLE 1 NOTE 3 ENABLE 2
All parameters measured at fMAX using a crystal input unless noted otherwise. Terminated at 50 to VDDO/2. NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 6B. AC CHARACTERISTICS, VDD = VDDO = 2.5V5%, TA = 0C TO 70C
Symbol Parameter Using External Crystal fMAX odc Output Frequency Output Duty Cycle Output Skew; NOTE 2, 5 RMS Phase Jitter (Random); NOTE 3 Output Rise/Fall Time Output Enable Time; NOTE 4 ENABLE 1 ENABLE 2 25MHz @ (Integration Range: 100Hz-1MHz) 20% to 80% 200 0.26 800 4 4 4 4 Using External Clock Source; NOTE 1 Test Conditions Minimum Typical Maximum Units 10 DC 47 40 100 53 80 MH z MH z % ps ps ps cycles cycles cycles cycles
tsk(o) tjit(O)
tR/tF
tEN tDIS
Output Disable Time; ENABLE 1 NOTE 4 ENABLE 2
All parameters measured at fMAX using a crystal input unless noted otherwise. Terminated at 50 to VDDO/2. NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Please refer to phase noise plot. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
83905AM
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5
REV. B MAY 16, 2005
Integrated Circuit Systems, Inc.
ICS83905
LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER
Test Conditions Using External Crystal Minimum Typical Maximum Units 10 DC 47 40 100 53 80 25MHz @ (Integration Range: 100Hz-1MHz) 20% to 80% ENABLE 1 ENABLE 2 200 0.27 900 4 4 4 4 MHz MHz % ps ps ps cycles cycles cycles cycles
TABLE 6C. AC CHARACTERISTICS, VDD = VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol Parameter fMAX odc Output Frequency Output Duty Cycle Output Skew; NOTE 2, 4 RMS Phase Jitter (Random) Output Rise/Fall Time Output Enable Time; NOTE 3
Using External Clock Source; NOTE 1
tsk(o) tjit(O)
tR/tF
tEN tDIS
Output Disable Time; ENABLE 1 NOTE 3 ENABLE 2
All parameters measured at fMAX using a crystal input unless noted otherwise. Terminated at 50 to VDDO/2. NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 6D. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol Parameter Using External Crystal fMAX odc Output Frequency Output Duty Cycle Output Skew; NOTE 2, 4 RMS Phase Jitter (Random) Output Rise/Fall Time Output Enable Time; NOTE 3 ENABLE 1 ENABLE 2 25MHz @ (Integration Range: 100Hz-1MHz) 20% to 80% 200 0.14 800 4 4 4 4 Using External Clock Source; NOTE 1 Test Conditions Minimum Typical Maximum Units 10 DC 48 40 100 52 80 MHz MHz % ps ps ps cycles cycles cycles cycles
tsk(o) tjit(O)
tR/tF
tEN tDIS
Output Disable Time; ENABLE 1 NOTE 3 ENABLE 2
All parameters measured at fMAX using a crystal input unless noted otherwise. Terminated at 50 to VDDO/2. NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
83905AM
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6
REV. B MAY 16, 2005
Integrated Circuit Systems, Inc.
ICS83905
LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER
Test Conditions Using External Crystal Minimum Typical Maximum Units 10 DC 48 40 100 52 80 25MHz @ (Integration Range: 100Hz-1MHz) 20% to 80% ENABLE 1 ENABLE 2 200 0.18 900 4 4 4 4 MH z MH z % ps ps ps cycles cycles cycles cycles
TABLE 6E. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol Parameter fMAX odc Output Frequency Output Duty Cycle Output Skew; NOTE 2, 4 RMS Phase Jitter (Random) Output Rise/Fall Time Output Enable Time; NOTE 3
Using External Clock Source; NOTE 1
tsk(o) tjit(O)
tR/tF
tEN tDIS
Output Disable Time; ENABLE 1 NOTE 3 ENABLE 2
All parameters measured at fMAX using a crystal input unless noted otherwise. Terminated at 50 to VDDO/2. NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 6F. AC CHARACTERISTICS, VDD = 2.5V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C
Symbol Parameter Using External Crystal fMAX odc Output Frequency Output Duty Cycle Output Skew; NOTE 2, 4 RMS Phase Jitter (Random) Output Rise/Fall Time Output Enable Time; NOTE 3 ENABLE 1 ENABLE 2 25MHz @ (Integration Range: 100Hz-1MHz) 20% to 80% 200 0.19 900 4 4 4 4 Using External Clock Source; NOTE 1 Test Conditions Minimum Typical Maximum Units 10 DC 47 40 100 53 80 MHz MHz % ps ps ps cycles cycles cycles cycles
tsk(o) tjit(O)
tR/tF
tEN tDIS
Output Disable Time; ENABLE 1 NOTE 3 ENABLE 2
All parameters measured at fMAX using a crystal input unless noted otherwise. Terminated at 50 to VDDO/2. NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
83905AM
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7
REV. B MAY 16, 2005
Integrated Circuit Systems, Inc.
ICS83905
LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER
25MHz
RMS Phase Jitter (Random) 100Hz to 1MHz = 0.26ps (typical)
TYPICAL PHASE NOISE AT 25MHZ (2.5V CORE/ 2.5V OUTPUT)
0 -10 -20 -30 -40 -50
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 10 100 1k 10k 100k 1M
Raw Phase Noise Data
TYPICAL PHASE NOISE AT 25MHZ (3.3V CORE/ 3.3V OUTPUT)
0 -10 -20 -30 -40 -50
OFFSET FREQUENCY (HZ) 25MHz
RMS Phase Jitter (Random) 100Hz to 1MHz = 0.13ps (typical)
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 10 100 1k 10k 100k 1M
Raw Phase Noise Data
83905AM
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OFFSET FREQUENCY (HZ)
REV. B MAY 16, 2005
Integrated Circuit Systems, Inc.
ICS83905
LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V5% 1.25V5%
VDD, VDDO
SCOPE
Qx
VDD, VDDO
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
-1.65V5%
-1.25V5%
3.3V
CORE/3.3V
OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
0.9V0.1V
2.05V5%
1.25V5%
VDD , VDDO
SCOPE
Qx
V DD VDDO
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
-0.9V 0.1V
-1.25V5%
1.8V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
2.40.9V
0.9V0.1V
1.6V0.025% 0.9V0.1V
VDD VDDO
SCOPE
Qx
V DD VDDO
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
-0.9V0.1V
-0.9V0.1V
3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
83905AM
2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
REV. B MAY 16, 2005
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Integrated Circuit Systems, Inc.
ICS83905
LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER
V
V
2
DD
DDO
Qx
BCLKx
2
t PW
t
V
DDO
PERIOD
Qy
2 tsk(o)
odc =
t PW t PERIOD
x 100%
OUTPUT SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
80% 20% tR
80% 20% tF
Clock Outputs
OUTPUT RISE/FALL TIME
83905AM
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10
REV. B MAY 16, 2005
Integrated Circuit Systems, Inc.
ICS83905
LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER APPLICATION INFORMATION
CRYSTAL INPUT INTERFACE
Figure 1A shows an example of ICS83905 crystal interface with a parallel resonant crystal. The frequency accuracy can be fine tuned by adjusting the C1 and C2 values. For a parallel crystal with loading capacitance CL = 18pF, we suggest C1 = 15pF and C2 = 15pF to start with. These values may be slightly fine tuned further to optimize the frequency accuracy for different board layouts. Slightly increasing the C1 and C2 values will slightly reduce the frequency. Slightly decreasing the C1 and C2 values will slightly increase the frequency. For the oscillator circuit below, R1 can be used, but is not required. For new designs, it is recommended that R1 not be used.
XTAL_IN C1 15p X1 18pF Parallel Cry stal 0 XTAL_OUT C2 15p R1 (optional)
FIGURE 1. CRYSTAL OSCILLATOR INTERFACE
83905AM
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REV. B MAY 16, 2005
Integrated Circuit Systems, Inc.
ICS83905
LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER
accurate, but minor adjustments might be required. For the LVCMOS output drivers, two termination examples are shown in the schematic. For additional termination, examples are shown in the LVCMOS Termination Application Note.
LAYOUT GUIDELINE
Figure 2 shows an example of ICS83905 application schematic. In this example, the device is operated at VDD = 3.3V and VDDO = 3.3V. The decoupling capacitors should be located as close as possible to the power pins. The input is driven by an 18pF load resonant quartz crystal. The tuning capacitors (C1, C2) are fairly
VDDO = 3.3V VDD = 3.3V CL = 18 pf C2 15pf U1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 C1 15pF R2 31 Zo = 50 Ohm
LVCMOS
ENABLE 2 VDDO
XTAL_OUT ENABLE 2 GND BCLK0 VDDO BCLK1 GND BCLK2
XTAL_IN ENABLE 1 BCLK5 VDDO BCLK4 GND BCLK3 VDD
ENABLE 1 VDD R3 100 Zo = 50 Ohm R4 100 LVCMOS
ICS83905
VDD C3 10uF C4 .1uF
VDDO C5 .1uF C6 .1uF
Optional Termination
Unused outputs can be left floating. There should be no trace attached to unused outputs. Device characterized and specification limits set with all outputs terminated.
FIGURE 2. Schematic of Recommended Layout
83905AM
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REV. B MAY 16, 2005
Integrated Circuit Systems, Inc.
ICS83905
LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 7A. JAVS. AIR FLOW TABLE
FOR
16 LEAD SOIC
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 78.8C/W
1
71.1C/W
2
66.2C/W
TABLE 7B.
JAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0 200
118.2C/W 81.8C/W
500
106.8C/W 78.1C/W
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards
137.1C/W 89.0C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 7C. JAVS. AIR FLOW TABLE
FOR
20 LEAD VFQFN
JA by Velocity (Meters per Second)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 141.7C/W 38.5C/W
1
126C/W 35C/W
2.5
116.9C/W 33.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83905 is: 339 Pin compatible to MPC905
83905AM
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REV. B MAY 16, 2005
Integrated Circuit Systems, Inc.
ICS83905
LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER
16 LEAD SOIC PACKAGE OUTLINE - G SUFFIX
FOR
PACKAGE OUTLINE - M SUFFIX
FOR
16 LEAD TSSOP
TABLE 8A. PACKAGE DIMENSIONS
SYMBOL N A A1 B C D E e H h L 5.80 0.2 5 0.40 0 1.35 0.10 0.33 0.19 9.80 3.8 0 MINIMUM
FOR
16 LEAD SOIC
MAXIMUM
TABLE 8B. PACKAGE DIMENSIONS
SYMBOL N Minimum
FOR
TSSOP
Maximum
Millimeters
Millimeters
16 1.75 0.25 0.51 0.25 10.00 4.00 1.27 BASIC 6.20 0.50 1.27 8
16 -0.05 0.80 0.19 0.09 4.90 6.40 BASIC 4.30 0.65 BASIC 0.45 0 -0.75 8 0.10 4.50 1.20 0.15 1.05 0.30 0.20 5.10
A A1 A2 b c D E E1 e L aaa
Reference Document: JEDEC Publication 95, MS-012
Reference Document: JEDEC Publication 95, MO-153
83905AM
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REV. B MAY 16, 2005
Integrated Circuit Systems, Inc.
ICS83905
LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER
20 LEAD VFQFN
PACKAGE OUTLINE - K SUFFIX
FOR
TABLE 8C. PACKAGE DIMENSIONS
FOR
20 LEAD VFQFN
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A3 b e ND NE D D2 E E2 L 0.75 0.35 0.75 4.0 2.80 0.75 0.18 0.50 BASIC 5 5 4.0 2.80 0.80 0 0.25 Reference 0.30 MINIMUM 20 1. 0 0.05 MAXIMUM
Reference Document: JEDEC Publication 95, MO-220
83905AM
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15
REV. B MAY 16, 2005
Integrated Circuit Systems, Inc.
ICS83905
LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER
Marking 83905AM 83905AM 83905AML 83905AML 83905AG 83905AG 83905AGL 83905AGL 83905A 83905A Package 16 Lead SOIC 16 Lead SOIC 16 Lead "Lead-Free" SOIC 16 Lead "Lead-Free" SOIC 16 Lead TSSOP 16 Lead TSSOP 16 Lead "Lead-Free" TSSOP 16 Lead "Lead-Free" TSSOP 20 Lead VFQFN 20 Lead VFQFN Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel tube 2500 tape & reel tube 2500 tape & reel tube 2500 tape & reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS83905AM ICS83905AMT ICS83905AMLF ICS83905AMLFT ICS83905AG ICS83905AGT ICS83905AGLF ICS83905AGLFT ICS83905AK ICS83905AKT
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 83905AM
http://www.icst.com/products/hiperclocks.html
16
REV. B MAY 16, 2005
Integrated Circuit Systems, Inc.
ICS83905
LOW SKEW, 1:6 CRYSTAL INTERFACE-TOLVCMOS / LVTTL FANOUT BUFFER
REVISION HISTORY SHEET
Rev A B B B
Table
Page 2 1 5-7 8 14 11 12
Description of Change Added Enable Timing Diagram. Features Section - added RMS Phase Jitter bullet. AC Characteristics Tables - added RMS Phase Jitter spec. Added Phase Noise Plot. Ordering Information Table - add TSSOP, non-LF par t number. Added Cr ystal Input Interface in Application Section. Added schematic layout.
Date 3/28/05 4/8/05 4/25/05 5/16/05
6A - 6F T9
83905AM
http://www.icst.com/products/hiperclocks.html
17
REV. B MAY 16, 2005

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