View ICS843101I-312_327107.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843101I-312
FEMTOCLOCKSTM CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
FEATURES
* One 312.5MHz nominal LVPECL output * Selectable crystal oscillator interface designed for 25MHz, 18pF parallel resonant crystal or LVCMOS/LVTTL single-ended input * Output frequency can be varied in 2% steps from nominal * VCO range: 560MHz - 690MHz * RMS phase jitter @ 312.5MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.52ps (typical) * Output supply modes Core/Output 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V * -40C to 85C ambient operating temperature * Available in both standard and lead-free RoHS-complaint packages
GENERAL DESCRIPTION
The ICS843101I-312 is a low phase-noise frequency margining synthesizer with freHiPerClockSTM quency margining capability and is a member of the HiPerClockSTM family of high performance clock solutions from ICS. In the default mode, the device nominally generates a 312.5MHz LVPECL output clock signal from a 25MHz crystal input. There is also a frequency margining mode available where the device can be programmed, using the serial interface, to vary the output frequency up or down from nominal in 2% steps. The ICS843101I-312 is provided in a 16-pin TSSOP.
IC S
BLOCK DIAGRAM
OE CLK
Pullup Pulldown
PIN ASSIGNMENT
VEE S_LOAD S_DATA Q S_CLOCK SEL nQ OE VCCA VCC 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 MODE VCCO Q nQ VEE CLK XTAL_OUT XTAL_IN
1
25MHz
/P OSC
0
XTAL_IN XTAL_OUT SEL
Phase Detector
VCO
560 - 690MHz
/N
Pulldown
/M
ICS843101I-312
16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View
S_CLOCK S_DATA S_LOAD MODE
Pulldown Pulldown Pulldown Pulldown
Serial Control
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
843101AGI-312
www.icst.com/products/hiperclocks.html
1
REV. A NOVEMBER 1, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843101I-312
FEMTOCLOCKSTM CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by an output divider prior to being sent to the LVPECL output buffer. The divider provides a 50% output duty cycle. The relationship between the crystal input frequency, the M divider, the VCO frequency and the output frequency is provided in Table 1. When changing back from frequency margining mode to nominal mode, the device will return to the default nominal configuration that will provide 312.5 MHz output frequency. Serial operation occurs when S_LOAD is HIGH. Serial data can be loaded in either the default mode or the frequency margining mode. The 6-bit shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. After shifting in the 6-bit M divider value, S_LOAD is transitioned from HIGH to LOW which latches the contents of the shift-register into the M divider control register. When S_LOAD is LOW, any transitions of S_CLOCK or S_DATA are ignored.
FUNCTIONAL DESCRIPTION
The ICS843101I-312 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A 25MHz fundamental crystal is used as the input to the on chip oscillator. The output of the oscillator is fed into the pre-divider. In frequency margining mode, the 25MHz crystal frequency is divided by 2 and a 12.5MHz reference frequency is applied to the phase detector. The VCO of the PLL operates over a range of 560MHz to 690MHz. The output of the M divider is also applied to the phase detector. The default mode for the ICS843101I-312 is 312.5MHz output frequency using a 25MHz crystal. The output frequency can be changed by placing the device into the margining mode using the mode pin and using the serial interface to program the M feedback divider. Frequency margining mode operation occurs when the MODE input is HIGH. The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for
TABLE 1. FREQUENCY MARGIN FUNCTION TABLE
XTAL (MHz) 25 25 25 25 25 25 25 25 25 25 25 Pre-Divider (P) 2 2 2 2 2 2 2 2 2 2 2 Reference Frequency (MHz) 12.5 12.5 12.5 12.5 12.5 12.5 12.5 12.5 12.5 12. 5 12. 5 Feedback Divider (M) 45 46 47 48 49 50 51 52 53 54 55 M-Data (Binary) 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 VCO (MHz) 562.5 575 587.5 600 612.5 625 637.5 650 662.5 675 687.5 Output Divider (N) 2 2 2 2 2 2 2 2 2 2 2 Output Frequency (MHz) 281.25 287.5 293.75 300 306.25 312.5 318.75 325 331.25 337.5 343.75 % Change -10.0 -8.0 -6.0 -4.0 -2.0 Nominal Mode 2.0 4.0 6.0 8.0 10.0
SERIAL LOADING
S_CLOCK S_DATA
M5 M4
t
S
M3
M2
M1
M0
t
S
t
H
S_LOAD
Time
FIGURE 1. SERIAL LOAD OPERATIONS
843101AGI-312
www.icst.com/products/hiperclocks.html
2
REV. A NOVEMBER 1, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843101I-312
FEMTOCLOCKSTM CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
Negative supply pins. Pulldown Controls the operation of the Serial input. LVCMOS/LVTTL interface levels. Shift register serial input. Data sampled on the rising edge of S_CLOCK. Pulldown LVCMOS/LVTTL interface levels. Clock in serial data present at S_DATA input into the shift register on the Pulldown rising edge of S_CLOCK. LVCMOS/LVTTL interface levels. Select pin. When HIGH, selects CLK input. Pulldown When LOW, selects XTAL inputs. LVCMOS/LVTTL interface levels. Output enable pin. Controls enabling and disabling of Q/nQ outputs. Pullup LVCMOS/LVTTL interface levels Analog supply pin. Core supply pin. Parallel resonant cr ystal interface. XTAL_OUT is the output, XTAL_IN is the input. Pulldown LVCMOS/LVTTL clock input. Differential output pair. LVPECL interface levels.
TABLE 2. PIN DESCRIPTIONS
1, 12 2 3 4 5 6 7 8 9, 10 11 13, 14 15 VEE S_LOAD S_DATA S_CLOCK SEL OE VCCA VCC XTAL_IN, XTAL_OUT CL K nQ, Q VCCO Input Input Input Input Input Power Power Input Input Ouput Power Power
Output supply pin. MODE pin. LOW = default mode. HIGH = frequency margining mode. 16 MODE Input Pulldown LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 3. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN RPULLUP Parameter Input Capacitance Input Pulldown Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
843101AGI-312
www.icst.com/products/hiperclocks.html
3
REV. A NOVEMBER 1, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843101I-312
FEMTOCLOCKSTM CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
TABLE 4A. OE CONTROL INPUT FUNCTION TABLE
Input OE 0 1 Outputs Q , nQ HiZ Enabled
TABLE 4B. SEL CONTROL INPUT FUNCTION TABLE
Input SEL 0 1 Selected Source XTAL_IN, XTAL_OUT CLK
TABLE 4C. MODE CONTROL INPUT FUNCTION TABLE
Input Mode 0 1 Condition Q, nQ Default Mode Frequency Margining Mode
TABLE 4D. SERIAL MODE FUNCTION TABLE
Inputs S_LOAD L H S_CLOCK X S_DATA X Data Serial inputs are ignored. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are latched. Conditions
L X NOTE: L = LOW H = HIGH X = Don't care = Rising edge transition = Falling edge transition
843101AGI-312
www.icst.com/products/hiperclocks.html
4
REV. A NOVEMBER 1, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843101I-312
FEMTOCLOCKSTM CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
4.6V -0.5V to VCC + 0.5V 50mA 100mA 89C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = -40C TO 85C
Symbol VCC VCCA VCCO IEE ICC ICCA ICCO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Core Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 92 78 7 4 Maximum 3.465 3.465 3.465 Units V V V mA mA mA mA
TABLE 5B. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V5%,VCCO = 2.5V5%, TA = -40C TO 85C
Symbol VCC VCCA VCCO IEE ICC ICCA ICCO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Core Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 2.375 Typical 3.3 3.3 2.5 90 78 7 4 Maximum 3.465 3.465 2.625 Units V V V mA mA mA mA
TABLE 5C. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 2.5V5%, TA = -40C TO 85C
Symbol VCC VCCA VCCO IEE ICC ICCA ICCO
843101AGI-312
Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Core Supply Current Analog Supply Current Output Supply Current
Test Conditions
Minimum 2.375 2.375 2.375
Typical 2.5 2.5 2.5 84 74 7 3
Maximum 2.625 2.625 2.625
Units V V V mA mA mA mA
www.icst.com/products/hiperclocks.html
5
REV. A NOVEMBER 1, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843101I-312
FEMTOCLOCKSTM CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
Test Conditions VCC = 3.3V VCC = 2.5V VCC = 3.3V VCC = 2.5V Minimum Typical 2 1. 7 -0.3 -0.3 Maximum VCC + 0.3 VCC + 0.3 0.8 1.7 150 5 -5 -150 20 Units V V V V A A A A ns/v
TABLE 5D. LVCMOS / LVTTL DC CHARACTERISTICS, TA = -40C TO 85C
Symbol VIH VIL Parameter Input High Voltage Input Low Voltage CLK, SEL, S_DATA, S_LOAD, S_CLOCK, MODE OE CLK, SEL, S_DATA, S_LOAD, S_CLOCK, MODE OE t/v Input Transistion Rise/Fall Rate OE, SEL, S_CLOCK, S_DATA, S_LOAD, MODE
IIH
Input High Current
VCC = VIN = 3.465 or 2.625V VCC = VIN = 3.465 or 2.625V VCC = 3.465V or 2.625V, VIN = 0V VCC = 3.465V or 2.625V, VIN = 0V
IIL
Input Low Current
TABLE 5E. LVPECL DC CHARACTERISTICS, TA = -40C TO 85C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 0.9 VCCO - 1.7 1. 0 Units V V V
NOTE 1: Outputs terminated with 50 to VCCO - 2V.
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using an 18pF parallel resonant cr ystal. Test Conditions Minimum Typical Maximum 25 50 7 100 Units MHz pF W Fundamental
TABLE 7. INPUT FREQUENCY CHARACTERISTICS, TA = -40C
Symbol Parameter CLK fIN Input Frequency XTAL_IN/XTAL_OUT S_CLOCK
TO
85C
Minimum Typical 25 25 50 Maximum Units MHz MHz MHz
Test Conditions
843101AGI-312
www.icst.com/products/hiperclocks.html
6
REV. A NOVEMBER 1, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843101I-312
FEMTOCLOCKSTM CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
Test Conditions Mode = LOW 312.5MHz, (1.875MHz - 20MHz) 20% to 80% Minimum Typical 312.5 0.52 425 50 10 10 10 Maximum Units MHz ps ps % ns ns ns
TABLE 8A. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = -40C TO 85C
Symbol fOUT t jit(O) tR / tF odc Parameter Output Frequency RMS Phase Jitter ; NOTE 1 Output Rise/Fall Time
Output Duty Cycle S_DATA to S_CLOCK tS Setup Time S_CLOCK to S_LOAD S_DATA to Hold Time tH S_CLOCK NOTE 1: Characterized using a 25MHz cr ystal.
TABLE 8B. AC CHARACTERISTICS, VCC = VCCA = 3.3V5%,VCCO = 2.5V5%, TA = -40C TO 85C
Symbol fOUT t jit(O) t R / tF odc Parameter Output Frequency RMS Phase Jitter ; NOTE 1 Output Rise/Fall Time Mode = LOW 312.5MHz, (1.875MHz - 20MHz) 20% to 80% Test Conditions Minimum Typical 312.5 0.46 405 50 10 10 10 Maximum Units MHz ps ps % ns ns ns
Output Duty Cycle S_DATA to S_CLOCK tS Setup Time S_CLOCK to S_LOAD S_DATA to Hold Time tH S_CLOCK NOTE 1: Characterized using a 25MHz cr ystal.
TABLE 8C. AC CHARACTERISTICS, VCC = VCCA = VCCO = 2.5V5%, TA = -40C TO 85C
Symbol fOUT t jit(O) t R / tF odc Parameter Output Frequency RMS Phase Jitter ; NOTE 1 Output Rise/Fall Time Mode = LOW 312.5MHz, (1.875MHz - 20MHz) 20% to 80% Test Conditions Minimum Typical 312.5 0.45 375 50 10 10 10 Maximum Units MHz ps ps % ns ns ns
Output Duty Cycle S_DATA to S_CLOCK tS Setup Time S_CLOCK to S_LOAD S_DATA to Hold Time tH S_CLOCK NOTE 1: Characterized using a 25MHz cr ystal.
843101AGI-312
www.icst.com/products/hiperclocks.html
7
REV. A NOVEMBER 1, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843101I-312
FEMTOCLOCKSTM CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
AT
TYPICAL PHASE NOISE
0 -10 -20 -30 -40 -50 -60 -70
312.5MHZ (3.3V)
10 Gigabit Ethernet Filter 312.5MHz
RMS Phase Noise Jitter 1.875MHz to 20MHz = 0.52ps (typical)
NOISE POWER dBc Hz
-80 -90 -100 -110 -120 -130 -140 -150 -170 -180 -190 100 1k 10k 100k 1M 10M 100M
Raw Phase Noise Data
OFFSET FREQUENCY (HZ)
843101AGI-312
www.icst.com/products/hiperclocks.html
8
-160
Phase Noise Result by adding 10 Gigabit Ethernet Filter to raw data
REV. A NOVEMBER 1, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843101I-312
FEMTOCLOCKSTM CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V
2.8V0.04V 2V
V CC , VCCA, VCCO
Qx
SCOPE
V CC , VCCA VCCO
Qx
SCOPE
LVPECL
nQx
LVPECL
VEE
nQx
VEE
-1.3V 0.165V
-0.5V 0.125V
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
2V
Phase Noise Plot
Noise Power
V CC , VCCA, VCCO
Qx
SCOPE
LVPECL
nQx
Phase Noise Mask
VEE
f1 Offset Frequency f2
-0.5V 0.125V
RMS Jitter = Area Under the Masked Phase Noise Plot
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
nQ 80% Clock Outputs 80% VSW I N G 20% tR tF 20% Q
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
OUTPUT RISE/FALL TIME
843101AGI-312
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
www.icst.com/products/hiperclocks.html
9
REV. A NOVEMBER 1, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843101I-312
FEMTOCLOCKSTM CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843101I-312 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA. The 10 resistor can also be replaced by a ferrite bead.
3.3V or 2.5V VCC .01F VCCA .01F 10F 10
FIGURE 2. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS843101I-312 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 3 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_OUT C1 27p X1 18pF Parallel Crystal XTAL_IN C2 27p
Figure 3. CRYSTAL INPUt INTERFACE
843101AGI-312
www.icst.com/products/hiperclocks.html
10
REV. A NOVEMBER 1, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843101I-312
FEMTOCLOCKSTM CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
RECOMMENDATIONS FOR UNUSED INPUT PINS INPUTS:
CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. CLK INPUT: For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the CLK input to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50
125
FOUT FIN
125
Zo = 50 FOUT FIN
Zo = 50 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
Zo = 50 84 84
FIGURE 4A. LVPECL OUTPUT TERMINATION
FIGURE 4B. LVPECL OUTPUT TERMINATION
843101AGI-312
www.icst.com/products/hiperclocks.html
11
REV. A NOVEMBER 1, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843101I-312
FEMTOCLOCKSTM CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
very close to ground level. The R3 in Figure 4B can be eliminated and the termination is shown in Figure 4C.
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 5A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is
2.5V 2.5V VCC=2.5V R1 250 Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R2 62.5 R4 62.5 R3 250
2.5V VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
R3 18
FIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE
843101AGI-312
www.icst.com/products/hiperclocks.html
12
REV. A NOVEMBER 1, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843101I-312
FEMTOCLOCKSTM CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843101I-312. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843101I-312 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 92mA = 318.78mW Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 318.78mW + 30mW = 348.78mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 81.8C/W per Table 9 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.349W *81.8C/W = 113.5C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 9. THERMAL RESISTANCE JA FOR 16-PIN TSSOP, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 137.1C/W 89.0C/W
200
118.2C/W 81.8C/W
500
106.8C/W 78.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
843101AGI-312
www.icst.com/products/hiperclocks.html
13
REV. A NOVEMBER 1, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843101I-312
FEMTOCLOCKSTM CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT RL 50 VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = V (V
CCO_MAX
OH_MAX
=V
CCO_MAX
- 0.9V
-V
OH_MAX
) = 0.9V =V - 1.7V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CCO_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CCO_MAX
CCO_MAX
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
L
CCO_MAX
-V
OH_MAX
)=
[(2V - 0.9V)/50] * 0.9V = 19.8mW ))/R ] * (V
L
Pd_L = [(V
OL_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
843101AGI-312
www.icst.com/products/hiperclocks.html
14
REV. A NOVEMBER 1, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843101I-312
FEMTOCLOCKSTM CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER RELIABILITY INFORMATION
TABLE 10. JAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 137.1C/W 89.0C/W
200
118.2C/W 81.8C/W
500
106.8C/W 78.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS843101I-312 is: 4093
843101AGI-312
www.icst.com/products/hiperclocks.html
15
REV. A NOVEMBER 1, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843101I-312
FEMTOCLOCKSTM CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP
TABLE 11. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 -0.05 0.80 0.19 0.09 4.90 6.40 BASIC 4.50 0.65 BASIC 0.75 8 0.10 Millimeters Minimum 16 1.20 0.15 1.05 0.30 0.20 5.10 Maximum
Reference Document: JEDEC Publication 95, MO-153
843101AGI-312
www.icst.com/products/hiperclocks.html
16
REV. A NOVEMBER 1, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843101I-312
FEMTOCLOCKSTM CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
TABLE 12. ORDERING INFORMATION
Part/Order Number Marking Package Shipping Packaging Temperature ICS843101AGI-312 TBD 16 Lead TSSOP tube -40C to 85C ICS843101AGI-312T TBD 16 Lead TSSOP 2500 tape & reel -40C to 85C ICS843101AGI-312LF TBD 16 Lead "Lead-Free" TSSOP tube -40C to 85C ICS843101AGI-312LFT TBD 16 Lead "Lead-Free" TSSOP 2500 tape & reel -40C to 85C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS complaint.
The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843101AGI-312
www.icst.com/products/hiperclocks.html
17
REV. A NOVEMBER 1, 2005

▲Up To Search▲

Price & Availability of ICS843101I-312

	To Download ICS843101I-312 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .