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| NB7L32M 2.5V/3.3V, 14GHz /2 Clock Divider w/CML Output and Internal Termination Descriptions The NB7L32M is an integrated /2 divider with differential clock inputs and asynchronous reset. Differential clock inputs incorporate internal 50 W termination resistors and accept LVPECL (Positive ECL), CML, or LVDS. The high frequency reset pin is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the reset allows for the synchronization of multiple NB7L32M's in a system. The differential 16 mA CML output provides matching internal 50 W termination which guarantees 400 mV output swing when externally receiver terminated 50 W to VCC (See Figure 16). The device is housed in a small 3x3 mm 16 pin QFN package. Features http://onsemi.com MARKING DIAGRAM* 16 1 QFN-16 MN SUFFIX CASE 485G A L Y W G NB7L 32M ALYWG * * * * * * * * * Maximum Input Clock Frequency 14 GHz Typical 200 ps Max Propagation Delay 30 ps Typical Rise and Fall Times < 0.5 ps Maximum (RMS) Random Clock Jitter Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V CML Output Level (400 mV Peak-to-Peak Output), Differential Output Only 50 W Internal Input and Output Termination Resistors Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP, EP, and SG Devices These are Pb-Free Devices = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package *For additional marking information, refer to Application Note AND8002/D. FUNCTIONAL BLOCK DIAGRAM R VCC VEE R1 VTCLK 50 W CLK CLK 50 W VTCLK Divide by 2 Reset Q Q TRUTH TABLE CLK x Z CLK x W R H L Q L /2 Q H /2 Z = LOW to HIGH Transition W = HIGH to LOW Transition x = Don't Care ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. (c) Semiconductor Components Industries, LLC, 2005 November, 2005 - Rev. 0 1 Publication Order Number: NB7L32M/D NB7L32M VCC 16 VTCLK CLK CLK VTCLK 1 2 NB7L32M 3 4 5 NC 6 VEE 7 VEE 8 VEE 10 9 Q VCC R 15 VCC VCC 14 13 12 11 VCC Q Exposed Pad (EP) Figure 1. Pin Configuration (Top View) Table 1. PIN DESCRIPTION Pin 1 Name VTCLK I/O - Description Internal 50 W termination pin. In the differential configuration when the input termination pin (VTCLK, VTCLK) are connected to a common termination voltage or left open, and if no signal is applied on CLK/CLK input then the device will be susceptible to self-oscillation. Noninverted differential input. In the differential configuration when the input termination pin (VTCLK, VTCLK) are connected to a common termination voltage or left open and if no signal is applied on CLK/CLK input, then the device will be susceptible to self-oscillation. Inverted differential input. In the differential configuration when the input termination pin (VTCLK, VTCLK) are connected to a common termination voltage or left open and if no signal is applied on CLK/CLK input, then the device will be susceptible to self-oscillation. Internal 50 W termination pin. In the differential configuration when the input termination pin (VTCLK, VTCLK) are connected to a common termination voltage or left open and if no signal is applied on CLK/CLK input, then the device will be susceptible to self-oscillation. No connect. NC pin must be left open. Negative supply voltage. Positive supply voltage. Inverted differential output. Typically terminated with 50 W resistor to VCC. Noninverted differential output. Typically terminated with 50 W resistor to VCC. Reset Input. Internal pulldown to 75 kW to VEE. Exposed Pad. The thermally exposed pad (EP) on package bottom (see case drawing) must be attached to a heat-sinking conduit. EP is electrically isolated from VCC and VEE. 2 CLK ECL, CML, LVDS Input 3 CLK ECL, CML, LVDS Input 4 VTCLK - 5 6, 7, 8 9, 12, 13, 14, 16 10 11 15 - NC VEE VCC Q Q R EP - - - CML Output CML Output LVTTL/LVCMOS - http://onsemi.com 2 NB7L32M Table 2. ATTRIBUTES Characteristics Internal Input Pulldown Resistor ESD Protection Moisture Sensitivity (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. R1 Human Body Model Machine Model QFN-16 Oxygen Index: 28 to 34 Value 75 kW > 500 V > 30 V Level 1 UL 94 V-0 @ 0.125 in 349 Table 3. MAXIMUM RATINGS Symbol VCC VEE VI VINPP IIN Iout TA Tstg qJA qJC Tsol Parameter Positive Power Supply Negative Power Supply Positive Input Negative Input Differential Input Voltage Input Current Through RT (50 W Resistor) Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) (Note 2) Thermal Resistance (Junction-to-Case) Wave Solder Pb-Free 0 lfpm 500 lfpm 1S2P <3 sec @ 260C QFN-16 QFN-16 QFN-16 Static Surge Continuous Surge QFN-16 Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V VI VCC VI VEE Condition 2 Rating 3.6 -3.6 3.6 -3.6 2.8 45 80 25 50 -40 to +85 -65 to +150 41.6 35.2 4.0 265 Unit V V V V V mA mA mA mA C C C/W C/W C/W C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 2. JEDEC standard multilayer board - 1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 3 NB7L32M Table 4. DC CHARACTERISTICS, CLOCK INPUTS, CML OUTPUTS VCC = 2.375 V to 3.465 V, VEE = 0 V, TA = -40C to +85C Symbol ICC VOH VOL RTOUT RTemp Coef Characteristic Power Supply Current (Note 3) Output HIGH Voltage (Note 4) Output LOW Voltage (Note 4) Internal Output Termination Resistor Internal I/O Termination Resistor Temperature Coefficient Min 50 VCC - 40 VCC - 500 45 Typ 65 VCC - 10 VCC - 400 50 6.38 Max 80 VCC VCC - 330 55 Unit mA mV mV W mW/C DIFFERENTIAL CLK/CLK INPUT DRIVEN SINGLE-ENDED (see Figure 10 and 12) Vth VIH VIL VIHD VILD VCMR VID IIH IIL RTIN VIH VIL IIH IIL Input Threshold Reference Voltage Range (Note 6) Single-ended Input HIGH Voltage Single-ended Input LOW Voltage 1050 Vth + 150 VEE 1200 VEE 1125 150 VCC VCC + 300 Vth - 150 VCC + 300 VCC - 75 VCC 2500 mV mV mV DIFFERENTIAL CLK/CLK INPUTS DRIVEN DIFFERENTIALLY (see Figure 11 and 13) Differential Input HIGH Voltage Differential Input LOW Voltage Input Common Mode Range (Differential Configuration, Note 7) Differential Input Voltage (VIHD - VILD) Input HIGH Current Input LOW Current CLK/CLK (VTCLK/R/VTCLK/R Open) CLK/CLK(VTCLK/R/VTCLK/R Open) mV mV mV mV 0 -50 45 30 0 50 100 50 55 mA mA W Internal Input Termination Resistor LVTTL/LVCMOS RESET INPUT Single-ended Input HIGH Voltage Single-ended Input LOW Voltage Input HIGH Current Input LOW Current R R 2000 VEE 0 0 30 10 VCC 800 100 100 mV mV mA mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. Input termination pins open and all outputs loaded with external RL = 50 W receiver termination resistor. 4. CML outputs require RL = 50 W receiver termination resistors to VCC for proper operation. (See Figure 9) 5. Input and output parameters vary 1:1 with VCC. 6. Vth is applied to the complementary input when operating in single-ended mode. 7. VCMR(MIN) varies 1:1 with VEE, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 4 NB7L32M Table 6. AC CHARACTERISTICS VCC = 2.375 V to 3.465 V, VEE = 0 V (Note 8) -40C Symbol VOUTPP Characteristic Output Voltage Amplitude (@ VINPP(MIN)) fin 7 GHz (See Figures 2, 3, 4, 5, 6, and 7) fin 12 GHz Maximum Input Clock Frequency (See Figures 2 and 3) Propagation Delay to Output Differential (See Figure 8) Duty Cycle Skew (Note 9) Device-to-Device Skew (Note 12) Reset Recovery (See Figure 8) Minimum Pulse Width Random Clock Jitter (RMS) (Note 11) Input Voltage Swing/Sensitivity (Differential Configuration) (Note 10) Output Rise/Fall Times @ 1 GHz (20% - 80%) fin 7 GHz fin = 12 GHz 150 30 R 300 500 CLK to Q R to Q Min 190 160 12 130 200 Typ 330 320 14 155 240 2 6 135 210 0.13 0.14 0.5 0.5 2500 45 150 30 200 300 20 50 300 500 Max Min 190 160 12 130 200 255C Typ 330 320 14 155 240 2 6 135 210 0.13 0.14 0.5 0.5 2500 45 150 30 200 300 20 50 300 500 Max Min 190 160 12 130 200 855C Typ 330 320 14 155 260 2 6 135 210 0.13 0.14 0.5 0.5 2500 45 200 300 20 50 ps ps ps mV ps Max Unit mV fIN tPLH, tPHL tskew tRR tPW tJITTER VINPP tr tf GHz ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. Measured by forcing VINPP(MIN) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC. Input edge rates 40 ps (20% - 80%). 9. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw- and Tpw+ 1 GHz. 10. VINPP(MAX) cannot exceed VCC - VEE. Input voltage swing is a single-ended measurement operating in differential mode. 11. Additive RMS jitter with 50% duty cycle input clock signal. 12. Device-to-device skew is measured between outputs under identical transition @ 1 GHz. http://onsemi.com 5 NB7L32M OUTPUT VOLTAGE AMPLITUDE (mV) 450 400 350 300 250 200 150 100 50 0 0 2 4 6 8 10 12 14 VCC = 3.3 V VCC = 2.5 V INPUT CLOCK FREQUENCY (GHz) Figure 2. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fOUT) at Ambient Temperature (VINPP = 150 mV) 0 -5 INPUT POWER (dBm) -10 -15 -20 -25 -30 -35 -40 -45 0 2 4 6 8 10 12 14 Safe Operating Area Typical +223.61 +125.74 +70.71 +39.76 +22.36 +12.57 +7.07 +3.98 +2.24 +1.26 16 INPUT VOLTAGE (mVrms) INPUT CLOCK FREQUENCY (GHz) Figure 3. Input Signal Amplitude vs Input Clock Frequency (All Temperatures and Power Supplies; Guaranteed Output Amplitude of at Least VOUTPP = 160 mV) http://onsemi.com 6 NB7L32M VOLTAGE (50 mV/div) TIME (190 ps/div) VOLTAGE (50 mV/div) TIME (190 ps/div) Figure 4. Typical Output Waveform with fIN = 7 GHz( VCC = 2.5 V, VINPP = 400 mV, Room Temperature, VOUTPP = 357 mV, tr = 33 ps, tf = 30 ps, fOUT = 3.499 GHz) Figure 5. Typical Output Waveform with fIN = 7 GHz(VCC = 3.3 V, VINPP = 400 mV, Room Temperature, VOUTPP = 387 mV, tr = 32 ps, tf = 29.8 ps, fOUT = 3.499 GHz) VOLTAGE (50 mV/div) TIME (52 ps/div) VOLTAGE (50 mV/div) TIME (52 ps/div) Figure 6. Typical Output Waveform with fIN = 14 GHz(VCC = 2.5 V, VINPP = 400 mV, Room Temperature, VOUTPP = 292 mV, tr = 25 ps, tf = 27 ps, fOUT = 7.01 GHz) Figure 7. Typical Output Waveform with fIN = 14 GHz(VCC = 3.3 V, VINPP = 400 mV, Room Temperature, VOUTPP = 319 mV, tr = 25 ps, tf = 26 ps, fOUT = 7.01 GHz) 50% 50% VOUTPP = VOH(Q) - VOL(Q) Q tPLH tPHL VINPP = VIH(CLK) - VIL(CLK) 50% 50% CLK R tRR(MIN) 50% Figure 8. AC Reference Measurement (Timing Diagram) http://onsemi.com 7 NB7L32M VCC 50 W Q Driver Device Q Zo = 50 W Zo = 50 W 50 W D Receiver Device D Figure 9. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8073/D - Termination of CML Logic Devices.) CLK Vth Vth CLK CLK CLK Figure 10. Differential Input Driven Single-Ended VCC Vthmax VIHmax VILmax VIH Vth VIL VIHmin VILmin NOTE: Figure 11. Differential Inputs Driven Differentially VCC VCMmax VCMR D D VCMmin GND VEE v VIN v VCC + 300 mV; VIH > VIL VIHDmax VILDmax VID = VIHD - VILD VIHDtyp VILDtyp VIHDmin VILDmin Vth D Vthmin GND Figure 12. Vth Diagram Figure 13. VCMR Diagram VCC 50 W 50 W Q Q 16 mA VEE Figure 14. CML Output Structure http://onsemi.com 8 NB7L32M APPLICATION INFORMATION All NB7L32M inputs can accept PECL, CML, and LVDS signal levels. The limitations for differential input signal (LVDS, PECL, or CML) are minimum input swing of 150 mV and the maximum input swing of 2500 mV. Within these conditions, the input voltage can range from VCC to 1.2 V. Examples interfaces are illustrated below in a 50 W environment (Z = 50 W). For output termination and interface, refer to application note AND8020/D. Table 5. INTERFACING OPTIONS Interfacing Options CML LVDS AC-COUPLED RSECL, PECL, NECL Connections Connect VTD and VTD to VCC (See Figure 15) Connect VTD and VTD Together (See Figure 17) Bias VTD and VTD Inputs within Common Mode Range (VCMR) (See Figure 16) Standard ECL Termination Techniques (See Figure 9) VCC VCC 50 W 50 W Q Z = 50 W VCC Z = 50 W VCC D VTD VTD D VEE 50 W 50 W NB7L32M CML Driver Q VEE Figure 15. CML to NB7L32M Interface VCC VCC Z = 50 W C D VTD VTD D 50 W NB7L32M 50 W PECL Driver Recommended RT Values VCC RT RT VEE VEE RT 5.0 V 290 W 3.3 V 150 W 2.5 V 80 W Z = 50 W VBias* VBias* C VEE *VBias must be within common mode range limits (VCMR) Figure 16. PECL to NB7L32M Interface http://onsemi.com 9 NB7L32M APPLICATION INFORMATION VCC VCC Z = 50 W LVDS Driver Z = 50 W D VTD VTD D 50 W NB7L32M 50 W VEE VEE Figure 17. LVDS to NB7L32M Interface ORDERING INFORMATION Device NB7L32MMNG NB7L32MMNR2G Package QFN-16 (Pb-Free) QFN-16 (Pb-Free) Shipping 123 Units / Rail 3000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 10 NB7L32M PACKAGE DIMENSIONS 16 PIN QFN MN SUFFIX CASE 485G-01 ISSUE B D A B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG DIM A A1 A3 b D D2 E E2 e K L SEATING PLANE MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.20 --- 0.30 0.50 PIN 1 LOCATION 0.15 C 0.15 C 0.10 C 16 X 0.08 C 16X L NOTE 5 4 16X K 1 16 16X 13 0.10 C A B 0.05 C NOTE 3 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. CCC CCC CCC TOP VIEW (A3) SIDE VIEW D2 5 E A A1 C e 8 EXPOSED PAD 9 E2 12 e b BOTTOM VIEW http://onsemi.com 11 NB7L32M/D |
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