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TISP61089D, TISP61089SD, TISP61089AD, TISP61089ASD, TISP61089P, TISP61089AP DUAL FORWARD-CONDUCTING P-GATE THYRISTORS PROGRAMMABLE OVERVOLTAGE PROTECTORS
TISP61089 Gated Protector Series
Overvoltage Protection for Negative Rail SLICs Dual Voltage-Tracking Protectors - `61089 for Battery Voltages to ......................................... -75 V - `61089A for Battery Voltages to ..................................... -100 V - Low Gate Triggering Current ....................................... < 5 mA - High Holding Current ............................................... > 150 mA Rated for GR-1089-CORE and K.44 Impulses
Impulse Wave Shape IPPSM Voltage 2/10 10/700 10/1000 Current 2/10 5/310 10/1000 A 120 40 30
2/10 Overshoot Voltage Specified
Element Diode SCR IPP = 100 A, 2/ 10 V 8 12
Package Options - Surface Mount 8-pin Small-Outline Line Feed-Thru Connection (D) Shunt Version Connection (SD) - Through-Hole 8-pin DIP (P) ..................................................... UL Recognized Components
D Package, P Package Top Views and Device Symbol for Feed-Thru Pin-Out
(Tip) (Gate) K1 G NC (Ring) K2 1 2 3 4 8 7 6 5 K1 (Tip) A A (Ground) (Ground) G A A K1 K1
K2 (Ring)
MD6XBD
NC - No internal connection Terminal typical application names shown in parenthesis
K2
K2
SD6XAEB
D Package Top View and Device Symbol for Shunt (SD) Pin-Out
(Tip) (Gate) K1 G NC (Ring) K2 1 2 3 4 8 7 6 5 NC A A NC
MD6XBE
K1 (Ground) (Ground) G A A
NC - No internal connection Terminal typical application names shown in parenthesis
K2
SD6XAU
How To Order
Device TISP61089 Package D (Small-Outline) Carrier R Tube R Tube Tube Order as TISP61089DR TISP61089D TISP61089SDR TISP61089SD TISP61089P TISP61089AS TISP61089A D (Small-Outline) P (8-pin DIP) TISP61089A D (Small-Outline) Device Package Carrier R Tube R Tube Tube Order as TISP61089ADR TISP61089AD TISP61089ASDR TISP61089ASD TISP61089AP
TISP61089S TISP61089
D (Small-Outline) P (8-pin DIP)
Carrier R is Embossed Tape Reeled
Carrier R is Embossed Tape Reeled
NOVEMBER 1995 - REVISED AUGUST 2002 Specifications are subject to change without notice.
1
TISP61089 Gated Protector Series
Description
These `61089 parts are all dual forward-conducting buffered p-gate thyristor (SCR) overvoltage protectors. They are designed to protect monolithic SLICs (Subscriber Line Interface Circuits) against overvoltages on the telephone line caused by lightning, a.c. power contact and induction. The `61089 limits voltages that exceed the SLIC supply rail voltage. The `61089 parameters are specified to allow equipment compliance with Telcordia (formally Bellcore) GR-1089-CORE and ITU-T recommendations K.20, K.21 and K.45. The SLIC line driver section is typically powered from 0 V (ground) and a negative (battery) voltage. The protector gate is connected to this negative supply. This references the protection (clipping) voltage to the negative supply voltage. The protection voltage will then track the negative supply voltage and the overvoltage stress on the SLIC is minimized. Positive overvoltages are clipped to ground by diode forward conduction. Negative overvoltages are initially clipped close to the SLIC negative supply rail value. If sufficient current is available from the overvoltage, then the protector SCR will switch into a low voltage on-state condition. As the overvoltage subsides the high holding current of `61089 SCR avoids d.c. latchup. The `61089 is intended to be used with a series resistance of at least 25 and a suitable overcurrent function for Telcordia compliance. Power fault conditions require a series overcurrent element which either interrupts or reduces the circuit current before the `61089 current rating is exceeded. For equipment compliant to ITU-T recommendations K.20 or K.21 or K.45 only, the series resistor value is set by the coordination requirements. For coordination with a 400 V limit GDT, a minimum series resistor value of 10 is recommended. The `61089 buffered gate design reduces the loading on the SLIC supply during overvoltages caused by power cross and induction. The regular pin-out for surface mount and through-hole packages is a feed through configuration. Connection to the SLIC is made via the `61089, Ring through pins 4 - 5 and Tip through pins 1 - 8. A non-feed-through surface mount (D) package is available. This shunt (SD) version pin-out does not make duplicate connections to pin 5 and pin 8 which increases package creepage distance from ground of the other connections from about 0.7 mm to over 3 mm. High voltage ringing SLICs, with battery voltages below -100 V and down to -155 V, can be protected by the TISP61089B device. Details of this device are in the TISP61089B data sheet.
Absolute Maximum Ratings, -40 C TJ 85 C (Unless Otherwise Noted)
Rating Repetitive peak off-state voltage, VGK = 0 Repetitive peak gate-cathode voltage, VKA = 0 Non-repetitive peak on-state pulse current (see Notes 1 and 2) 10/1000 s (Telcordia (Bellcore) GR-1089-CORE, Issue 2, February 1999, Section 4) 5/320 s (ITU-T K.20, K.21& K.45, K.44 open-circuit voltage wave shape 10/700 s) 1.2/50 s (Telcordia (Bellcore) GR-1089-CORE, Issue 2, February 1999, Section 4) 2/10 s (Telcordia (Bellcore) GR-1089-CORE, Issue 2, February 1999, Section 4) Non-repetitive peak on-state current, VGG = -75 V, 50 Hz to 60 Hz (see Notes 1 and 2) 0.1 s 1s 5s 300 s 900 s Non-repetitive peak gate current, 1/2 s pulse, cathodes commoned (see Notes 1 and 2) Operating free-air temperature range Junction temperature Storage temperature range IGSM TA TJ Tstg ITSM 11 4.8 2.7 0.95 0.93 +40 -40 to +85 -40 to +150 -40 to +150 A C C C A IPPSM 30 40 100 120 A 61089 `61089A 61089 `61089A Symbol VDRM VGKRM Value -100 -120 -85 -120 Unit V V
NOTES: 1. Initially the protector must be in thermal equilibrium with -40 C T J 85 C. T he surge may be repeated after the device returns to its initial conditions. Gate voltage ranges are -20 V to -75 V for the `61089 and -20 V to -100 V for the `61089A. 2. The rated current values may be applied either to the Ring to Ground or to the Tip to Ground terminal pairs. Additionally, both terminal pairs may have their rated current values applied simultaneously (in this case the Ground terminal current will be twice the rated current value of an individual terminal pair). Above 85 C, derate linearly to zero at 150 C lead temperature.
NOVEMBER 1995 - REVISED AUGUST 2002 Specifications are subject to change without notice.
2
TISP61089 Gated Protector Series
Recommended Operating Conditions
Component CG Gate decoupling capacitor Series resistor for GR-1089-CORE first-level surge survival RS Series resistor for GR-1089-CORE first-level and second-level surge survival Series resistor for GR-1089-CORE intra-building port surge survival Series resistor for K.20, K.21 and K.45 coordination with a 400 V primary protector Min 100 25 40 8 10 Typ 220 Max Unit nF
Electrical Characteristics, TJ = 25 C (Unless Otherwise Noted)
Parameter ID Off-state current VD = VDRM , VGK = 0 Test Conditions TJ = 25 C TJ = 85 C -57 -60 -60 -64 9 12 12 16 3 6 8 8 12 -150 TJ = 25 C TJ = 85 C -5 -50 5 2.5 0.1 100 50 mA A A mA V C pF pF V V V V Min Typ Max -5 -50 Unit A A
V(BO)
Breakover voltage
2/10 s, IPP = -56 A, RS = 45 , VGG = -48 V, CG = 220 nF 2/10 s, IPP = -100 A, RS = 50 , VGG = -48 V, CG = 220 nF 1.2/50 s, I PP = -53 A, RS = 47 , VGG = -48 V, C G = 220 nF 1.2/50 s, I PP = -96 A, RS = 52 , VGG = -48 V, C G = 220 nF 2/10 s, IPP = -56 A, RS = 45 , VGG = -48 V, CG = 220 nF 2/10 s, IPP = -100 A, RS = 50 , VGG = -48 V, CG = 220 nF 1.2/50 s, I PP = -53 A, RS = 47 , VGG = -48 V, C G = 220 nF 1.2/50 s, I PP = -96 A, RS = 52 , VGG = -48 V, C G = 220 nF IF = 5 A, tw = 200 s 2/10 s, IPP = 56 A, RS = 45 , VGG = -48 V, CG = 220 nF 2/10 s, IPP = 100 A, RS = 50 , VGG = -48 V, CG = 220 nF 1.2/50 s, I PP = 53 A, RS = 47 , VGG = -48 V, C G = 220 nF 1.2/50 s, I PP = 96 A, RS = 52 , VGG = -48 V, C G = 220 nF IT = -1 A, di/dt = 1A/ms, VGG = -48 V VGG = VGK = VGKRM, VKA = 0 IT = -3 A, tp(g) 20 s, VGG = -48 V IT = -3 A, tp(g) 20 s, VGG = -48 V 1.2/50 s, I PP = -53 A, RS = 47 , VGG = -48 V, C G = 220 nF f = 1 MHz, Vd = 1 V, IG = 0, (see Note 3) VD = -3 V VD = -48 V
VGK(BO)
Gate-cathode impulse breakover voltage Forward voltage Peak forward recovery voltage Holding current Gate reverse current Gate trigger current Gate-cathode trigger voltage Gate switching charge Cathode-anode offstate capacitance
VF
VFRM
IH IGKS IGT VGT QGS CKA
NOTES: 3. These capacitance measurements employ a three terminal capacitance bridge incorporating a guard circuit. The unmeasured device terminals are a.c. connected to the guard terminal of the bridge.
Thermal Characteristics
Parameter RJA Junction to free air thermal resistance Test Conditions TA = 25 C, EIA/JESD51-3 PCB, EIA/JESD51-2 environment, PTOT = 1.7 W P package 100 D Package Min Typ Max 120 C/W Unit
NOVEMBER 1995 - REVISED AUGUST 2002 Specifications are subject to change without notice.
3
TISP61089 Gated Protector Series
Parameter Measurement Information
+i IPPSM Quadrant I Forward Conduction Characteristic
IFSM (= |ITSM|) IF VF VGK(BO) VGG ID
-v
+v
IH
V(BO)
IT ITSM Quadrant III Switching Characteristic IPPSM -i
PM6XAAC
Figure 1. Voltage-Current Characteristic Unless Otherwise Noted, All Voltages are Referenced to the Anode
4
NOVEMBER 1995 - REVISED AUGUST 2002 Specifications are subject to change without notice.
TISP61089 Gated Protector Series
Thermal Information
PEAK NON-RECURRING AC vs CURRENT DURATION
20 ITSM -- Peak Non-Recurrent 50 Hz Current -- A 15 10 8 7 6 5 4 3 2 1.5 1 0.8 0.7 0.6 0.5 0.01
TI61AFA
RING AND T IP TERM INALS: Equal ITSM values applied simultaneously GROUND TERM INAL: Current twice ITSM value EIA /JESD51 Environment and PCB, TA = 25 C VGG = -80 V VGG = -60 V
VGG = -100 V
0.1
1 10 100 t -- Current Duration -- s
1000
Figure 2. Non-repetitive Peak On-State Current against Duration (Gate Voltage Ranges are -20 V to -75 V for the '61089 and -20 V to -100 V for the '61089A)
NOVEMBER 1995 - REVISED AUGUST 2002 Specifications are subject to change without notice.
5
TISP61089 Gated Protector Series
APPLICATIONS INFORMATION
Gated Protectors
This section covers three topics. First, it is explained why gated protectors are needed. Second, the voltage limiting action of the protector is described. Third, an example application circuit is described.
Purpose of Gated Protectors
Fixed voltage thyristor overvoltage protectors have been used since the early 1980s to protect monolithic SLICs (Subscriber Line Interface Circuits) against overvoltages on the telephone line caused by lightning, a.c. power contact and induction. As the SLIC was usually powered from a fixed voltage negative supply rail, the limiting voltage of the protector could also be a fixed value. The TISP1072F3 is a typical example of a fixed voltage SLIC protector. SLICs have become more sophisticated. To minimize power consumption, some designs automatically adjust the supply voltage, VBAT , to a value that is just sufficient to drive the required line current. For short lines the supply voltage would be set low, but for long lines, a higher supply voltage would be generated to drive sufficient line current. The optimum protection for this type of SLIC would be given by a protection voltage which tracks the SLIC supply voltage. This can be achieved by connecting the protection thyristor gate to the SLIC supply, Figure 3. This gated (programmable) protection arrangement minimizes the voltage stress on the SLIC, no matter what value of supply voltage.
TIP WIRE 600 GENERATOR SOURCE RESISTANCE 600 RING WIRE AC GENERATOR 0 - 600 V rms C1 220 nF IG ISLIC IBAT VBAT C2 D1
AI6XAGB
'61089 RSa 40 Th4
SLIC
RSb 40
Th5
SWITCHING M ODE POWER SUPPLY Tx
Figure 3. `61089 Buffered Gate Protector
Operation of Gated Protectors
Figures 4 and 5 show how the '61089 device limits negative and positive overvoltages. Positive overvoltages (Figure 5) are clipped by the antiparallel diodes in the '61089 protector and the resulting current is diverted to ground. Negative overvoltages (Figure 4) are initially clipped close to the SLIC negative supply rail value (VBAT ). If sufficient current is available from the overvoltage, then the protector (Th5) will crowbar into a low voltage on-state condition. As the overvoltage subsides the high holding current of the crowbar prevents d.c. latchup. The protection voltage will be the sum of the gate supply (VBAT ) and the peak gate-cathode voltage (VGK(BO)). The protection voltage will be increased if there is a long connection between the gate decoupling capacitor, C1, and the gate terminal. During the initial rise of a fast impulse, the gate current (IG ) is the same as the cathode current (I K). Rates of 70 A/s can cause inductive voltages of 0.7 V in 2.5 cm of printed wiring track. To minimize this inductive voltage increase of protection voltage, the length of the capacitor to gate terminal tracking should be minimized. Inductive voltages in the protector cathode wiring will also increase the protection voltage. These voltages can be minimized by routing the SLIC connection through the protector as shown in Figure 3.
Application Circuit
Figure 6 shows a typical '61089 part SLIC card protection circuit. The incoming line conductors, Ring (R) and Tip (T), connect to the relay matrix via the series overcurrent protection. Fusible resistors, fuses and positive temperature coefficient (PTC) thermistors can be used for overcurrent protection. Resistors will reduce the prospective current from the surge generator for both the '61089 device and the ring/test
6
NOVEMBER 1995 - REVISED AUGUST 2002 Specifications are subject to change without notice.
TISP61089 Gated Protector Series
APPLICATIONS INFORMATION
Application Circuit (Continued)
protector. The TISP7xxxF3 protector has the same protection voltage for any terminal pair. This protector is used when the ring generator configuration may be ground or battery-backed. For dedicated ground-backed ringing generators, the TISP3xxxF3 gives better protection as its inter-conductor protection voltage is twice the conductor to ground value. Relay contacts 3a and 3b connect the line conductors to the SLIC via the '61089 protector. The protector gate reference voltage comes from the SLIC negative supply (VBAT). A 220 nF gate capacitor sources the high gate current pulses caused by fast rising impulses.
SLIC PROTEC TOR SLIC
SLIC PROTEC TOR SLIC
IK
Th5 '61089 C1 220 nF IG VBAT
AI6XAHC
IF
Th5 '61089 C1 220 nF VBAT
AI6XAIC
Figure 4. Negative Overvoltage Condition
Figure 5. Positive Overvoltage Condition
OVERCURRENT PROTEC TION TIP WIRE RSa
RING/TEST PROTEC TION Th1
TEST RELAY
RING RELAY
SLIC RELAY S3a
SLIC PROTEC TOR Th4
SLIC
S1a Th3
S2a
RING WIRE
RSb
Th2 TISP 3xxxF3 OR 7xxxF3 S3b S1b S2b
Th5 '61089 C1 220 nF VBAT
TEST EQUIPMENT
RING GENERATOR
AI6XAJC
Figure 6. Typical Application Circuit
NOVEMBER 1995 - REVISED AUGUST 2002 Specifications are subject to change without notice.
7
TISP61089 Gated Protector Series
MECHANICAL DATA
Device Symbolization Code
Devices will be coded as below.
Device TISP61089D TISP61089SD TISP61089AD TISP61089ASD TISP61089P TISP61089AP Symbolization Code P61089 61089S 61089A 1089AS TISP61089 61089A
8
NOVEMBER 1995 - REVISED AUGUST 2002 Specifications are subject to change without notice.
TISP61089 Gated Protector Series
MECHANICAL DATA
D008 Plastic Small-outline Package
This small-outline package consists of a circuit mounted on a lead frame and encapsulated within a plastic compound. The compound will withstand soldering temperature with no deformation, and circuit performance characteristics will remain stable when operated in high humidity conditions. Leads require no additional cleaning or processing when used in soldered assembly.
D008
4.80 - 5.00 (0.189 - 0.197)
8-pin Small Outline Microelectronic Standard Package MS-012, JEDEC Publication 95
8
7
6
5
5.80 - 6.20 (0.228 - 0.244)
INDEX
3.81 - 4.00 (0.150 - 0.157)
1
2
3
4
1.35 - 1.75 (0.053 - 0.069)
7 NOM 3 Places
0.25 - 0.50 x 45 N0M (0.010 - 0.020)
4.60 - 5.21 (0.181 - 0.205)
0.102 - 0.203 (0.004 - 0.008) 0.28 - 0.79 (0.011 - 0.031) Pin Spacing 1.27 (0.050) (see Note A) 6 places
0.36 - 0.51 (0.014 - 0.020) 8 Places 0.190 - 0.229 (0.0075 - 0.0090)
7 NOM 4 Places 0.51 - 1.12 (0.020 - 0.044)
44
DIMENSIONS ARE:
MILLIMETERS (INCHES)
NOTES: A. B. C. D.
Leads are within 0.25 (0.010) radius of true position at maximum material condition. Body dimensions do not include mold flash or protrusion. Mold flash or protrusion shall not exceed 0.15 (0.006). Lead tips to be planar within 0.051 (0.002).
MDXXAA E
NOVEMBER 1995 - REVISED AUGUST 2002 Specifications are subject to change without notice.
9
TISP61089 Gated Protector Series
MECHANICAL DATA
D008 Tape DImensions
D008 Package (8-pin Small Outline) Single-Sprocket Tape
3.90 - 4.10 (.154 - .161) 7.90 - 8.10 (.311 - .319) 1.95 - 2.05 (.077 - .081)
1.50 - 1.60 (.059 - .063) 0.40 (.016)
0.8 MIN. (.03)
5.40 - 5.60 (.213 - .220) 11.70 - 12.30 (.461 - .484)
6.30 - 6.50 (.248 - .256)
o 1.50 MIN. (.059)
0 MIN.
Direction of Feed
Cover Tape
Carrier Tape Embossment
2.0 - 2.2 (.079 - .087)
DIMENSIONS ARE:
MILLIMETERS (INCHES)
NOTES: A. Taped devices are supplied on a reel of the following dimensions:Reel diameter: Reel hub diameter: Reel axial hole:
330 +0.0/-4.0 (12.99 +0.0/-.157) 100 2.0 (3.937 .079) 13.0 0.2 (.512 .008)
MDXXATC
B. 2500 devices are on a reel.
10
NOVEMBER 1995 - REVISED AUGUST 2002 Specifications are subject to change without notice.
TISP61089 Gated Protector Series
MECHANICAL DATA
P008 Plastic Dual-In-Line Package
This dual-in-line package consists of a circuit mounted on a lead frame and encapsulated within a plastic compound. The compound will withstand soldering temperature with no deformation, and circuit performance characteristics will remain stable when operated in high humidity conditions The package is intended for insertion in mounting-hole rows on 7.62 (0.300) centers. Once the leads are compressed and inserted, sufficient tension is provided to secure the package in the board during soldering. Leads require no additional cleaning or processing when used in soldered assembly.
P008
9.25 - 9.75 (.364 - .384)
8 7 6 5
Index Notch
6.10 - 6.60 (.240 - .260)
1
2
3
4
1.78 MAX. (.070) 4 Places
7.62 - 8.23 (.300 - .324)
5.08 MAX. (.200)
Seating Plane
0.51 MIN. (.020)
3.17 MIN. (.125)
0.20 - 0.36 (.008 - .014)
0.38 - 0.53 (.015 - .021) 8 Places
MILLIMETERS (INCHES)
2.54 TYP. (.100) (see Note A) 6 Places
8.38 - 9.40 (.330 - .370)
DIMENSIONS ARE:
MDXXCF
NOTES: A. Each pin centerline is located within 0.25 (0.010) of its true longitudinal position. B. Dimensions fall within JEDEC MS001 - R-PDIP-T, 0.300" Dual-In-Line Plastic Family. C. Details of the previous dot index P008 package style, drawing reference MDXXABA, are given in the earlier publications.
NOVEMBER 1995 - REVISED AUGUST 2002 Specifications are subject to change without notice.
11
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