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T4225B
Low-Cost Time-Code Receiver
Description
The T4225B is a bipolar integrated straight-through receiver circuit in the frequency range of 40 kHz to 80 kHz. The device is designed for radio-controlled clock applications.
Features
D D D D
Very low power consumption Very high sensitivity High selectivity by using two crystal filters Power-down mode available
D Only a few external components necessary D Digitalized serial output signal D AGC hold mode
Block Diagram
PON GND VCC Power supply Decoder FLA DEC TCO
95 10481
FLB
IN1 IN
AGC amplifier
Rectifier & integrator
SL
SB
Q1A
Q1B Q2A
Q2B
REC
INT
Figure 1.
Ordering and Package Information
Extended Type Number T4225B-MF T4225B-MC T4225B-MW Package No No No Remarks Die on foil Die in tray Wafer
Rev. A3, 03-Dec-98
1 (16)
T4225B
PAD Coordinates
The T4225B is only available as die for "chip-on-board" mounting. DIE size: 2.26 x 1.54 mm PAD size: 100 x 100 mm (contact window 88 x 88 mm) Thickness: 300 mm 20 mm
"
Symbol IN1 IN GND SB Q1A Q1B REC INT DEC FLA FLB SL Q2A Q2B PON TCO VCC
Function Amplifier input (inverted) Amplifier input (non inverted) Ground Bandwidth control Crystal filter 1 Crystal filter 1 Rectifier output Integrator output Decoder input Lowpass filter Lowpass filter AGC hold mode Crystal filter 2 Crystal filter 2 Power-ON/OFF control Time-code output Supply voltage
x-axis/mm 128 128 354 696 1040 1290 1528 1766 2044 2044 2044 2044 1724 1402 918 460 128
y-axis/mm 846 310 124 128 128 128 128 128 268 676 1072 1310 1324 1324 1324 1324 1246
The PAD coordinates are referred to the left bottom point of the contact window.
PAD Layout
TCO VCC FLB PON Q2B Q2A SL
IN1
T4225B
FLA
IN y - axis GND SB Q1A Q1B REC INT
DEC
x - axis Reference point (%)
95 10386
Figure 2.
2 (16)
Rev. A3, 03-Dec-98
T4225B
IN
A ferrite antenna is connected between IN and VCC. For high sensitivity, the Q factor of the antenna circuit should be as high as possible. Please note that a high Q factor requires temperature compensation of the resonant frequency in most cases. We recommend a Q factor between 50 and 100. Specifications are valid for Q > 30. An optimal signal-to-noise ratio will be achieved by a resonant resistance of 50 to 200 kW.
REC
Rectifier output and integrator input: The capacitor C1 between REC and INT is the lowpass filter of the rectifier and at the same time a damping element of the gain control.
94 8374
VCC
REC GND
Figure 6.
94 8379
IN
Figure 3.
DEC
Decoder input: Senses the current through the integration capacitor C2. The dynamic input resistance has a value of about 420 kW and is low compared to the impedance of C2.
SB
A resistor RSB is connected between SB and GND. It controls the bandwidth of the crystal filters. It is recommended: RSB = 0 W for DCF 77.5 kHz, RSB = 10 kW for 60 kHz WWVB and RSB = open for JG2AS 40 kHz.
94 8381
DEC SB GND
Figure 7.
GND
Figure 4.
94 8376
Q1A, Q1B
In order to achieve a high selectivity, a crystal is connected between the Pins Q1A and Q1B. It is used with the serial resonant frequency of the time-code transmitter (e.g., 60 kHz WWVB, 77.5 kHz DCF or 40 kHz JG2AS). The equivalent parallel capacitor of the filter crystal is internally compensated. The compensated value is about 0.7 pF. If full sensitivity and selectivity are not needed, the crystal filter can be substituted by a capacitor of 10 pF for DCF and WWVB and 22 pF for JG2AS.
SL
AGC hold mode: SL high (VSL = VCC) sets normal function, SL low (VSL = 0) disconnects the rectifier and holds the voltage VINT at the integrator output and also the AGC amplifier gain. VCC
Q1A
Q1B
94 8378
SL
94 8382
GND
Figure 5.
Figure 8.
Rev. A3, 03-Dec-98
3 (16)
T4225B
INT
Integrator output: The voltage VINT is the control voltage for the AGC. The capacitor C2 between INT and DEC defines the time constant of the integrator. The current through the capacitor is the input signal of the decoder.
94 8375
PON
If PON is connected to GND, the receiver will be activated. The set-up time is typically 0.5 s after applying GND at this pin. If PON is connected to VCC, the receiver will switch to power-down mode. VCC
INT PON GND
Figure 9. Figure 12.
94 8373
FLA, FLB
Lowpass filter: A capacitor C3 connected between FLA and FLB suppresses higher frequencies at the trigger circuit of the decoder.
TCO
The digitized serial signal of the time-code transmitter can be directly decoded by a microcomputer. Details about the time-code format of several transmitters are described separately. The output consists of a PNP-NPN push-pull-stage. It should be taken into account that in power-down mode (PON = high), TCO will be high.
FLB
FLB
VCC PON
94 8377
TCO
Figure 10.
94 8380
GND
Figure 13.
Q2A, Q2B
According to Q1A/Q1B, a crystal is connected between the Pins Q2A and Q2B. It is used with the serial resonant frequency of the time-code transmitter (e.g., 60 kHz WWVB, 77.5 kHz DCF or 40 kHz JG2AS). The equivalent parallel capacitor of the filter crystal is internally compensated. The value of the compensation is about 0.7 pF.
An additional improvement of the driving capability may be achieved by using a CMOS driver circuit or an NPN transistor with pull-up resistor connected to the collector (see figure 14). When using a CMOS driver, this circuit must be connected to VCC. VCC 10 kW
Q2A
Q2B GND
Figure 11.
100 kW TCO Pin16 TCO
94 8395 e
94 8383
Figure 14.
4 (16)
Rev. A3, 03-Dec-98
T4225B
Please note: The signals and voltages at the Pins REC, INT, FLA, FLB, Q1A, Q1B, Q2A and Q2B cannot be measured by standard measurement equipment due to very high internal impedances. For the same reason, the PCB should be protected against surface humidity. If high inductance values and low capacitor values are used, the additional parasitic capacitances of the coil (v20 pF) must be considered. The Q value of the capacitor should be no problem if a high Q type is used. The Q value of the coil differs more or less from the DC resistance of the wire. Skin effects can be observed but do not dominate. Therefore, it should not be a problem to achieve the recommended values of the resonant resistance. The use of thicker wire increases the Q value and accordingly reduces bandwidth. This is advantageous in order to improve reception in noisy areas. On the other hand, temperature compensation of the resonant frequency might become a problem if the bandwidth of the antenna circuit is low compared to the temperature variation of the resonant frequency. Of course, the Q value can also be reduced by a parallel resistor. Temperature compensation of the resonant frequency is a must if the clock is used at different temperatures. Please ask your supplier of bar antenna material and of capacitors for specified values of the temperature coefficient. Furthermore, some critical parasitics have to be considered. These are shortened loops (e.g., in the ground line of the PCB board) close to the antenna and undesired loops in the antenna circuit. Shortened loops decrease the Q value of the circuit. They have the same effect like conducting plates close to the antenna. To avoid undesired loops in the antenna circuit, it is recommended to mount the capacitor Cres as close as possible to the antenna coil or to use a twisted wire for the antenna-coil connection. This twisted line is also necessary to reduce feedback of noise from the microprocessor to the IC input. Long connection lines must be shielded. A final adjustment of the time-code receiver can be carried out by pushing the coil along the bar antenna. The maximum of the integrator output voltage VINT at Pin INT indicates the resonant point. But attention: The load current should not exceed 1 nA, that means an input resistance 1 GW of the measuring device is required. Therefore, a special DVM or an isolation amplifier is necessary.
Design Hints for the Ferrite Antenna
The bar antenna is a very critical device of the complete clock receiver. Observing some basic RF design rules helps to avoid possible problems. The IC requires a resonant resistance of 50 kW to 200 kW. This can be achieved by a variation of the L/C-relation in the antenna circuit. It is not easy to measure such high resistances in the RF region. A more convenient way is to distinguish between the different bandwidths of the antenna circuit and to calculate the resonant resistance afterwards. Thus, the first step in designing the antenna circuit is to measure the bandwidth. Figure 16 shows an example for the test circuit. The RF signal is coupled into the bar antenna by inductive means, e.g., a wire loop. It can be measured by a simple oscilloscope using the 10:1 probe. The input capacitance of the probe, typically about 10 pF, should be taken into consideration. By varying the frequency of the signal generator, the resonant frequency can be determined.
RF signal generator 77.5 kHz Scope
10 : 1 w10 MW wire loop Cres
94 7907 e
Probe
Figure 15.
At the point where the voltage of the RF signal at the probe drops by 3 dB, the two frequencies can then be measured. The difference between these two frequencies is called the bandwidth BWA of the antenna circuit. As the value of the capacitor Cres in the antenna circuit is known, it is easy to compute the resonant resistance according to the following formula: 1 R res 2 p BW A Cres
w
+
where Rres is the resonant resistance, BWA is the measured bandwidth (in Hz) Cres is the value of the capacitor in the antenna circuit (in Farad).
Rev. A3, 03-Dec-98
5 (16)
T4225B
Absolute Maximum Ratings
Parameters Supply voltage Ambient temperature range Storage temperature range Junction temperature Electrostatic handling ( MIL Standard 883 D ), except Pad IN, Q1A, Q1B, Q2A, Q2B Symbol VCC Tamb Rstg Tj VESD Value 5.25 -40 to +85 -40 to +85 125 2000 Unit V _C _C _C V
Electrical Characteristics
VCC = 3 V, reference point Pin 3, input signal frequency 80 kHz, Tamb = 25_C, unless otherwise specified Parameters Supply voltage range Supply current Test Conditions / Pin Pad VCC Pad VCC Without reception signal with reception signal = 200 mV OFF mode VCC = 1.5 V Pad IN Rres = 100 kW, Qres > 30 Symbol VCC ICC Min. 1.2 Typ. Max. 5.25 25 20 0.1 Unit V
15 t fin Vin Vin Cin 40 40 1 80 1.5 2
mA mA mA
s
Set-up time after VCC ON AGC amplifier input; IN Reception frequency range Minimum input voltage Maximum input voltage Input capacitance to ground Time code output; TCO Output voltage HIGH LOW Output current HIGH LOW Decoding characteristics for typical fieldstrentgh 1 mV/m
80 1.5
kHz
mV
mV pF
Pad TCO RLOAD = 870 kW to GND RLOAD = 650 kW to VCC VTCO = VCC/2 VTCO = VCC/2 DCF77 based on the values of the application circuit fig. 20: TCO pulse width 100 ms TCO pulse width 200 ms Delay compared with the transient of the RF signal: drop down (start transition) rise for 100 ms pulse (end transition) rise for 200 ms pulse (end transition) ts te1 te2 30 25 10 60 55 30 ms ms ms VOH VOL ISOURCE ISINK VCC - 0.4 0.4 3 4 10 12 V V
mA mA
130 230 ms ms
t100 t200
60 160
90 190
6 (16)
Rev. A3, 03-Dec-98
T4225B
Parameters Decoding characteristics for typical fieldstrentgh 1 mV/m Test Conditions / Pin WWVBbased on the values of the application circuit fig. 21: TCO pulse width 200 ms TCO pulse width 500 ms TCO pulse width 800 ms Delay compared with the transient of the RF signal: drop down (start transition) rise (end transition) JG2AS based on the values of the application circuit fig. 22: TCO pulse width 200 ms TCO pulse width 500 ms TCO pulse width 800 ms Delay compared with the transient of the RF signal: start transition (RF on) end transition (RF off) Power- ON/OFF control; PON Pad PON Input voltage Required IIN 0.5 mA HIGH LOW Input current VCC = 3 V VCC = 1.5 V VCC = 5 V Set-up time after PON AGC hold mode; SL Pad SL Input voltage Required IIN 0.5 mA HIGH LOW Input current Vin = VCC Vin = GND Rejection of interference fd - fud = 625 Hz signals Vd = 3 mV, fd = 77.5 kHz using 2 crystal filters using 1 crystal filter ts te 10 30 110 220 ms ms ts te 45 20 80 45 ms ms Symbol Min. Typ. Max. Unit
t200 t500 t800
140 440 740
200 500 800
ms ms ms
t200 t500 t800
240 420 720
410 490 790
ms ms ms
y
VCC - 0.2 IIN 1.4 1.7 0.7 3 0.5 VCC - 1.2 2
V V
mA mA mA
s
t
2
y
VCC - 0.2 VCC - 1.2 0.1 2.5
V V
mA mA
dB dB
af af
43 22
Rev. A3, 03-Dec-98
7 (16)
T4225B
Test Circuit (for Fundamental Function)
Test point: DVM with high and low input line for measuring of a voltage Vxx or a current lxx by conversion into a voltage.
Vd 1.657V
Ipon 300k Stco Vtco
TCO PON Q2B
Spon
1M 82p
Q2A
1M Isl Ssl
SL
T4225B
Ivcc 100k
VCC
10M Sdec
STABILISATION
DECODING
FLB
Iin
IN1 FLA
Idec 100M
1M
AGCAMPLIFIER
IN GND SB Q1A Q1B
RECTIFIER
DEC REC INT
Vdec
VCC 3V
~ Vin Ssb Vrec
82p
680p 3.3 n Srec Sint 10M Vrec
420k
Vsb
1M
10M
Vint Vint
Isb Irec Figure 16. Iint
95 10549
8 (16)
Rev. A3, 03-Dec-98
T4225B
Figure 17 shows a typical diagram to control sensitivity by measuring the voltage at INT vs. Vin. The input signal (e.g., generator frequency 77.5 kHz) is coupled to the input of the circuit via a transformer with a 50-W termination. In order to avoid a load at the INT Pin, the voltage should be measured with a meter input resistance > 1 GW! (1) (2) normal curve no optimal layout conditions
1.0 0.9 VINT ( V ) 0.8 0.7 2 0.6 1 0.5 -20
95 11210
0
20
40
60
80
100
Vin ( dBmV )
Figure 17.
VCC 50 Generator signal (e.g., 77.5 kHz) Rg Ra La INT -10 dB Lb Rb IN1 IN Ra = Rb = 50 W La = Lb = 88 mH
Figure 18.
T4225B
V INT (Ri > GW)
95 11208
Layout
95 10212
95 11213
Figure 19.
Rev. A3, 03-Dec-98
9 (16)
T4225B
Application Circuit for DCF 77.5 kHz
Control lines +VCC TCO PON 3) 77.5 kHz
95 10385
Microcomputer Keyboard Display
SL 1)
VCC TCO IN1 Ferrite Antenna fres = 77.5 kHz IN GND SB Q1A Q1B REC INT PON Q2B Q2A SL FLB C 3 10 nF FLA DEC
T4225B
C
1
C
2
1) If SL is not used, SL is connected to VCC 2) 77.5-kHz crystal can be replaced by 10 pF 3) If IC is activated, PON is connected to GND
77.5 kHz 2)
6.8 nF
33 nF
Figure 20.
Application Circuit for WWVB 60 kHz
Control lines +VCC TCO PON 3) 60 kHz
95 10384
SL 1)
Microcomputer Keyboard Display
VCC TCO IN1 Ferrite Antenna f res = 60 kHz IN GND SB Q1A Q1B REC INT PON Q2B Q2A SL FLB C 3 10 nF FLA DEC
T4225B
1) If SL is not used, SL is connected to VCC 2) 60-kHz crystal can be replaced by 10 pF 3) If IC is activated, PON is connected to GND
C 10 k 60 kHz 2)
1
C
2
15 nF
47 nF
Figure 21.
10 (16)
Rev. A3, 03-Dec-98
T4225B
Application Circuit for JG2AS 40 kHz
Control lines +V TCO PON 3) 40 kHz
95 10383
SL 1)
Microcomputer Keyboard Display
VCC TCO IN1 Ferrite Antenna fres = 40 kHz IN GND SB Q1A Q1B REC INT PON Q2B Q2A SL FLB C 3 10 nF FLA DEC
T4225B
1MW R 40 kHz 2) C1
C2 220 nF
1) If SL is not used, SL is connected to VCC 2) 40-kHz crystal can be replaced by 22 pF 3) If IC is activated, PON is connected to GND
0.68 nF
Figure 22.
Rev. A3, 03-Dec-98
11 (16)
T4225B
Information on the German Transmitter
Station: DCF 77, Frequency 77.5 kHz, Transmitting power 50 kW Location: Mainflingen/Germany, Geographical coordinates: 50__ 0.1'N, 09__ 00'E Time of transmission: permanent
Time frame 1 minute
( index count 1 second )
Time frame 40 45 50 55 0 5 10
0
5
10
15
20
25
30
35
coding when required
R A1 Z 1 Z 2 A2 S 1 2 4 8 10 20 40 P1 1 2 4 8 10 20 P 2 1 2 4 8 10 20 1 2 4 1 2 4 8 10 1 2 4 8 10 20 40 80 P3
minutes
hours
calendar day month day of the week
year
93 7527
Example:19.35 h s 1 2 seconds 20 21 22
Start Bit
4 23 24
8 25
10 26
20 27
40 28
P1 29
1 30
2 31
4 32
hours
8 33
10 34
20 35
P2
minutes Parity Bit P1 Figure 23.
Parity Bit P2
Modulation
The carrier amplitude is reduced to 25% at the beginning of each second for a period of 100 ms (binary zero) or 200 ms (binary one), except the 59th second.
Time-Code Format: (based on Information of Deutsche Bundespost)
The time-code format consists of 1-minute time frames. There is no modulation at the beginning of the 59th
second to indicate the switch over to the next 1-minute time frame. A time frame contains BCD-coded information of minutes, hours, calendar day, day of the week, month and year between the 20th second and 58th second of the time frame, including the start bit S (200 ms) and parity bits P1, P2 and P3. Furthermore, there are 5 additional bits R (transmission by reserve antenna), A1 (announcement of change-over to summer time), Z1 (during summer time 200 ms, otherwise 100 ms), Z2 (during standard time 200 ms, otherwise 100 ms) and A2 (announcement of leap second) transmitted between the 15th second and 19th second of the time frame.
12 (16)
Rev. A3, 03-Dec-98
T4225B
Information on the British Transmitter
Station: MSF Frequency 60 kHz Transmitting power 50 kW Location: Teddington, Middlesex Geographical coordinates: 52__ 22'N, 01_ 11'W Time of transmission: permanent, except the first Tuesday of each month from 10.00 h to 14.00 h.
Time frame 1 minute
( index count 1 second)
Time frame 45 50 55 0
0
0
5
10
15
20
25
30
35
40
5
10
80 40 20 10 8 4 2 1 10 8 4 2 1 20 10 8 4 2 1 4 2 1 20 10 8 4 2 1 40 20 10 8 4 2 1 0
year Switch over to the next time frame
month
day of hour month day of week
minute Parity check bits
0 500 ms 500 ms
1
minute identifier BST hour + minute day of week day + month year BST 7 GMT change impending
93 7528
Example: March 1993 seconds 17
80
40
20
10
8
4
2
1
10
8
4
2
1
18
19
20
21
year
22
23
24
25
26
27
28
29
30
month Figure 24.
Modulation
The carrier amplitude is switched off at the beginning of each second for a period of 100 ms (binary zero) or 200 ms (binary one).
Time-Code Format
The time-code format consists of 1-minute time frames. A time frame contains BCD-coded information of year, month, calendar day, day of the week, hours and minutes. At the switch-over to the next time frame, the carrier amplitude is switched off for a period of 500 ms. The prescence of the fast code during the first 500 ms at the beginning of the minute is not guaranteed. The transmission rate is 100 bits/s and the code contains information of hour, minute, day and month.
Rev. A3, 03-Dec-98
13 (16)
T4225B
Information on the US Transmitter
Station: WWVB Frequency 60 kHz Transmitting power 40 kW Location: Fort Collins Geographical coordinates: 40__ 40'N, 105__ 03'W Time of transmission: permanent
Time frame 1 minute
( index count 1 second)
Time frame 45 50 55 0
P0
0
P 0 FM R 40 20 10
5
10
15
20 10
20
25
200 100
30
35
40
5
10
AD D SU B AD D P4 800 400 200 100
80 40 20 10 P5 8 4 2 1
8 4 2 1 P1
8 4 2 1 P2
80 40 20 10 P3 8 4 2 1
minutes
hours
days
UTI UTI year sign correction
daylight savings time bits leap second warning bit leap year indicator bit "0" = non leap year "1" = leap year
93 7529 e
Example: UTC 18.42 h Time frame P0 seconds 0 1 40 20 10 2 3 4 5 8 6 4 7 2 8 1 P1 20 10 8 4 2 1 P2
9 10 11 12 13 14 15 16 17 18 19 20
hours
minutes Frame-reference marker Figure 25.
Modulation
The carrier amplitude is reduced by 10 dB at the beginning of each second and is restored within 500 ms (binary one) or within 200 ms (binary zero).
Time-Code Format
The time-code format consists of 1-minute time frames. A time frame contains BCD-coded information of minutes, hours, days and year. In addition, there are 6 position-identifier markers (P0 thru P5) and 1 frame-reference marker with reduced carrier amplitude of 800 ms duration.
14 (16)
Rev. A3, 03-Dec-98
T4225B
Information on the Japanese Transmitter
Station: JG2AS Frequency 40 kHz Transmitting power 10 kW Location: Sanwa, Ibaraki Geographical coordinates: 36_ 11' N, 139_ 51' E Time of transmission: permanent
Time frame 1 minute
(index count 1 second)
Time frame 40 45 50
P5
0
PO FRM 40 20 10
5
10
20 10
15
20
200 10 0
25
30
35
55
0
P0
5
10
minutes
hours
da ys code dut1
Example: 18.42 h Time frame P0 seconds 59 0 40 20 10 1 2 3 4 5
minutes Frame-reference marker (FRM) Position-identifier marker P0
8 6
ADD SUB ADD P4 8 4 2 1
8 4 2 1 P2
8 4 2 1 P1
80 40 20 10 P3 8 4 2 1
4 7
2 8
1 P1
20 10
8
4
2
1 P2
9 10 11 12 13 14 15 16 17 18 19 20
hours Position identifier marker P1
0.5 second: Binary one 0.8 second: Binary zero 0.2 second: Identifier markers P0...P5 0.5 s "1" 0.8 s "0" 0.2 s
93 7508 e
"P" Figure 26.
Modulation
The carrier amplitude is 100% at the beginning of each second and is switched off after 500 ms (binary one) or after 800 ms (binary zero).
Time-Code Format
The time-code format consists of 1-minute time frames. A time frame contains BCD-coded information of minutes, hours and days. In addition, there are 6 positionidentifier markers (P0 thru P5) and 1 frame-reference marker (FRM) with reduced carrier amplitude of 800 ms duration.
Rev. A3, 03-Dec-98
15 (16)
T4225B
Ozone Depleting Substances Policy Statement
It is the policy of TEMIC Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances ( ODSs). The Montreal Protocol ( 1987) and its London Amendments ( 1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2 . Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency ( EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C ( transitional substances ) respectively. TEMIC Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC Semiconductors products for any unintended or unauthorized application, the buyer shall indemnify TEMIC Semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 ( 0 ) 7131 67 2594, Fax number: 49 ( 0 ) 7131 67 2423
16 (16)
Rev. A3, 03-Dec-98

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