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DGK
D
P
SN65HVD3082E, SN75HVD3082E SN65HVD3085E, SN65HVD3088E
SLLS562C - MARCH 2003 - REVISED - JUNE 2004
LOW POWER RS 485 TRANSCEIVER Available in Small MSOP-8 Package
FEATURES D Available in Small MSOP-8 Package D Meets or Exceeds the Requirements of the
TIA/EIA-485A Standard
DESCRIPTION
These devices are half-duplex transceivers designed for RS-485 data bus networks. Powered by a 5-V supply, they are fully compliant with TIA/EIA-485A standard. With controlled transition times, these devices are suitable for transmitting data over long twisted-pair cables. SN65HVD3082E and SN75HVD3082E devices are optimized for signaling rates up to 200 kbps. SN65HVD3085E is suitable for data transmission up to 1 Mbps, whereas SN65HVD3088E is suitable for applications requiring signaling rates up to 20 Mbps. These devices are designed to operate with very low supply current, typically 0.3 mA, exclusive of the load. When in the inactive shutdown mode, the supply current drops to a few nanoamps, making these devices ideal for power-sensitive applications. The wide common-mode range and high ESD protection levels of these devices make them suitable for demanding applications such as energy meter networks, electrical inverters, status/command signals across telecom racks, cabled chassis interconnects, and industrial automation networks where noise tolerance is essential. These devices match the industry-standard footprint of SN75176. Power-on reset circuits keep the outputs in a highimpedance state until the supply voltage has stabilized. A thermal shutdown function protects the device from damage due to system fault conditions. The SN75HVD3082E is characterized for operation from 0C to 70C and SN65HVD308xE are characterized for operation from -40C to 85C air temperature.
D Low Quiescent Power
- 0.3 mA Active Mode - 1 nA Shutdown Mode
D D D D
1/8 Unit Load--Up to 256 Nodes on a Bus Bus-Pin ESD Protection Up to 15 kV Industry-Standard SN75176 Footprint Failsafe Receiver (Bus Open, Bus Shorted, Bus Idle)
APPLICATIONS D D D D D D D
Energy Meter Networks Motor Control Power Inverters Industrial Automation Building Automation Networks Battery-Powered Applications Telecommunications Equipment
ORDERING INFORMATION
TA 0C to 70C SIGNALING RATE (Mbps) 0.2 0.2 -40C to 85C 1 20 P SN75HVD3082EP Marked as 75HVD3082 SN65HVD3082EP Marked as 65HVD3082 PACKAGE TYPE D(1) SN75HVD3082ED Marked as VN3082 SN65HVD3082ED Marked as VP3082 SN65HVD3085ED Marked as VP3085 SN65HVD3088ED Marked as VP3088 DGK(2) SN75HVD3082EDGK Marked as NWM SN65HVD3082EDGK Marked as NWN SN65HVD3085EDGK Marked as NWK SN65HVD3088EDGK Marked as NWH
(1) The D package is available taped and reeled. Add an R suffix to the device type (i.e., SN65HVD3082EDR). (2) The DGK package is available taped and reeled. Add an R suffix to the device type (i.e., SN65HVD3082EDGKR).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
SN65HVD3082E, SN75HVD3082E SN65HVD3085E, SN65HVD3088E
SLLS562C - MARCH 2003 - REVISED - JUNE 2004
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1) (2) UNITS Supply voltage range, VCC Voltage range at A or B Voltage range at any logic pin Receiver output current Voltage input range, transient pulse, A and B, through 100 (see Figure 13) Junction temperature, TJ Continuous total power dissipation -0.5 V to 7 V -9 V to 14 V -0.3 V to VCC + 0.3 V -24 mA to 24 mA -50 V to 50 V 170C Refer to Package Dissipation Table
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
PACKAGE DISSIPATION RATINGS
PACKAGE D P DGK JEDEC BOARD MODEL Low k(1) High k(2) Low k(1) Low k(1) High k(2) TA <25C POWER RATING 507 mW 824 mW 686 mW 394 mW 583 mW DERATING FACTOR(3) ABOVE TA = 25C 4.82 mW/C 7.85 mW/C 6.53 mW/C 3.76 mW/C 5.55 mW/C TA = 70C POWER RATING 289 mW 471 mW 392 mW 255 mW 333 mW TA = 85C POWER RATING 217 mW 353 mW 294 mW 169 mW 250 mW
(1) In accordance with the low-k thermal metric definitions of EIA/JESD51-3 (2) In accordance with the high-k thermal metric definitions of EIA/JESDS1-7 (3) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
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SN65HVD3082E, SN75HVD3082E SN65HVD3085E, SN65HVD3088E
SLLS562C - MARCH 2003 - REVISED - JUNE 2004
RECOMMENDED OPERATING CONDITIONS(1)
MIN Supply voltage, VCC Input voltage at any bus terminal (separately or common mode), VI High-level input voltage (D, DE, or RE inputs), VIH Low-level input voltage (D, DE, or RE inputs), VIL Differential input voltage, VID Driver Output current, IO Differential load resistance, RL SN65HVD3082E, SN75HVD3082E Signaling rate, 1/tUI SN65HVD3085E SN65HVD3088E SN65HVD3082E, SN65HVD3085E, SN65HVD3088E Operating free-air temperature, TA SN75HVD3082E -40 0 Receiver 4.5 -7 2 0 -12 -60 -8 54 60 0.2 1 20 85 70 C C Mbps TYP MAX 5.5 12 VCC 0.8 12 60 8 mA UNIT V V V V V
Junction temperature, TJ(2) -40 130 (1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this data sheet. (2) See thermal characteristics table for information on maintenance of this specification for the DGK package.
SUPPLY CURRENT
over recommended operating conditions unless otherwise noted PARAMETER Driver and receiver enabled ICC Driver enabled, receiver disabled Receiver enabled, driver disabled D at VCC or open, D at VCC or open, D at VCC or open, TEST CONDITIONS DE at VCC, RE at 0 V, No load DE at VCC, RE at VCC, No load DE at 0 V, RE at 0 V, No load DE at 0 V, RE at VCC MIN TYP(1) 425 330 300 0.001 MAX 900 600 600 2 UNIT A A A A
Driver and receiver disabled D at VCC or open, (1) All typical values are at 25C and with a 5-V supply.
ELECTROSTATIC DISCHARGE PROTECTION
PARAMETER Human body model Human body model(2) All pins TEST CONDITIONS Bus terminals and GND MIN TYP(1) 15 4 1 MAX UNIT kV kV kV
(3) Charged-device-model All pins (1) All typical values at 25C (2) Tested in accordance with JEDEC Standard 22, Test Method A114-A. (3) Tested in accordance with JEDEC Standard 22, Test Method C101.
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SN65HVD3082E, SN75HVD3082E SN65HVD3085E, SN65HVD3088E
SLLS562C - MARCH 2003 - REVISED - JUNE 2004
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DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS IO = 0, No load RL = 54 , See Figure 1 RL = 100 VTEST = -7 V to 12 V, See Figure 2 See Figure 1 and Figure 2 See Figure 3 See Figure 3 High-impedance output current Input current See receiver input currents D, DE -7 V VO 12 V, See Figure 7 -100 -250 100 250 MIN 3 1.5 2 1.5 -0.2 1 -0.1 0 2.6 0 500 0.2 3 0.1 V mV A A mA V TYP(1) 4.3 2.3 V MAX UNIT
VOD
Differential output voltage
VOD VOC(SS) VOC(SS) VOC(PP) IOZ II
Change in magnitude of differential output voltage Steady-state common-mode output voltage Change in steady-state common-mode output voltage
IOS Short-circuit output current (1) All typical values are at 25C and with a 5V-supply.
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted PARAMETER tPLH tPHL Propagation delay time, low-to-high-level output Propagation delay time, high-to-low-level output TEST CONDITIONS RL = 54 , CL = 50 pF, See Figure 4 RL = 54 , CL = 50 pF, See Figure 4 RL = 54 , CL = 50 pF, See Figure 4 RL = 110 , , RE at 0 V, See Figure 5 and Figure 6 RL = 110 , , RE at 0 V, See Figure 5 and Figure 6 HVD3082E HVD3085E HVD3088E HVD3082E HVD3085E HVD3088E HVD3082E HVD3085E HVD3088E HVD3082E HVD3085E HVD3088E HVD3082E HVD3085E HVD3088E 500 MIN TYP 700 150 12 900 200 7 20 5 1.4 2500 1000 13 80 60 12 3500 2500 1600 MAX 1300 500 20 1500 300 15 200 50 5 7000 2500 30 200 100 30 7000 4500 2600 ns ns ns ns ns ns UNIT
tr tf
Differential output signal rise time Differential output signal fall time
tsk(p)
Pulse skew ( |tPHL - tPLH| )
tPZH tPZL
Propagation delay time, high-impedance-to-high-level output Propagation delay time, high-impedance-to-low-level output
tPHZ tPLZ
Propagation delay time, high-level-to-high-impedance output Propagation delay time, low-level-to-high-impedance output Propagation delay time, shutdown-to-high-level output Propagation delay time, shutdown-to-low-level output
tPZH(SHDN) tPZL(SHDN)
RL = 110 , RE HVD3082E HVD3085E at VCC, See Figure 5 HVD3088E
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SN65HVD3082E, SN75HVD3082E SN65HVD3085E, SN65HVD3088E
SLLS562C - MARCH 2003 - REVISED - JUNE 2004
RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted PARAMETER VIT+ VIT- Vhys VOH VOL IOZ Positive-going input threshold voltage Negative-going input threshold voltage Hysteresis voltage (VIT+ - VIT-) High-level output voltage Low-level output voltage High-impedance-state output current VID = 200 mV, IOH = -8 mA, See Figure 8 VID = -200 mV, IOH = 8 mA, See Figure 8 VO = 0 to VCC, RE= VCC VIH = 12 V, VCC = 5 V VIH = 12 V, VCC = 0 VIH = -7 V, VCC = 5 V VIH = -7 V, VCC = 0 VIH = 2 V VIL = 0.8 V VI = 0.4 sin (4E6t) + 0.5 V, DE at 0 V 4 -1 0.04 0.06 -0.1 -0.05 -60 -60 -0.04 -0.03 -30 -30 7 A A pF IO = -8 mA IO = 8 mA TEST CONDITIONS MIN -200 TYP(1) -85 -115 30 4.6 0.15 0.4 1 0.1 0.125 mA MAX -10 UNIT mV mV mV V V A
II
Bus input current
IIH IIL
High-level input current (RE) Low-level input current (RE)
Cdiff Differential input capacitance (1) All typical values are at 25C and with a 5-V supply.
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted PARAMETER tPLH Propagation delay time, low-to-high-level output RL = 54 , CL = 15 pF, See Figure 9 TEST CONDITIONS HVD3082E HVD3085E HVD3088E tPHL Propagation delay time, high-to-low-level output HVD3082E HVD3085E HVD3088E HVD3082E HVD3085E HVD3088E tr tf tPZH Output signal rise time Output signal fall time Output enable time to high level VID = -1.5 V to 1.5 V, CL = 15 pF, See Figure 9 HVD3082E HVD3085E HVD3088E tPZL Output enable time to low level HVD3082E HVD3085E HVD3088E HVD3082E HVD3085E HVD3088E tPLZ Output enable time from low level HVD3082E HVD3085E HVD3088E tPZH(SHDN) Propagation delay time, shutdown-to-high-level output tPZL(SHDN) Propagation delay time, shutdown-to-low-level output CL = 15 pF, DE at 0 V, See Figure 12 1600 1700 8 5 10 1.5 1.8 5 4 79 MIN TYP 75 MAX 200 100 200 100 30 10 3 3 50 30 50 30 50 30 50 30 3500 3500 ns ns ns ns ns ns ns ns ns ns UNIT ns
tsk(p)
Pulse skew ( |tPHL - tPLH| )
tPHZ
Output enable time from high level
CL = 15 pF, DE at 3 V, See Figure 10 and Figure 11
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SN65HVD3082E, SN75HVD3082E SN65HVD3085E, SN65HVD3088E
SLLS562C - MARCH 2003 - REVISED - JUNE 2004
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PARAMETER MEASUREMENT INFORMATION
NOTE:Test load capacitance includes probe and jig capacitance (unless otherwise specified). Signal generator characteristics: rise and
fall time < 6 ns, pulse rate 100 kHz, 50% duty cycle. ZO = 50 (unless otherwise specified).
II 0 V or 3 V D
A IOA VOD B IOB 50 pF
27 27 VOC
Figure 1. Driver Test Circuit, VOD and VOC Without Common-Mode Loading
375 IOA 0 V or 3 V IOB VOD 60 375 VTEST = -7 V to 12 V
VTEST
Figure 2. Driver Test Circuit, VOD With Common-Mode Loading
27 A D Signal Generator 50 B 27 50 pF VOC VOC VA VB VOC(PP) 3.25 V 1.75 V VOC(SS)
Figure 3. Driver VOC Test Circuit and Waveforms
3V INPUT RL = 54 Signal Generator CL = 50 pF 50 OUTPUT tr 0V 10% tf VOD(L) VOD tPLH 90% 1.5 V 1.5 V 0V tPHL VOD(H)
Figure 4. Driver Switching Test Circuit and Waveforms
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SN65HVD3082E, SN75HVD3082E SN65HVD3085E, SN65HVD3088E
SLLS562C - MARCH 2003 - REVISED - JUNE 2004
A 0 V or 3 V 3 V if Testing A Output 0 V if Testing B Output DE Signal Generator 50 D B
S1
Output DE 1.5 V 1.5 V 0.5 V
3V 0V VOH Output 2.5 V tPHZ VOff 0
CL = 50 pF
RL = 110
tPZH
Figure 5. Driver Enable/Disable Test Circuit and Waveforms, High Output
5V RL = 110 3V Output CL = 50 pF DE tPZL Output 1.5 V 1.5 V 0V tPLZ 2.5 V 0.5 V 5V VOL
A D 0 V or 3 V 0 V if Testing A Output 3 V if Testing B Output DE Signal Generator 50 B
S1
Figure 6. Driver Enable/Disable Test Circuit and Waveforms, Low Output
IOS VO Voltage Source IO VID VO
Figure 7. Driver Short-Circuit Test
Figure 8. Receiver Parameter Definitions
Signal Generator
50 VID A B R IO Input B Input A tPLH Output 90% 1.5 V tr tf 50% 0V tPHL VOH 10% V OL 1.5 V
Signal Generator
50
CL = 15 pF
VO
Figure 9. Receiver Switching Test Circuit and Waveforms
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SN65HVD3082E, SN75HVD3082E SN65HVD3085E, SN65HVD3088E
SLLS562C - MARCH 2003 - REVISED - JUNE 2004
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VCC VCC
D DE A 54 B 3V R RE 1 k CL = 15 pF tPZH 1.5 V tPHZ VOH VOH -0.5 V GND 0V RE 1.5 V 0V
Signal Generator
50 R
Figure 10. Receiver Enable/Disable Test Circuit and Waveforms, Data Output High
0V VCC D DE A 54 B 3V R RE Signal Generator 50 R 1.5 V 1 k CL = 15 pF tPZL tPLZ VCC VOL +0.5 V VOL 5V RE 1.5 V 0V
Figure 11. Receiver Enable/Disable Test Circuit and Waveforms, Data Output Low
VCC A R B 1 k CL = 15 pF RE Signal Generator 50 RE
1.5 V
Switch Down for V(A) = 1.5 V, Switch Up for V(A) = -1.5 V 3V
1.5 V or -1.5 V
0V tPZH(SHDN) tPZL(SHDN) 5V R 0V 1.5 V VOL VOH
Figure 12. Receiver Enable From Shutdown Test Circuit and Waveforms
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SN65HVD3082E, SN75HVD3082E SN65HVD3085E, SN65HVD3088E
SLLS562C - MARCH 2003 - REVISED - JUNE 2004
100 Pulse Generator, 15 s Duration, 1% Duty Cycle
VTEST 0V 15 s 1.5 ms -VTEST
Figure 13. Test Circuit and Waveforms, Transient Over-Voltage Test
DEVICE INFORMATION PIN ASSIGNMENTS
D, P OR DGK PACKAGE (TOP VIEW) D
LOGIC DIAGRAM (POSITIVE LOGIC)
4
R RE DE D
1 2 3 4
8 7 6 5
VCC B A GND
3 DE 2 RE R1 6 7 A B
FUNCTION TABLE
DRIVER INPUT D H L X Open X ENABLE DE H H L H Open OUTPUTS A H L Z H Z B L H Z L Z RECEIVER DIFFERENTIAL INPUTS VID = VA - VB VID -0.2 V -0.2 V < VID < -0.01 V -0.01 V VID X Open circuit Short circuit X NOTE: H= high level; L = low level; Z = high impedance; X = irrelevant; ? = indeterminate ENABLE RE L L L H L L Open OUTPUT R L ? H Z H H Z
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SN65HVD3082E, SN75HVD3082E SN65HVD3085E, SN65HVD3088E
SLLS562C - MARCH 2003 - REVISED - JUNE 2004
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EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
D and RE Input VCC 200 k 500 W DE Input VCC
Input
Input
500 W 200 k
9V
9V
A Input VCC 16 V 180 k Input 16 V 36 k Input 36 k 16 V
B Input VCC 36 k
180 k 36 k 16 V
A and B Outputs VCC 16 V VCC
R Outputs
5 Output 16 V Output
9V
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SN65HVD3082E, SN75HVD3082E SN65HVD3085E, SN65HVD3088E
SLLS562C - MARCH 2003 - REVISED - JUNE 2004
DGK Package
THERMAL CHARACTERISTICS
PARAMETER JA JB JC P(AVG) Junction-to-ambient thermal resistance(1) Junction-to-board thermal resistance Junction-to-case thermal resistance Average power dissipation RL = 54 , Input to D is a 200 kbps 50% duty cycle square wave Vcc at 5.5 V, TJ = 130C RL = 54 , Input to D is a 1 Mbps 50% duty cycle square wave Vcc at 5.5 V, TJ = 130C RL = 54 , Input to D is a 20 Mbps 50% duty cycle square wave Vcc at 5.5 V, TJ = 130C High k board model TA Ambient air temperature Low k board model HVD3082E TEST CONDITIONS Low-k(2) board, no air flow High-k(3) board, no air flow High-k(3) board, no air flow MIN TYP 266 180 108 66 203 MAX UNIT C/W C/W
mW
P(AVG)
Average power dissipation
HVD3085E
205
mW
P(AVG)
Average power dissipation
HVD3088E -40 -40
276 93 75
mW
C
TSD Thermal shut-down junction temperature 165 C (1) See TI application note literature number SZZA003, Package Thermal Characterization Methodologies, for an explanation of this parameter. (2) JESD51-3 Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (3) JESD51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
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SN65HVD3082E, SN75HVD3082E SN65HVD3085E, SN65HVD3088E
SLLS562C - MARCH 2003 - REVISED - JUNE 2004
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TYPICAL CHARACTERISTICS
BUS INPUT CURRENT vs BUS INPUT VOLTAGE
80 60 I I - Input Bias Current - A I CC - Supply Current - mA 10 No Load, VCC = 5 V TA = 25C 50% Square wave input SN65HVD3082E
RMS SUPPLY CURRENT vs SIGNALING RATE
40 20 0 VCC = 0 V VCC = 5 V
Driver and Receiver 1
-20 -40 -60 -8
Receiver Only
-6
-4
-2 0 2 4 6 VI - Bus Input Voltage - V
8
10
12
0.1 1 10 Signaling Rate - kbps 100
Figure 14
SN65HVD3085E
Figure 15
SN65HVD3088E
RMS SUPPLY CURRENT vs SIGNALING RATE
100 No Load, VCC = 5 V TA = 25C 50% Square wave input 10 100
RMS SUPPLY CURRENT vs SIGNALING RATE
No Load, VCC = 5 V TA = 25C 50% Square wave input 10 Driver and Receiver
I CC - Supply Current - mA
Driver and Receiver
1 Receiver Only
I CC - Supply Current - mA
1
Receiver Only 0.1 1 100 Signaling Rate - kbps 10 1000 0.1 0.001 0.010 0.100 1 10 100
Signaling Rate - Mbps
Figure 16
Figure 17
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SN65HVD3082E, SN75HVD3082E SN65HVD3085E, SN65HVD3088E
SLLS562C - MARCH 2003 - REVISED - JUNE 2004
TYPICAL CHARACTERISTICS
DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs DIFFERENTIAL OUTPUT CURRENT
5 4.5 VOD - Differential Output Voltage - V 4 3.5 3 2.5 2 1.5 1 0.5 0 0 10 20 30 40 IO - Differential Output Current - mA 50 RL = 60 TA = 25C VCC = 5 V 5 4.5 VO - Receiver Output Voltage - V RL = 120 4 3.5 3 2.5 2 1.5 1 0.5 0 -200 -180 -160 -140 -120 -100 -80 -60 -40 -20 VID - Differential Input Voltage - V 0 TA = 25C VCC = 5 V VIC = 0.75 V
RECEIVER OUTPUT VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE
Figure 18
Figure 19
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SLLS562C - MARCH 2003 - REVISED - JUNE 2004
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APPLICATION INFORMATION
RT
RT
NOTE: The line should be terminated at both ends with its characteristic impedance (RT = ZO). Stub lengths off the main line should be kept as short as possible.
Figure 20. Typical Application Circuit
POWER USAGE IN AN RS-485 TRANSCEIVER
Power consumption is a concern in many applications. Power supply current is delivered to the bus load as well as to the transceiver circuitry. For a typical RS-485 bus configuration, the load that an active driver must drive consists of all of the receiving nodes, plus the termination resistors at each end of the bus. The load presented by the receiving nodes depends on the input impedance of the receiver. The TIA/EIA-485-A standard defines a unit load as allowing up to 1 mA. With up to 32 unit loads allowed on the bus, the total current supplied to all receivers can be as high as 32 mA. The HVD308xE is rated as a 1/8 unit load device. As shown in Figure 14, the bus input current is less than 1/8 mA, allowing up to 256 nodes on a single bus. The current in the termination resistors depends on the differential bus voltage. The standard requires active drivers to produce at least 1.5 V of differential signal. For a bus terminated with one standard 120- resistor at each end, this sums to 25 mA differential output current whenever the bus is active. Typically the HVD308xE can drive more than 25 mA to a 60 load, resulting in a differential output voltage higher than the minimum required by the standard. (See Figure 16.) Overall, the total load current can be 60 mA to a loaded RS-485 bus. This is in addition to the current required by the transceiver itself; the HVD308xE circuitry requires only about 0.4 mA with both driver and receiver enabled, and only 0.3 mA with either the driver enabled or with the receiver enabled. In low-power shutdown mode, neither the driver nor receiver is active, and the supply current is very low. Supply current increases with signaling rate primarily due to the totum pole outputs of the driver (see Figure 15). When these outputs change state, there is a moment when both the high-side and low-side output transistors are conducting and this creates a short spike in the supply current. As the frequency of state changes increases, more power is used.
LOW-POWER SHUTDOWN MODE
When both the driver and receiver are disabled (DE low and RE high) the device is in shutdown mode. If the enable inputs are in this state for less than 60 ns, the device does not enter shutdown mode. This guards against inadvertently entering shutdown mode during driver/receiver enabling. Only when the enable inputs are held in this state for 300 ns or more, the device is assured to be in shutdown mode. In this low-power shutdown mode, most internal circuitry is powered down, and the supply current is typically 1 nA. When either the driver or the receiver is re-enabled, the internal circuitry becomes active. If only the driver is re-enabled (DE transitions to high) the driver outputs are driven according to the D input after the enable times given by tPZH(SHDN) and tPZL(SHDN) in the driver switching characteristics. If the D input is open when the driver is enabled, the driver outputs defaults to A high and B low, in accordance with the driver failsafe feature. If only the receiver is re-enabled (RE transitions to low) the receiver output is driven according to the state of the bus inputs (A and B) after the enable times given by tPZH(SHDN) and tPZL(SHDN) in the receiver switching characteristics. If there is no valid state on the bus the receiver responds as described in the failsafe operation section. If both the receiver and driver are re-enabled simultaneously, the receiver output is driven according to the state of the bus inputs (A and B) and the driver output is driven according to the D input. Note that the state of the active driver affects the inputs to the receiver. Therefore, the receiver outputs are valid as soon as the driver outputs are valid.
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THERMAL CHARACTERISTICS OF IC PACKAGES
JA (Junction-to-Ambient Thermal Resistance) is defined as the difference in junction temperature to ambient temperature divided by the operating power JA is NOT a constant and is a strong function of
D D D
the PCB design (50% variation) altitude (20% variation) device power (5% variation)
JA can be used to compare the thermal performance of packages if the specific test conditions are defined and used. Standardized testing includes specification of PCB construction, test chamber volume, sensor locations, and the thermal characteristics of holding fixtures. JA is often misused when it is used to calculate junction temperatures for other installations. TI uses two test PCBs as defined by JEDEC specifications. The low-k board gives average in-use condition thermal performance and consists of a single trace layer 25 mm long and 2-oz thick copper. The high-k board gives best case in-use condition and consists of two 1-oz buried power planes with a single trace layer 25 mm long with 2-oz thick copper. A 4% to 50% difference in JA can be measured between these two test cards JC (Junction-to-Case Thermal Resistance) is defined as difference in junction temperature to case divided by the operating power. It is measured by putting the mounted package up against a copper block cold plate to force heat to flow from die, through the mold compound into the copper block. JC is a useful thermal characteristic when a heatsink is applied to package. It is NOT a useful characteristic to predict junction temperature as it provides pessimistic numbers if the case temperature is measured in a non-standard system and junction temperatures are backed out. It can be used with JB in 1-dimensional thermal simulation of a package system. JB (Junction-to-Board Thermal Resistance) is defined to be the difference in the junction temperature and the PCB temperature at the center of the package (closest to the die) when the PCB is clamped in a cold-plate structure. JB is only defined for the high-k test card. JB provides an overall thermal resistance between the die and the PCB. It includes a bit of the PCB thermal resistance (especially for BGA's with thermal balls) and can be used for simple 1-dimensional network analysis of package system (see Figure 21).
Ambient Node qCA Calculated Surface Node qJC Calculated/Measured Junction qJB Calculated/Measured
PC Board
Figure 21. Thermal Resistance
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MECHANICAL DATA
MPDI001A - JANUARY 1995 - REVISED JUNE 1999
P (R-PDIP-T8)
0.400 (10,60) 0.355 (9,02) 8 5
PLASTIC DUAL-IN-LINE
0.260 (6,60) 0.240 (6,10)
1
4 0.070 (1,78) MAX 0.325 (8,26) 0.300 (7,62) 0.015 (0,38) 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.010 (0,25) NOM Gage Plane
0.020 (0,51) MIN
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M
0.430 (10,92) MAX
4040082/D 05/98 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
MECHANICAL DATA
MSOI002B - JANUARY 1995 - REVISED SEPTEMBER 2001
D (R-PDSO-G**)
8 PINS SHOWN 0.050 (1,27) 8 5 0.020 (0,51) 0.014 (0,35) 0.010 (0,25)
PLASTIC SMALL-OUTLINE PACKAGE
0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81)
0.008 (0,20) NOM
Gage Plane 1 A 4 0- 8 0.044 (1,12) 0.016 (0,40)
0.010 (0,25)
Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS ** DIM A MAX A MIN
8 0.197 (5,00) 0.189 (4,80)
14 0.344 (8,75) 0.337 (8,55)
16 0.394 (10,00) 0.386 (9,80)
4040047/E 09/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012
POST OFFICE BOX 655303
* DALLAS, TEXAS 75265
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