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Integrated Circuit Systems, Inc.
ICS843-106
106.25MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR
FEATURES
* One LVCMOS/LVTTL output, 15 output impedance One LVPECL output pair * Crystal oscillator interface designed for 25MHz, 18pF parallel resonant crystal * Output frequency: 106.25MHz * Random jitter: 3ps (typical) * Deterministic jitter: 0.24ps (typical) * 3.3V operating supply * 0C to 70C ambient operating temperature * Available in both standard and lead-free RoHS-compliant packages
GENERAL DESCRIPTION
The ICS843-106 is a Fibre Channel Dual Output Oscillator and a member of the HiPerClockSTM HiPerClocks TM family of high perfor mance devices from ICS. The ICS843-106 uses a 25MHz crystal to synthesize 106.25MHz. The ICS843-106 has excellent jitter performance. The ICS843-106 is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space.
IC S
BLOCK DIAGRAM
LVCMOS 106.25MHz 25MHz
PIN ASSIGNMENT
Q0 VCC XTAL_IN XTAL_OUT VEE 1 2 3 4 8 7 6 5 Q1 nQ1 VCCO Q0
XTAL_IN
Clock Synthesizer
LVPECL 106.25MHz
XTAL_OUT
Q1 nQ1
ICS843-106
8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View
ICS843-106
8-Lead SOIC 3.90mm x 4.92mm x 1.37mm body package M Package Top View
843AG-106
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REV. A JANUARY 10, 2006
Integrated Circuit Systems, Inc.
ICS843-106
106.25MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR
Type Power Input Power Description Positive supply pin. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Negative supply pin. Single-ended clock output. LVCMOS/LVTTL interface levels. 15 output impedance. Output supply pin. Differential LVPECL output pair.
TABLE 1. PIN DESCRIPTIONS
Number 1 2, 3 4 5 6 7, 8 Name VCC XTAL_IN, XTAL_OUT VEE Q0 VCCO nQ1, Q1
Output Power Output
TABLE 2. PIN CHARACTERISTICS
Symbol CIN ROUT Parameter Input Capacitance Output Impedance Q0 Test Conditions Minimum Typical 4 15 Maximum Units pF
843AG-106
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REV. A JANUARY 10, 2006
Integrated Circuit Systems, Inc.
ICS843-106
106.25MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR
4.6V -0.5V to VCC + 0.5 V -0.5V to VCCO + 0.5V 50mA 100mA NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, VO (LVCMOS) Outputs, IO (LVPECL) Continuous Current Surge Current Package Thermal Impedance, JA 8 Lead TSSOP 8 Lead SOIC Storage Temperature, TSTG 101.7C/W (0 mps) 112.7C/W (0 lfpm) -65C to 150C
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V0.3V, TA = 0C TO 70C
Symbol VCC VCCO IEE ICC ICCO Parameter Positive Supply Voltage Output Supply Voltage Power Supply Current Power Supply Current Output Supply Current Test Conditions Minimum 3.0 3.0 Typical 3.3 3.3 Maximum 3.6 3.6 116 96 24 Units V V mA mA mA
TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCO = 3.3V0.3V, TA = 0C TO 70C
Symbol VOH Parameter Output High Voltage; NOTE 1 Test Conditions Minimum 2.6 0.5 Typical Maximum Units V V
Output Low Voltage; NOTE 1 VOL NOTE 1: Outputs terminated with 50 to VCCO/2. See Parameter Measurement Information Section, "3.3V Output Load Test Circuit".
TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = VCCO = 3.3V0.3V, TA = 0C TO 70C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 0.9 VCCO - 1.7 1.0 Units V V V
NOTE 1: Outputs terminated with 50 to VCCO - 2V.
843AG-106
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REV. A JANUARY 10, 2006
Integrated Circuit Systems, Inc.
ICS843-106
106.25MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR
Test Conditions Minimum Typical Fundamental 25 30 30 18 15 1 MHz ppm ppm pF ppm mW Maximum Units
TABLE 4. CRYSTAL CHARACTERISTICS (NOTE 1)
Parameter Mode of Oscillation Frequency Frequency Tolerance Frequency Stability Over Operating Temperature Range Load Capacitance (CL); NOTE 2 Aging for 10 Years
Drive Level NOTE 1: Using an HC49/US SMD package, the parameters shown above target 100ppm accuracy. NOTE 2: See Cr ystal Input Interface in the Application Information Section.
TABLE 5. AC CHARACTERISTICS, VCC = VCCO = 3.3V0.3V, TA = 0C TO 70C
Symbol fOUT tDJ tRJ tRMS tp-p tOSC t R / tF Parameter Output Frequency Deterministic Jitter ; NOTE 1 Random Jitter ; NOTE 1 RMS of Total Distribution (); NOTE 2 Peak-to-Peak Jitter ; NOTE 1 Oscillation Star t Up Time Output Rise/Fall Time Q0 Q1/nQ1 20% to 80% 100 250 Test Conditions Minimum Typical 106.25 0.24 3 3.12 24 10 500 800 52 Maximum Units MH z ps ps ps ps ms ps ps %
odc Output Duty Cycle 48 NOTE 1: Measured using Wavecrest SIA-3000. NOTE 2: Measured using Wavecrest SIA-3000, Tj @ 10e-12BER result divided by 14.
843AG-106
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REV. A JANUARY 10, 2006
Integrated Circuit Systems, Inc.
ICS843-106
106.25MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR
PARAMETER MEASUREMENT INFORMATION
1.65V 0.15V 2V
VCC, VCCO
SCOPE
Qx
VCC, VCCO
Qx
SCOPE
LVCMOS
GND
LVPECL
nQx
VEE
-1.65V 0.15V
-1.3V 0.3V
3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT
V
CC
nQ1 Q1
t PW
t
PERIOD
Q0
t PW
t
2
PERIOD
odc =
t PW t PERIOD
x 100%
odc =
t PW t PERIOD
x 100%
LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
LVPECL OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
80% 20% tR
80% 20% tF
80% Clock Outputs
80% VSW I N G
Clock Outputs
20% tR tF
20%
LVCMOS OUTPUT RISE/FALL TIME
843AG-106
LVPECL OUTPUT RISE/FALL TIME
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REV. A JANUARY 10, 2006
Integrated Circuit Systems, Inc.
ICS843-106
106.25MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR APPLICATION INFORMATION
RECOMMENDATIONS FOR UNUSED OUTPUT PINS
LVCMOS OUTPUT: An unused LVCMOS output should be terminated with 100 to ground as close as possible to the device. LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
CRYSTAL INPUT INTERFACE
The ICS843-106 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 1 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
XTAL_OUT C1 12p X1 18pF Parallel Cry stal XTAL_IN C2 12p
Figure 1. CRYSTAL INPUt INTERFACE
843AG-106
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REV. A JANUARY 10, 2006
Integrated Circuit Systems, Inc.
ICS843-106
106.25MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR
crystal, see the application note, Crystal Timing Budget and Accuracy for FemtoClockTM .
FREQUENCY STABILITY
The table shown provides a basic guideline in selecting the proper quartz crystal that meets a timing budget of 100ppm. For more information on selecting the proper
Parameter Frequency Tolerance Frequency Stability Aging for 10 Years Accuracy of ICS Oscillator Load Capacitance Accuracy Total Overall Timing Error
Typical
30 30
Units ppm ppm ppm ppm ppm ppm
15 10 3 88
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines.Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
Zo = 50 FOUT FIN
Zo = 50 125
3.3V 125
Zo = 50 50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FOUT FIN
RTT =
Zo = 50 84 84
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
843AG-106
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REV. A JANUARY 10, 2006
Integrated Circuit Systems, Inc.
ICS843-106
106.25MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843-106. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843-106 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 0.3V = 3.6V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.6V * 116mA = 417.6mW Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 417.6mW + 30mW = 447.6mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5C/W per Table 6A below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.448W * 90.5C/W = 110.5C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6A. THERMAL RESISTANCE JA FOR 8-PIN TSSOP, FORCED CONVECTION
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 101.7C/W
1
90.5C/W
2.5
89.8C/W
TABLE 6B. THERMAL RESISTANCE JA FOR 8 LEAD SOIC FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W
200
128.5C/W 103.3C/W
500
115.5C/W 97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
843AG-106
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REV. A JANUARY 10, 2006
Integrated Circuit Systems, Inc.
3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 3.
VCC
ICS843-106
106.25MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR
Q1
VOUT RL 50 VCC - 2V
FIGURE 3. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = V (V
CCO_MAX
OH_MAX
=V
CC_MAX
- 0.9V
-V
OH_MAX
) = 0.9V =V - 1.7V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CC_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX - (VCC_MAX - 2V))/R ] * (VCC_MAX - VOH_MAX) = [(2V - (V _MAX - VOH_MAX))/R ] * (VCC_MAX - VOH_MAX) = L CC L [(2V - 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
843AG-106
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REV. A JANUARY 10, 2006
Integrated Circuit Systems, Inc.
ICS843-106
106.25MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR RELIABILITY INFORMATION
TABLE 7A. JAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 101.7C/W
1
90.5C/W
2.5
89.8C/W
TABLE 7B. JAVS. AIR FLOW TABLE 8 LEAD SOIC
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W
200
128.5C/W 103.3C/W
500
115.5C/W 97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS843-106 is: 2376
843AG-106
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REV. A JANUARY 10, 2006
Integrated Circuit Systems, Inc.
ICS843-106
106.25MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR
PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
TABLE 8A. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 2.90 6.40 BASIC 4.50 Millimeters Minimum 8 1.20 0.15 1.05 0.30 0.20 3.10 Maximum
TABLE 8B. PACKAGE DIMENSIONS
SYMBOL N A A1 B C D E e H h L 5.80 0.25 0.40 0 1.35 0.10 0.33 0.19 4.80 3.80 1.27 BASIC 6.20 0.50 1.27 8 Millimeters MINIMUM 8 1.75 0.25 0.51 0.25 5.00 4.00 MAXIMUM
Reference Document: JEDEC Publication 95, MS-012
Reference Document: JEDEC Publication 95, MO-153
843AG-106
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REV. A JANUARY 10, 2006
Integrated Circuit Systems, Inc.
ICS843-106
106.25MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR
Marking 3A106 3A106 TBD TBD TBD TBD TBD TBD Package 8 lead TSSOP 8 lead TSSOP 8 lead "Lead-Free" TSSOP 8 lead "Lead-Free" TSSOP 8 lead SOIC 8 lead SOIC 8 lead "Lead-Free" SOIC 8 lead "Lead-Free" SOIC Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel tube 2500 tape & reel tube 2500 tape & reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS843AG-106 ICS843AG-106T ICS843AG-106LF ICS843AG-106LFT ICS843AM-106 ICS843AM-106T ICS843AM-106LF ICS843AM-106LFT
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843AG-106
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REV. A JANUARY 10, 2006

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