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PD 6.070A
PRELIMINARY
IRPT5051
POWIRTRAINTM Integrated Power Stage for 15 hp Motor Drives
* 15 hp (11kW) power output * 380 - 480VAC; 50/60 Hz * Available as complete system or sub-system assemblies
Power Assembly
* * * * * * 3-phase rectifier bridge 3-phase ultrafast IGBT inverter NTC temperature sensor Pin-to-base plate isolation 2500 Vrms Easy-to-mount package Case temperature range -20C to 95C operational
Driver-Plus Board
* Capacitor filter with precharge current limit * Isolated gate drive circuits * On-board local power supply for gate driver and capacitor precharge control * MOV surge suppression at input * Isolated inverter current feedback * Short circuit, earth/ground fault, over-temperature protection * Input and output terminals; optional external brake * Control interface connector
380 - 480 V 3-phase input
IRPT5051C
POWIRTRAIN
driver power supply
variable frequency/ voltage
AC motor
POWIRTRAIN
isolated PWM signals
isolated power supply
isolated feedback
PWM signal generator
feedback processing
keyboard
External Control Functions Figure 1. The IRPT5051C POWIRTRAIN within a motor control system
Revised 11/5/96
page 1
IRPT5051
System Description
The IRPT5051C POWIRTRAIN provides the complete power conversion function for a 15hp (11kW) variable frequency AC motor controller. It contains a 3-phase input rectifier, DC link capacitor, 3-phase IGBT inverter, isolated gate drive circuits, shutdown protection, isolated trip and current feedback signals, and capacitor pre-charge function. Terminal blocks fitted to the POWIRTRAIN allow for end-user input and output connections. Output power is pulse-width modulated (PWM) 3-phase, variable frequency, variable voltage controlled by externally generated user-provided PWM logic input signals, which control the inverter stage - IGBT switching. The PWM input signal terminals and the output feedback signals are optically isolated from the power circuit. Figure 1 is a block diagram of the IRPT5051C POWIRTRAIN within an AC motor control system. Figure 4 shows the functions and architecture of the IRPT5051C. The IRPT5051C combines a lower Insulated Metal Substrate (IMS) power board, containing the power semiconductors and a thermistor, with the Driver-Plus Board. The power assembly is designed to be mounted to a heat sink. Figure 2 shows the IRPT5051A power assembly. The Driver-Plus Board interfaces electrically to the IRPT5051A power assembly via soldered connector pins. All external connections to the POWIRTRAIN are made to terminal blocks on the Driver-Plus Board (figure 3.) The IRPT5051C POWIRTRAIN offers several benefits to the motor control manufacturer: * It eliminates component selection, design layout, interconnection, gate drive, local power supply, thermal sensing, current sensing, and protection. * It provides committed power semiconductor losses and junction temperatures. * Parts inventory is reduced. * Gate drive and protection circuits are designed to closely match the operating characteristics of the power semiconductors. This allows power losses to be minimized and power rating to be maximized to a greater extent than is possible by designing with individual components. * Optimized layout for performance and efficiency is provided. * Low inductance system reduces noise and snubber requirements. * Manufacturing assembly is greatly simplified.
[POWIRTRAIN specifications and ratings are given for system input and output voltage and current, power losses and heat sink requirements over a range of operating conditions. POWIRTRAIN system ratings are verified by IR in final testing.]
inverter. A thermistor is included in the inverter section for thermal sensing. The power stage is designed to minimize inductance in the power path and reduce noise during inverter operation. The power level interfaces to the Driver-Plus Board through solder pins, minimizing assembly and alignment. The power assembly mounts to a heat sink with five screw mount positions, one in each corner and a fifth near the center to insure good thermal contact between the IMS and the heat sink. Wide copper traces on the IMS insure low impedance interconnects for the power components.
Figure 2. IRPT5051A Power Assembly
The IRPT5051D Driver-Plus Board
Figure 3 is a photograph of the IRPT5051D Driver-Plus Board containing the driver, sensing and protection functions. Figure 4 provides detailed functional block diagrams of the IRPT5051D. The switching power supply delivers a nominal 18V DC output, referenced to the negative DC bus, N. This feeds the gate drive, relay control and under voltage (UV) circuits, which are optically isolated from the control input section, and therefore require their own local power source. The gate drive circuits deliver on/off gate drive signals to the IGBTs' gates, corresponding with input PWM control signals IN1 through IN6. The PWM gate normally allows the input PWM control signals to pass to the input opto-isolators of the gate drive circuits. The conduction periods of the inverter switches essentially mimic those demanded by the PWM input signals. During power-up and power-down, or in the event of overcurrent (OI) or overtemperature (OT), the latch inhibits the PWM
The IRPT5051A IMS Power Assembly
The IRPT5051A Power Assembly, shown in figure 2, employs surface-mount 1600V rated D2Pak input rectifiers and surfacemount SMD-10 1200V IGBT Co-pack switches for the output
page 2
IRPT5051
gate, deactivating the gate drive circuits and shutting off the inverter. The relay control circuit delivers an on/off signal via an opto-isolator to the relay driver which controls the relay (K1). The relay contact is open during power-up, inserting the resistor R in series with the DC bus capacitor and limiting the capacitor charging current. In normal operation, the relay contact is closed. If the AC line voltage falls below 300V or if one input phase is lost, or if the DC line voltage falls to less than 82% of the peak line voltage, the relay contact opens. The UV circuit senses the voltage of the local power supply, and sends a signal via an opto-isolator to the latch in the event of undervoltage. The UV circuit normally activates the latch only during power-up and power-down, preventing the IGBTs from
being turned on when the local power supply voltage is too low for proper IGBT switching. The current signal processing circuit receives inputs from current transformers connected in series with the input lines and the DC bus capacitor. The output of the current signal processing circuit, IFB, is essentially an isolated replica of the inverter input current. An isolated current feedback signal, IFB, is provided as an output of the IRPT5051A. If the inverter current exceeds the trip level of 65A, IFB also activates the latch. The thermistor activates the latch if the temperature of the IMS substrate exceeds a set level. The 15V isolated power supply used to power the IRPT5051 should be the same as the one for the PWM gnereation, otherwise the protection functions will be disabled.
Figure 3. IRPT5051D Driver-Plus Board
page 3
IRPT5051
INPUT RECTIFIER P
IMS POWER BOARD Q1 THERMISTOR Q3
OUTPUT INVERTER Q5
Q2
Q4
Q6
RS T
RP P
RT1
RT2 N
G1 E1 G2 E2
G3 E3 G4 E4
G5 E5 G6 E6
U VW
RS T
RP P
RT1
RT2 N
G1 E1 G2 E2
G3 E3 G4 E4
G5 E5 G6 E6
U VW
PRECHARGER
DC LINK CAPS
LINE SENSE
CT
RELAY CONTACT (K1) CAP SENSE
SWITCHING POWER SUPPLY +18 GATE DRIVER CIRCUITS OPTO ISOLATION
RELAY CONTROL AND U/V OPTO ISOLATION
CT
CT
CURRENT SIGNAL PROCESSING
RELAY DRIVER AND RELAY COIL (K1)
LATCH OI, OT, UV
CT
PWM GATE
16 GND R S T POWER TB CN6A
19 20 17
15
7
89
SIGNAL TB 12 13 14 18
1
2
3
4
5
6 N PU V W
+15 COM
-15
IFB CN5
BUS SFT KIFB RIPPLE CHG
RESET OI OT UV
IN1 IN2
IN3 IN4 IN5 IN6 CN5
Driver - PlusBoard Driver-Plus Board
POWER TB CN6B
Figure 4. IRPT5051C Basic Architecture
page 4
IRPT5051
Specifications
PARAMETER Input Power
Voltage Frequency Input Current
VALUES
380V -15% to 480V +10%, 3-phase 50 - 60Hz 40A rms 300 A peak 0 - 480V rms 15hp (11kW) 25A rms
CONDITIONS
Output Power
TA = 40C, Rth SA = 0.075 C/W 10 ms half-cycle non-repetitive surge defined by external PWM control Vin = 440VAC PWM frequency = 4kHz, fo=60Hz, TA = 40C, Rth SA = 0.075 C/W
Voltage Nominal Motor hp (kW) Nominal Motor Current
DC Link
DC link voltage Control Power
Control Inputs
PWM input signals IN1 - IN6 Input resistance IN1 - IN6 Pulse deadtime Minimum input pulse duration Maximum pulse duration for each upper IGBT RESET SFT CHG
850V maximum 15V 5%, 200mA positive supply 15V 5%, 10mA, negative supply 15V, 10mA, 10% (max rise/fall time 150nsec) 720 5% 2.5 secs, minimum 1.0 sec 20ms 15V active high, CMOS input (min duration 1sec) 2 mA pull-down to energize relay (overrides internal control) 65A peak, 10% 100C, 5% 40A peak, 10% 1.5 sec typical 100mV/A 10% max. DC offset 200mV active high, 15V CMOS active high, 15V CMOS 15V high 4.7k pull-up, <0.5V low at 1.0mA; high-to-low transition at Vbus=82% peak of line voltage 15V high, 10k pull-up, during UV <0.5 low at 1mA with no UV 15V high when relay coil energized; low when relay coil de-energized measured from input line closure; line voltage > 300V pin to baseplate isolation M5 screw type 90%RH max. (non-condensing) 90%RH max. (non-condensing)
page 5
input signals uninhibited internally input signals inhibited internally
Protection
Output current trip level Overtemperature trip level Ground current trip level Short circuit shutdown time
Feedback Signals
output terminals shorted
Current feedback signal, IFB Overcurrent trip signal, OI Overtemp trip signal, OT BUS RIPPLE UV Relay coil feedback, K1FB
Capacitor Precharge Module
DC bus capacitor precharge time 400msecs max
Isolation Voltage Operating Case Temperature Mounting Torque
System Environment
2500VRMS, 60Hz, 1 minute -20C to 95C 5 N-m
Ambient Operating Temp. Range 0 to 40C Storage Temp. range -20 to 60C
IRPT5051
0 .14 4 00
Thermal Resistance (RthS-AC/W)
3 00
0 .1 2 50
0 .08
Power, 100% output current
RthSA 3 Hz min
2 00
0 .06 1 50 0 .04
0 .02
RthSA 1.5 Hz min Note: RthSA is for 100% current
1 00
50
0 1 2
0
PWM Frequency (kHz)
3
4
5
Figure 5a. 15hp/25A output Heat Sink Thermal Resistance and Power Dissipation vs. PWM Frequency
Operating Conditions: Vin=440Vrms, MI=1.15, PF=0.8, TA=40C, ZthSA limits temperature rise (Tc) during 1 minute overload to 10C
0 .25 4 00
3 50
Thermal Resistance (RthS-AC/W)
10 hp (7.5kW)
0 .15
3 00
Power, 150% output current RthSA 3 Hz min Power, 100% output current
2 50
2 00
0 .1
1 50
1 00 0 .05
Note: RthSA is for 150% current
0 1 2
RthSA 1.5 Hz min
3 4 5
50
0
page 6
Figure 5b. 10hp/16.5A output Heat Sink Thermal Resistance and Power Dissipation vs. PWM Frequency
PWM Frequency (kHz)
Total Power Dissipation (Watts)
0 .2
Total Power Dissipation (Watts)
0 .12
15 hp (11kW)
3 50
IRPT5051
0.4 300
0.35
7.5 hp (5.5kW)
Total Power Dissipation (Watts)
page 7
250
Thermal Resistance (RthS-AC/W)
0.3
0.25
RthSA 3 Hz min Power, 150% output current
200
0.2
150
0.15
0.1
Power, 100% output current
RthSA 1.5 Hz min
100
50 0.05
0
Note: RthSA is for 150% current
1 2
0 3 4 5 6
Figure 5c. 7.5hp/12A output Heat Sink Thermal Resistance and Power Dissipation vs. PWM Frequency
0 .6 300
PWM Frequency (kHz)
5 hp (3.65kW)
Thermal Resistance (RthS-AC/W) Total Power Dissipation (Watts)
0 .5 250
0 .4
200
Power, 150% output current
0 .3 150
0 .2
RthSA 3 Hz min Power, 100% output current Note: RthSA is for 150% current RthSA 1.5 Hz min
PWM Frequency (kHz)
8 10 12 14
100
0 .1
50
0 2 4 6
0
Figure 5d. 5hp/8.4A output Heat Sink Thermal Resistance and Power Dissipation vs. PWM Frequency
IRPT5051
Mounting, Hookup and Application Instructions
Mounting
Unless supplied connected, first connect the IRPT5051D and the IRPT5051A power assembly. 1. Remove all particles and grit from the heat sink and power substrate. 2. Spread a .004" to .005" layer of silicone grease on the heat sink, covering the entire area that the power substrate will occupy. 3. Place the power substrate onto the heat sink with the mounting holes aligned and press it firmly into the silicone grease. 4. Place the 5 M5 mounting screws through the PCB and power substrate and into the heat sink and tighten with fingers.
Control Connections
All input and output control connections are made via a female connector to CN6.
Power Connections
3-phase input connections are made to terminals R,S and T. Inverter output terminal connections are made to terminals U,V and W. Positive and negative dc bus connections are brought out to terminals P (positive) and N (negative). An external braking circuit can be connected across terminals P and N.
Logic Sequence During Power-Up
When 3-phase input power is first switched on, PWM inputs to the IRPT5051 must be inhibited until all the following logic conditions are met: 1. external 15V supply is established 2. UV feedback signal is low, indicating local power supply for gate drive circuits is established 3. K1FB signal is high, indicating capacitor precharge relay is energized. When these conditions are simultaneously met, a 15V RESET pulse should be applied to the RESET input. PWM input signals can now be released to the IRPT5051. The first PWM input signal to each of the lower IGBT inputs (IN2, IN4, IN6) should have at least 50s duration, to allow the bootstrap capacitors to charge.
Figure 6. Power Assembly Mounting Screw Sequence 5. Tighten the screws to 2 Nm torque, according to the sequence shown below. 6. Re-tighten the screws to 4-5 Nm using the same sequence as in step 5.
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5
2
1
4
3
Logic Sequence During Power-Down
The following sequence is recommended for normal power down: 1. reduce motor speed to zero by PWM control 2. inhibit PWM inputs 3. disconnect main power.
Figure 7a. Control Signal Connector
Figure 7b. Input and Output Terminal Blocks
IRPT5051
IRPT5051D Mechanical Specifications
NOTE: Dimensions are in inches (millimeters)
10.000 [254.0]
1.900 [48.26] 20-11 CN5 PCB 1-10 HEATSINK + CAPACITOR
5.850 [148.59]
POWER ASSEMBLY CAPACITOR CN6A CN6B +
GND 1.20 [30.48]
R
S
T
U
V
W
N
P
3.90 [99.06] 7.875 [200.03]
7X .500 [12.7] 1.250 [31.75]
2.035 [51.69] MAX.
CN6A
CN6B
POWER ASSEMBLY HEATSINK
3.000 [76.2]
.475 [12.07]
CAPACITOR AIR FLOW
2X
3.000 [76.2]
5.500 [139.7]
FAN
page 9
7.060 [179.32]
6.000 [152.4]
IRPT5051
IRPT5051A Mechanical Specifications
NOTE: Dimensions are in inches (millimeters)
5.300 [134.62]
CN2
CN1
S
G
RT1
S
G
S
G
Q1
Q3
Q5
D1
A
D2
A
E
E
E
E
E
E
3.700 [93.98]
CN3
D3
A
D4
A
S
G
S
G
S
G
CN4
Q2 D5
A
Q4
Q6
D6
A
E
E
E
E
E
E
.500 [12.7] MAX.
2.769 [70.333] 2.869 [72.873] 2.969 [75.413]
1.069 [27.153] 1.169 [29.693] 1.269 [32.233] 1.369 [34.773] 1.469 [37.313] 1.569 [39.853] 1.669 [42.393] 1.769 [44.933] 1.869 [47.473]
2.269 [57.633] 2.369 [60.173]
3.969 [100.813] 4.069 [103.353] 4.169 [105.893]
3.369 [85.573]
3.469 [88.113]
.250 [6.350] THRU HOLES 5X
CONNECTOR CLEARANCE BOTTOM SIDE ONLY 4X
3.450 [87.630]
CN2 CN1
B A
3.550 [90.170] 3.350 [85.090]
123456 78 12 13 17 18 19 23 24 29 30
3.075 [78.105] 2.975 [75.565] 2.875 [73.025] 2.775 [70.485] 2.675 [67.945]
1 2 3 4
.050 [1.27] 83X CN4
2.375 [60.325] 2.275 [57.785] 2.175 [55.245] 1.954 [49.632]
7 8 9 1 56 10 14 15 19 23 24
B 1 2 3 4
A
2.350 [5.690] 2.250 [57.150] 2.150 [54.610] 2.050 [52.070] 1.950 [49.530] 1.854 [47.092] 1.754 [44.552] 1.650 [41.910] 1.550 [39.370] 1.450 [36.830] 1.350 [34.290] 1.250 [31.750]
CN3 1.654 [42.012] 1.575 [40.005] 1.475 [37.465] 1.375 [34.925]
15 16 17
A B 7 8 9 10
.875 [22.225] .775 [19.685] .675 [17.145] .575 [14.605]
22 23 24
.250 [6.350] .000 SUPPORT & SCREW CLEARANCE .250 [ 6.350] R TOP & BOTTOM SIDES
.250 [6.350]
2.945 [78.803]
3.069 [77.953]
3.569 [90.653]
NOTES: 1. MATERIAL: FR4, .065 [1.651]THICK MAX.
page 10
Driver-Plus Board Hole Position and Sizes for Power Assembly
4.860 [123.444] 4.960 [125.984] 5.050 [128.27] 5.060 [128.524] 5.160[131.064]
.850 [21.590] .950 [24.130] 1.050 [26.670] 1.150 [29.210]
2.569 [65.253] 2.669 [67.793]
2.069 [52.553] 2.169 [55.093]
4.369 [110.973] 4.469 [113.513]
4.669 [118.593]
.000
5X
5X
IRPT5051
Part Number Identification and Ordering Instructions
IRPT5051A Power Assembly
IMS assembly incorporating 1600V input rectifiers in D 2Paks, 1200V ultra-fast IGBT inverter with ultra-fast freewheeling diodes in SMD10 packages, along with a temperature sensing thermistor. The assembly is fully tested to meet all data sheet specifications.
IRPT5051D Driver-Plus Board
Printed circuit board assembled with DC link capacitors, relay in-rush circuit, high power terminal blocks, surge suppression MOVs, IGBT gate drivers, protection circuitry and low power supply. The PCB is functionally tested with standard power assembly to meet all system specifications.
IRPT5051C Complete POWIRTRAIN
Power Assembly (IRPT5051A) and Driver-Plus Board (IRPT5051D) pre-assembled and tested to meet all system specifications.
IRPT5051E Design Kit
Complete POWIRTRAIN (IRPT5051C) with full set of design documentation, including schematic diagram. bill of material, mechanical layout, schematic file, Gerber files and design tips.
Functional Information
Capacitor Precharge
When the input line voltage is first switched on, the charging current of the dc bus capacitors is limited by a 100 Ohm precharge resistor. When the bus capacitor has charged to approximately 85% of the peak line voltage, the capacitor precharge control circuit energizes the relay K1, bypassing the 100 pre-charge resistor, so long as the line voltage exceeds 300V rms and all three input phase voltages are present. The relay feedback signal, K1FB is the voltage across the relay coil. This is 15V high when the relay is energized, and low when the relay is de-energized. At start-up, the input PWM signals should be inhibited externally until K1FB becomes high, since if the inverter is operated before the pre-charge resistor is bypassed, this resistor will be overloaded. The relay will drop out during operation if the dc bus voltage falls to less than 82% of the peak line voltage; if one or more input line voltages is lost; or if the input voltage falls below 300V. K1FB then becomes low and the PWM input signals should be inhibited externally to avoid overloading the pre-charge resistor. The BUS RIPPLE feedback signal is high when the relay is de-energized, and low when it is energized. If one of the input phases is lost, the relay drops out and the BUS RIPPLE signal oscillates from high to low at line frequency. The relay can be energized, if required, during single-phase operation by pulling down the SFT CHG terminal via an external open-collector transistor. The pull-down current is 2mA. The `lower' bus capacitor is discharged by a 10K resistor until its voltage reaches approximately 80V. Thereafter, discharge of the `lower' capacitor is via a 110k resistor.
Undervoltage
The undervoltage circuit monitors the voltage of the local gate driver power supply and sends a high input signal during undervoltage which sets the latch and inhibits the PWM input signals. This signal, brought out on pin 18 of CN5, is high during undervoltage. After it has gone low during power-up, a 15V RESET signal must be applied to reset the latch and allow the PWM input signals to pass to the gate drive circuits. PWM input signals must be 15V positive logic. They must source 10mA into the opto-isolators of the IGBT gate driver circuits. When inhibited by the internal PWM gate during power up, power down and fault conditions, each PWM input signal becomes loaded by a 720 Ohm resistor. Maximum rise and fall times of the PWM input signals should be 150 nsecs. Minimum dead time between outgoing and incoming PWM signals to the IGBTs in a given inverter leg should be 2.5secs. This is necessary to avoid inverter shoot-through. The minimum duration of any PWM input pulse should be 1sec. Typical propagation delay between the PWM input and drive output at the gate of the IGBT is 300ns.
Discharging the Bus Capacitors
When the input power is switched off, the `top' bus capacitor is discharged by a 10k resistor.
Bootstrap Supplies for the Gate Drive Circuits
The gate drive circuits for the upper IGBTs are powered from floating bootstrap capacitors. Each bootstrap capacitor is
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IRPT5051
charged via the corresponding lower IGBT when this is switched on. Prior to initial application of the PWM input signals at startup, the bootstrap capacitors are uncharged. Thus, an upper IGBT will not be turned on until after the corresponding lower IGBT has first been turned on to charge the bootstrap capacitor for the upper IGBT. The minimum initial conduction period of each lower IGBT at start-up should be about 50sec, to allow sufficient time for initial charging of the bootstrap capacitors. In normal operation, the bootstrap capacitor maintains adequate gate drive voltage for a period of 20 milliseconds. The maximum duration of the PWM input pulses (1N1, 1N3 and 1N5) should not exceed this period. Peak line-to-line fault current in excess of a nominal value of 65A and peak line-to-ground current in excess of 40A sets the latch and internally inhibits the IGBT gate drive. The overcurrent feedback signal, OI, simultaneously goes high. Reaction time to a bolted short circuit is typically about 1sec. The LED1 lights up when any of the fault signals (UV, OI, OT) set the latch, indicating a fault condition. When the RESET signal is applied to the latch, the LED1 goes OFF if the fault that is setting the latch clears. The internal PWM inhibit condition is cleared by applying 15V signal to the RESET terminal for a minimum period of 1 microsecond.
Heat Sink Requirements
Figures 5a through 5d (pp. 6-7) show the thermal resistance of the heat sink required for various output power levels and PWM switching frequencies. Maximum total losses of the unit are also shown. This data is based on the following key operating conditions: q The maximum continuous combined losses of the rectifier and inverter occur at full pulse-width modulation. These maximum losses set the maximum continuous operating temperature of the heat sink. q The maximum combined losses of the rectifier and inverter at full pulse-width modulation under overload set the incremental temperature rise of the heat sink during overload. q The minimum output frequency at which full overload current is to be delivered sets the peak IGBT junction temperatures. At low output frequency IGBT junction temperature tends to follow the instantaneous fluctuations of the output current. Thus, peak junction temperature rise increases as output frequency decreases.
Voltage Rise During Braking
The motor will feed energy back to the dc link during electrical braking, forcing the dc bus voltage to rise above the level defined by the input line voltage. Deceleration of the motor must be controlled by appropriate PWM control to keep the dc bus voltage within the rated maximum value of 850V. An external dissipative braking circuit, which keeps the bus voltage within the rated value, can be connected across the P and N terminals if required. t
Overtemperature Trip
If the temperature of the IMS substrate exceeds a nominal value of 100C, the overtemperature circuit sets the latch and internally inhibits the PWM input signals. The overtemperature feedback signal, OT, simultaneously goes high. The internal PWM inhibit condition is cleared by applying a 15V signal to the RESET terminal for a minimum period of 1 microsecond.
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331 EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020 IR CANADA: 7321 Victoria Park Ave., Suite 201, Markham, Ontario L3R 2Z8, Tel: (905) 475 1897 IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590 IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111 IR FAR EAST: K&H Bldg., 2F, 3-30-4 Nishi-Ikeburo 3-Chome, Toshima-Ki, Tokyo Japan 171 Tel: 81 3 3983 0086 IR SOUTHEAST ASIA: 315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 0316 Tel: 65 221 8371 http://www.irf.com/ Data and specifications subject to change without notice. 11/96
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