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K4D64163HF
64M DDR SDRAM
64Mbit DDR SDRAM
1M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM
Revision 1.1 August 2002
Samsung Electronics reserves the right to change products or specification without notice.
-1-
Rev. 1.1(Aug. 2002)
K4D64163HF
Revision History
Revision 1.1 (August 6, 2002)
* Typo corrected
64M DDR SDRAM
Revision 1.0 (June 17, 2002)
* Defined DC spec
Revision 0.1 (May 20, 2002) - Target Spec
* Typo corrected
Revision 0.0 (April 30, 2002) - Target Spec
* Defined Target Specification
-2-
Rev. 1.1(Aug. 2002)
K4D64163HF
1M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL FEATURES
* 3.3V + 5% power supply for device operation * 2.5V + 5% power supply for I/O interface * SSTL_2 compatible inputs/outputs * 4 banks operation * MRS cycle with address key programs -. Read latency 3 (clock) -. Burst length (2, 4 and 8) -. Burst type (sequential & interleave) * All inputs except data & DM are sampled at the positive going edge of the system clock * Differential clock input * No Wrtie-Interrupted by Read Function * 2 DQS's ( 1DQS / Byte )
64M DDR SDRAM
* Data I/O transactions on both edges of Data strobe * DLL aligns DQ and DQS transitions with Clock transition * Edge aligned data & data strobe output * Center aligned data & data strobe input * DM for write masking only * Auto & Self refresh * 64ms refresh period (4K cycle) * 66pin TSOP-II * Maximum clock frequency up to 300MHz * Maximum data rate up to 600Mbps/pin
ORDERING INFORMATION
Part NO. K4D64163HF-TC33 K4D64163HF-TC36 K4D64163HF-TC40 K4D64163HF-TC50 K4D64163HF-TC60 Max Freq. 300MHz 275MHz 250MHz 200MHz 166MHz Max Data Rate 600Mbps/pin 550Mbps/pin 500Mbps/pin 400Mbps/pin 333Mbps/pin SSTL_2 66 pin TSOP-II Interface Package
GENERAL DESCRIPTION
FOR 1M x 16Bit x 4 Bank DDR SDRAM
The K4D64163H is 67,108,864 bits of hyper synchronous data rate Dynamic RAM organized as 4 x1,048,576 words by 16 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 1.2GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.
-3-
Rev. 1.1(Aug. 2002)
K4D64163HF
PIN CONFIGURATION (Top View)
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NC LDM WE CAS RAS CS NC BA0 BA1 AP/A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM CK CK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS
64M DDR SDRAM
66 PIN TSOP(II) (400mil x 875mil) (0.65 mm Pin Pitch)
57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
PIN DESCRIPTION
CK,CK CKE CS RAS CAS WE LDQS,UDQS LDM,UDM Differential Clock Input Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Data Strobe Data Mask BA0, BA1 A0 ~A11 DQ0 ~ DQ15 VDD VSS VDDQ VSSQ NC Bank Select Address Address Input Data Input/Output Power Ground Power for DQ's Ground for DQ's No Connection
-4-
Rev. 1.1(Aug. 2002)
K4D64163HF
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol CK, CK*1 Input Type Function
64M DDR SDRAM
The differential system clock Input. All of the inputs are sampled on the rising edge of the clock except DQ's and DM's that are sampled on both edges of the DQS. Activates the CK signal when high and deactivates the CK signal when low. By deactivating the clock, CKE low indicates the Power down mode or Self refresh mode. CS enables the command decoder when low and disabled the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Latches row addresses on the positive going edge of the CK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Data Strobe : Output with read data, input with write data. Edgealigned with read data, centered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS corresponds to the data on DQ8-DQ15. Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. DM pins include dummy loading internally, to matches the DQ and DQS loading. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM correspons to the data on DQ8-DQ15. Data inputs/Outputs are multiplexed on the same pins. Selects which bank is to be active. Row/Column addresses are multiplexed on the same pins. Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA7. Power and ground for the input buffers and core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. Reference voltage for inputs, used for SSTL interface. This pin is recommended to be left "No connection" on the device
CKE
Input
CS
Input
RAS CAS WE
Input Input Input
LDQS,(U)DQS
Input/Output
LDM,UDM
Input
DQ0 ~ DQ15 BA0, BA1 A0 ~ A11 VDD/VSS VDDQ/VSSQ VREF NC/RFU
Input/Output Input Input Power Supply Power Supply Power Supply No connection/ Reserved for future use
*1 : The timing reference point for the differential clocking is the cross point of CK and CK. For any applications using the single ended clocking, apply VREF to CK pin.
-5-
Rev. 1.1(Aug. 2002)
K4D64163HF
BLOCK DIAGRAM (1Mbit x 16I/O x 4 Bank)
64M DDR SDRAM
16
Intput Buffer I/O Control LWE LDMi
CK, CK Bank Select
Data Input Register Serial to parallel
1Mx16 Output Buffer 2-bit prefetch Sense AMP Refresh Counter Row Buffer Row Decoder 1Mx16 1Mx16 1Mx16
32 16
x16
DQi
Address Register
CK,CK
ADDR
Column Decoder LRAS LCBR Col. Buffer
Latency & Burst Length Strobe Gen. Data Strobe
Programming Register LCKE LRAS LCBR LWE LCAS LWCBR
DLL
CK,CK
LDMi
Timing Register
CK,CK
CKE
CS
RAS
CAS
WE
LDM
UDM
-6-
Rev. 1.1(Aug. 2002)
K4D64163HF
FUNCTIONAL DESCRIPTION
* Power-Up Sequence
64M DDR SDRAM
DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply VDD before VDDQ . - Apply VDDQ before VREF & VTT 2. Start clock and maintain stable condition for minimum 200us. 3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high . 4. Issue precharge command for all banks of the device. 5. Issue a EMRS command to enable DLL *1 6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL. *1,2 7. Issue precharge command for all banks of the device. 8. Issue at least 2 or more auto-refresh commands. 9. Issue a mode register set command with A8 to low to initialize the mode register. *1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL. *2 Sequence of 6&7 is regardless of the order.
Power up & Initialization Sequence
0 CK,CK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
~
~~
Command
~
precharge ALL Banks
EMRS
MRS DLL Reset
precharge ALL Banks
1st Auto Refresh
2nd Auto Refresh
~~
tRP
2 Clock min.
2 Clock min.
tRP
tRFC
tRFC
~
2 Clock min.
Mode
Register Set
Any Command
Inputs must be stable for 200us
~
200 Clock min.
-7-
Rev. 1.1(Aug. 2002)
K4D64163HF
MODE REGISTER SET(MRS)
64M DDR SDRAM
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of address pins A0 ~ A11 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the mode register. Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test mode. A8 is used for DLL reset. A7,A8, BA0 and BA1 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies. BA1 RFU BA0 0 A11 A10 RFU A9 A8 DLL A7 TM A6 A5 A4 A3 BT A2 A1 Burst Length A0 Address Bus
CAS Latency
Mode Register
DLL A8 0 1 DLL Reset No Yes
Test Mode A7 0 1 mode Normal Test
Burst Type A3 0 1 Type Sequential Interleave Burst Length
CAS Latency BA0 0 1 An ~ A0 MRS EMRS A6 0 0 0 0 * RFU(Reserved for future use) should stay "0" during MRS cycle. 1 1 1 1 MRS Cycle
0 CK, CK Command
NOP Precharge All Banks NOP NOP MRS
A2 Latency Reserved Reserved Reserved 3 Reserved Reserved Reserved Reserved 0 0 0 0 1 1 1 1
A1 0 0 1 1 0 0 1 1
A0 0 1 0 1 0 1 0 1
Burst Type Sequential Reserve 2 4 8 Reserve Reserve Reserve Reserve Interleave Reserve 2 4 8 Reserve Reserve Reserve Reserve
A5 0 0 1 1 0 0 1 1
A4 0 1 0 1 0 1 0 1
1
2
3
4
5
6
7
8
NOP
Any Command
NOP
NOP
tRP
tMRD=2 tCK
*1 : MRS can be issued only at all banks precharge state. *2 : Minimum tRP is required to issue MRS command. -8-
Rev. 1.1(Aug. 2002)
K4D64163HF
EXTENDED MODE REGISTER SET(EMRS)
64M DDR SDRAM
The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore the extened mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0, A2 ~ A5, A7 ~ A11 and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. A1 and A6 are used for setting driver strength to normal, weak or matched impedance. Two clock cycles are required to complete the write operation in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address pins except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes.
BA1 RFU
BA0 1
A11
A10
A9 RFU
A8
A7
A6 D.I.C
A5
A4 RFU
A3
A2
A1 D.I.C
A0 DLL
Address Bus Extended Mode Register
BA0 0 1
An ~ A0 MRS EMRS
A6 0 1
A1 1 1
Output Driver Impedence Control Weak Matched
A0 0 1
DLL Enable Enable Disable
*1 : RFU(Reserved for future use) should stay "0" during EMRS cycle.
-9-
Rev. 1.1(Aug. 2002)
K4D64163HF
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD VDDQ TSTG PD IOS Value -0.5 ~ 3.6 -1.0 ~ 3.6 -0.5 ~ 3.6 -55 ~ +150 1.0 50
64M DDR SDRAM
Unit V V V C W mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 65C)
Parameter
Device Supply voltage Output Supply voltage Reference voltage Termination voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Output leakage current
Symbol
VDD VDDQ VREF Vtt VIH(DC) VIL(DC) VOH VOL IIL IOL
Min
3.135 2.375 0.49*VDDQ VREF-0.04 VREF+0.15 -0.30 Vtt+0.76 -5 -5
Typ
3.3 2.50 VREF -
Max
3.465 2.625 0.51*VDDQ VREF+0.04 VDDQ+0.30 VREF-0.15 Vtt-0.76 5 5
Unit
V V V V V V V V uA uA
Note
1 1 2 3 4 5 IOH=-15.2mA IOL=+15.2mA 6 6
Note : 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VREF is expected to equal 0.50*VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to peak noise on the VREF may not exceed + 2% of the DC value. Thus, from 0.50*VDDQ, VREF is allowed + 25mV for DC error and an additional + 25mV for AC noise. 3. Vtt of the transmitting device must track VREF of the receiving device. 4. VIH(max.)= VDDQ +1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 5. VIL(mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 6. For any pin under test input of 0V < VIN < VDD is acceptable. For all other pins that are not under test VIN=0V.
- 10 -
Rev. 1.1(Aug. 2002)
K4D64163HF
DC CHARACTERISTICS
Recommended operating conditions Unless Otherwise Noted, TA=0 to 65C)
64M DDR SDRAM
Version Parameter Operating Current (One Bank Active) Precharge Standby Current in Power-down mode Precharge Standby Current in Non Power-down mode Active Standby Current power-down mode Active Standby Current in in Non Power-down mode Operating Current ( Burst Mode) Refresh Current Self Refresh Current Symbol Test Condition -33 ICC1 ICC2P ICC2N ICC3P ICC3N ICC4 ICC5 ICC6 Burst Lenth=2 tRC tRC(min) -36 200 -40 190 5 110 110 160 390 210 105 105 150 370 200 95 95 140 350 190 2 80 80 120 320 180 70 70 100 300 170 -50 170 -60 160 mA mA mA mA mA mA mA mA 2 1 Unit Note
IOL=0mA, tCC= tCC(min)
CKE VIL(max), tCC= tCC(min) CKE VIH(min), CS VIH(min),
210
tCC= tCC(min)
CKE VIL(max), tCC= tCC(min) CKE VIH(min), CS VIH(min),
tCC= tCC(min) tRC tRFC(min)tRC tRFC(min) Page Burst, All Banks activated. tRC tRFC(min)
CKE 0.2V
Note : 1. Measured with outputs open. 2. Refresh period is 64ms.
AC INPUT OPERATING CONDITIONS
Recommended operating conditions(Voltage referenced to VSS=0V, VDD=3.3V+ 5%, VDDQ=2.5V+ 5%,TA=0 to 65C)
Parameter
Input High (Logic 1) Voltage; DQ Input Low (Logic 0) Voltage; DQ Clock Input Differential Voltage; CK and CK Clock Input Crossing Point Voltage; CK and CK
Symbol
VIH VIL VID VIX
Min
VREF+0.35 0.7 0.5*VDDQ-0.2
Typ
-
Max
VREF-0.35 VDDQ+0.6 0.5*VDDQ+0.2
Unit
V V V V
Note
1 2
Note : 1. VID is the magnitude of the difference between the input level on CK and the input level on CK 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same
- 11 -
Rev. 1.1(Aug. 2002)
K4D64163HF
AC OPERATING TEST CONDITIONS (VDD=3.3V5%, TA= 0 to 65C)
Parameter Input reference voltage for CK(for single ended) CK and CK signal maximum peak swing CK signal minimum slew rate Input Levels(VIH/VIL) Input timing measurement reference level Output timing measurement reference level Output load condition Value 0.50*VDDQ 1.5 1.0 VREF+0.35/VREF-0.35 VREF Vtt See Fig.1 Vtt=0.5*VDDQ
64M DDR SDRAM
Unit V V V/ns V V V
Note
RT=50 Output Z0=50
VREF =0.5*VDDQ
CLOAD=30pF
(Fig. 1) Output Load Circuit
CAPACITANCE (VDD=3.3V, TA= 25C, f=1MHz)
Parameter
Input capacitance( CK, CK ) Input capacitance(A0~A11, BA0~BA1) Input capacitance ( CKE, CS, RAS,CAS, WE ) Data & DQS input/output capacitance(DQ0~DQ31) Input capacitance(DM0 ~ DM3)
Symbol
CIN1 CIN2 CIN3 COUT CIN4
Min
1.0 1.0 1.0 1.0 1.0
Max
5.0 4.0 4.0 6.5 6.5
Unit
pF pF pF pF pF
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitance added to power line at board. Parameter Decoupling Capacitance between VDD and VSS Decoupling Capacitance between VDDQ and VSSQ Symbol CDC1 CDC2 Value 0.1 + 0.01 0.1 + 0.01 Unit uF uF
Note : 1. VDD and VDDQ pins are separated each other. All VDD pins are connected in chip. All VDDQ pins are connected in chip. 2. VSS and VSSQ pins are separated each other All VSS pins are connected in chip. All VSSQ pins are connected in chip.
- 12 -
Rev. 1.1(Aug. 2002)
K4D64163HF
C CHARACTERISTICS
Parameter
K cycle time K high level width K low level width QS out access time from CK utput access time from CK ata strobe edge to Dout edge ead preamble ead postamble K to valid DQS-in QS-In setup time QS-in hold time QS write postamble QS-In high level width QS-In low level width ddress and Control input setup ddress and Control input hold Q and DM setup time to DQS Q and DM hold time to DQS lock half period ata output hold time from DQS CL=3
64M DDR SDRAM
Symbol
-33 Min
3.3 0.45 0.45 -0.6 -0.6 0.9 0.4 0.8 0 0.45 0.4 0.4 0.4 0.9 0.9 0.4 0.4 tCLmin or tCHmin tHP-0.4
-36 Max
4.0 0.55 0.55 0.6 0.6 0.4 1.1 0.6 1.25 0.6 0.6 0.6 -
-40 Max
6 0.55 0.55 0.6 0.6 0.4 1.1 0.6 1.15 0.6 0.6 0.6 -
-50 Max
7 0.55 0.55 0.6 0.6 0.4 1.1 0.6 1.15 0.6 0.6 0.6 -
-60 Max
10 0.55 0.55 0.7 0.7 0.45 1.1 0.6 1.2 0.6 0.6 0.6 -
Min
3.6 0.45 0.45 -0.6 -0.6 0.9 0.4 0.85 0 0.35 0.4 0.4 0.4 0.9 0.9 0.4 0.4 tCLmin or tCHmin tHP-0.4
Min
4.0 0.45 0.45 -0.6 -0.6 0.9 0.4 0.85 0 0.35 0.4 0.4 0.4 0.9 0.9 0.4 0.4 tCLmin or tCHmin tHP-0.4
Min
5.0 0.45 0.45 -0.7 -0.7 0.9 0.4 0.8 0 0.3 0.4 0.4 0.4 1.0 1.0 0.45 0.45 tCLmin or tCHmin tHP0.45
Min
6.0 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.4 0.4 0.4 1.1 1.1 0.5 0.5 tCLmin or tCHmin tHP-0.5
Max
10 0.55 0.55 0.75 0.75 0.5 1.1 0.6 1.25 0.6 0.6 0.6 -
Unit Note
ns tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK ns ns ns ns ns ns 1 1 1
tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPREH tWPST tDQSH tDQSL tIS tIH tDS tDH tHP tQH
ote 1 : The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst ase output vaild window even then the clock duty cycle applied to the device is better than 45/55% A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle variation and replaces tDV tQHmin = tHP-X where . tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL) . X=A frequency dependent timing allowance account for tDQSQmax
- 13 -
Rev. 1.1(Aug. 2002)
K4D64163HF
AC CHARACTERISTICS (I)
Parameter
Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active Last data in to Row precharge @Normal Precharge Last data in to Row precharge @Auto Precharge Last data in to Read command Col. address to Col. address Mode register set cycle time Auto precharge write recovery + Precharge Exit self refresh to read comPower down exit time Refresh interval time
64M DDR SDRAM
-33 Min
17 20 11 6 6 2 3 3 2 1 3 9 200 2tCK +tIS 15.6
Symbol
-36 Max
100K -
-40 Max
100K -
-50 Max
100K -
-60 Max
100K -
Min
16 18 10 5 5 2 3 3 2 1 2 8 200 2tCK +tIS 15.6
Min
14 16 9 5 5 2 3 3 2 1 2 8 200 1tCK +tIS 15.6
Min
12 14 8 4 4 2 2 3 2 1 2 7 200 1tCK +tIS 15.6
Min
10 12 7 3 3 2 2 3 2 1 2 6 200 1tCK +tIS 15.6
Max
100K -
Unit
Note
tRC tRFC tRAS tRCD tRP tRRD tWR tWR_A tCDLR tCCD tMRD
tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK ns us 1 1 1
tDAL
tXSR tPDEX tREF
Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM
AC CHARACTERISTICS (II)
K4D64163HF-TC33 Frequency Cas Latency 300MHz (3.0ns ) 3 275MHz ( 3.6ns ) 3 250MHz ( 4.0ns ) 3 200MHz ( 5.0ns ) 3 166MHz ( 6.0ns ) 3 tRC 17 16 14 12 10 tRFC 20 18 16 14 12 tRAS 11 10 9 8 7 tRCD 6 5 5 4 3 tRP 6 5 5 4 3 tRRD 2 2 2 2 2 tDAL 9 8 8 7 6
(Unit : Number of Clock)
Unit
tCK tCK tCK tCK tCK
K4D64163HF-TC36 Frequency Cas Latency 275MHz (3.6ns ) 3 250MHz ( 4.0ns ) 3 200MHz ( 5.0ns ) 3 166MHz ( 6.0ns ) 3
tRC 16 14 12 10
tRFC 18 16 14 12
tRAS 10 9 8 7
tRCD 5 5 4 3
tRP 5 5 4 3
tRRD 2 2 2 2
tDAL 8 8 7 6
Unit
tCK tCK tCK tCK
K4D64163HF-TC40 Frequency Cas Latency 250MHz ( 4.0ns ) 3 200MHz ( 5.0ns ) 3 166MHz ( 6.0ns ) 3
tRC 14 12 10
tRFC 16 14 12
tRAS 9 8 7
tRCD 5 4 3
tRP 5 4 3
tRRD 2 2 2
tDAL 8 7 6
Unit
tCK tCK tCK
- 14 -
Rev. 1.1(Aug. 2002)
K4D64163HF
64M DDR SDRAM
K4D64163HF-TC50 Frequency Cas Latency 200MHz ( 5.0ns ) 3 166MHz ( 6.0ns ) 3
tRC 12 10
tRFC 14 12
tRAS 8 7
tRCD 4 3
tRP 4 3
tRRD 2 2
tDAL 7 6
Unit
tCK tCK
K4D64163HF-TC60 Frequency Cas Latency 166MHz ( 6.0ns ) 3
tRC 10
tRFC 12
tRAS 7
tRCD 3
tRP 3
tRRD 2
tDAL 6
Unit
tCK
Simplified Timing @ BL=4
0
CK, CK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
BA[1:0] BAa
BAa
BAa
BAa
BAb
BAa
BAb
A10/AP
Ra Ra
Ra
Rb
ADDR (A0~A11)
Ra
Ca
Ra
Rb
Ca
Cb
WE
DQS
DQ
Da0 Da1 Da2 Da3
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
DM
COMMAND
ACTIVEA
WRITEA
PRECH
ACTIVEA
ACTIVEB WRITEA
WRITEB
tRCD tRAS tRC tRP tRRD
Normal Write Burst (@ BL=4)
Multi Bank Interleaving Write Burst (@ BL=4)
- 15 -
Rev. 1.1(Aug. 2002)
K4D64163HF
PACKAGE DIMENSIONS (66pin TSOP-II)
64M DDR SDRAM
Units : Millimeters
(0.80) (0.50) (10x) (10x) 0.125 +0.075 -0.035 (0.50)
(R
.2 5 ) (R 0
#66
#34
10.160.10
(1.50)
#1 (1.50)
#33
0.6650.05
0.2100.05
(0.80)
5)
0. 15 )
0.05 MIN
(0.71)
0.65TYP 0.650.08
0.300.08 (10x)
0.10 MAX [ 0.075 MAX ]
( 4x )
NOTE 1. ( ) IS REFERENCE 2. [ ] IS ASS'Y OUT QUALITY
(R
0x~8x
- 16 -
Rev. 1.1(Aug. 2002)
0. 25 )
(R 0 .1
(10x)
1.20MAX
22.220.10
0.25TYP
0.45~0.75
1.000.10
11.760.20
(10.76)

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