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FUJITSU SEMICONDUCTOR DATA SHEET
DS05-30337-2E
FLASH MEMORY CARD
3V-ONLY FLASH MINIATURE CARD
MB98D81123(2MB)/81223(4MB)-15
2M/4M-BYTE 3 V-ONLY FLASH MINIATURE CARD
The Fujitsu Flash Miniature cards conform to "Miniature Card Specification" pubulished by MCIF; Miniature Card Implementers Forum. The Fujitsu Flash Miniature cards are small form factor Flash memory cards targeted various markets; digital photography, audio recording, hand held PCs and other small portable equipments. Miniature cards' high performance, small size (38 mm x 33 mm x 3.5 mm), low cost and simple interface are ideal for portable applications that require high speed flash disk drives or eXecute In Place (XIP). The Flash Miniature cards are 5 V-only operational and allow the users to use as x8 or x16 organization on low power at high speed. * * * * * * * * * * * * Small size: 33.0 mm (length) x 38.0 mm (width) x 3.5 mm (thickness) +3.3 V power supply program and erase Command control for Automated Program/Automated Erase operation Erase Suspend Read/Program Capability 128 KB Sector Erase (at x16 mode) Any Combination of Sectors Erase and Full Chip Erase Detection of completion of program/erase operation with Data# Polling or Toggle bit. Ready/Busy Output with BUSY# Reset Function with RESET# pin Write protect function with WP switch Low VCC Write Inhibit AIS (Attribute Information Structure) is available from the address "0000H" of Lower Byte.
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
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MB98D81123/81223-15
s PACKAGE
3 V - ONLY FLASH MINIATURE CARD
(CRD-60P-M02)
s DESCRIPTION
DIFFERENCES
MB98D81123 Density Memory Device Quantity Read Program Chip Erase Sector Erase Number of Sectors Erase Suspend Read Erase Suspend Program Address RESET# BUSY# 2 MB 8 M bit 2 1 B unit 1 B unit 1 MB unit 64 KB unit 32 Yes Yes A0 to A19 Yes Yes MB98D81223 4 MB 8 M bit 4 1 MB unit 64 Yes Yes A0 to A20 Yes Yes
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MB98D81123/81223-15
s PAD ASSIGNMENTS
Pad No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 EX 1 Symbol A18 A16 A14 N.C. CEH# A11 A9 A8 A6 A5 A3 A2 A0 N.C. N.C. VCC Pad No 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 EX 2 Symbol N.C. N.C. OE# D15 D13 D12 D10 D9 D0 D2 D4 N.C. D7 N.C. N.C. GND Pad No 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 EX 3 Symbol A19 A17 A15 A13 A12 RESET# A10 VS1# A7 N.C. A4 CEL# A1 N.C. N.C. CINS# Pad No 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Symbol CD# N.C. BUSY# WE# D14 RFU D11 VS2# D8 D1 D3 D5 D6 N.C. A20 *
* : A20 is "N.C." for MB98D81123.
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MB98D81123/81223-15
s PAD DESCRIPTIONS
Symbol A0 to A20 D0 to D15 CEL# CEH# OE# WE# RESET# I/O I I/O I I I I I Pad Name Address Input Data Input/Output Card Enable for Lower Byte Card Enable for Upper Byte Output Enable Write Enable Hardware Reset Symbol BUSY# CD# VS1#, VS2# N.C. VCC GND CINS# I/O O O O -- -- -- O Pad Name Ready/Busy Card Detect * Voltage Sense Non Connection Power Supply Ground Card Insertion
* : Take notice that those pads are connected internally.
s PAD LOCATIONS
Fig. 1 -- BOTTOM VIEW
60
31
30 EX 1 EX 3
1 EX 2
Voltage Key Voltage Key: See "UNIQUE FEATURES".
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MB98D81123/81223-15
s BLOCK DIAGRAM
MB98D81123
Fig. 2.1 -- BLOCK DIAGRAM
VCC GND Address
RESET WE OE Even Flash Memory CE 8M bit x 1 Address I/O R/B
Internal circuit Internal circuit
RESET#
VCC
VCC
100K 100K
CEL# CEH# OE#
D0 to D7
D8 to D15 VCC 100K WE#
RESET WE Address I/O Odd Flash Memory 8M bit x 1 R/B
Write Protect Switch N.C.
OE CE
VS1# VS2# N.C. VCC 10K BUSY# CINS# CD#
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MB98D81123/81223-15
MB98D81223
Fig. 2.2 -- BLOCK DIAGRAM
VCC GND Address A20
A 1Y /G1 Decoder /G2 2Y
Internal circuit Internal circuit
2
RESET Address I/O R/B Even Flash Memory CE
2
WE OE
RESET# VCC VCC 100K CEL# CEH# OE# 100K
8M bit x 2
D0 to D7
D8 to D15 VCC 100K
RESET WE Address I/O R/B Odd Flash Memory 8M bit x 2
WE#
Write Protect Switch N.C.
OE CE
VS1# VS2# N.C. VCC 10K BUSY# CINS# CD#
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MB98D81123/81223-15
s CHIP AND SECTOR DECODING
ERASE SECTOR DECODING TABLE
Sector Address (SA) A19 Sector 15 Sector 14 Sector 13 Total 16 sectors per 1 chip Sector 2 Sector 1 Sector 0 1 1 1
* * * *
A18 1 1 1
* * * *
A17 1 1 0
* * * *
A16 1 0 1
* * * *
0 0 0
0 0 0
1 0 0
0 1 0
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MB98D81123/81223-15
s CHIP CONFIGURATION
The miniature cards use 2 or 4 pcs of Flash Memory. * 2 pcs of Flash Memory are operated simultaneously at 16 bit mode and even number of chip is applied to lower byte and odd number of chip is applied to upper byte. At x8 bit mode, even address and odd address are selected with CEL# and CEH#.
1 x 16 bit mode CEL# = "L", CEH# = "L" : :
Odd Number of Chip + Even Number of Chip Odd Number of Chip + Even Number of Chip Odd Number of Chip + Even Number of Chip Odd Number of Chip + Even Number of Chip D15 * * * * * * * * * * * * * * D0
003h 002h 001h 000h
2 x 8 bit mode CEL# = "H", CEH# = "L" : :
CEL# = "L", CEH# = "H" : :
odd Number of Chip odd Number of Chip odd Number of Chip odd Number of Chip D15 * * * * D8
003h 002h 001h 000h
even Number of Chip even Number of Chip even Number of Chip even Number of Chip D7 * * * * * D0
003h 002h 001h 000h
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MB98D81123/81223-15
s FUNCTION DESCRIPTIONS
1. Read Mode
The data in the common can be read with "OE#=VIL" and "WE#=VIH". The address is selected with A0-A20. And CEL# and CEH# select output mode.
2. Standby Mode
- CEL# and CEH# at "VIH" place the card in Standby mode. D0-D15 are placed in a high-Z state independent of the status "OE#" and "WE#".
3. Output Disable Mode
- The outputs are disabled with OE# and WE# at "VIH". D0-D15 are placed in high-Z state.
4. Write Mode
1) Common Memory Write - The card is in Write mode with "OE#=VIH" and "WE# and CE#=VIL". - Commands can be written at the Write mode. - Two types of the Write mode, "WE# control" and "CE# control" are available.
5. Command Definitions
- User can select the card operation by writing the specific address and data sequences into the command register. If incollect address and data are written or improper sequence is done, the card is reseted to read mode. See "COMMAND DEFINISION TABLE".
6. Automated Program Capability
- Programming operation can switch the data from "1" to "0". - The data is programmed on a byte-by-byte or word-by-word basis. - The card will automatically provide adequate internally generated programming pulses and verify the programmed cell margin by writing four bus cycle operation. The card returns to Common Memory Read mode automatically after the programming is completed. - Addresses are latched at falling edge of WE# or CE# and data is latched at rising edge of WE# or CE#. The fourth rising edge of WE# or CE# on the command write cycle begins programming operation. - We can check whether a byte (word) programming operation is completed successfully by sequence flug with BUSY#, Data# Polling or Toggle Bit function. See "WRITE OPERATION STATUS". - Any commands written to the chip during programming operation will be ignored.
7. Automated Chip Erase Capability
- We can execute chip erase operation by 6 bus cycle operation. Chip erase does not require the user to program the chip prior to erase. Upon executing the Erase command sequence the chip automatically will program and verify the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timing during these operations. - The card returns to Common Memory Read mode automatically after the chip erasing is completed. - Whether or not chip erase operation is completed successfully can be checked by sequence flug with BUSY#, Data# Polling or Toggle Bit function. See "WRITE OPERATION STATUS". - Any commands written to the chip during programming operation will be ignored.
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MB98D81123/81223-15
8. Automated Sector Erase Capability
- We can execute the erase operation on any sectors by 6 bus cycle operation. - A time-out of 50 s (typ.) from the rising edge of the last Sector Erase command will initiate the Sector Erase command(s). - Multiple sectors in a chip can be erased concurrently. This sequence is followed with writes of 30H to addresses in other sectors desired to be concurrently erased. The time between writes 30H must be less than 50 s, otherwise that command will not be accepted. Any command other than Sector Erase or Erase Suspend during this time-out period will reset the chip to Read mode. The automated sector erase begins after the 50 s (typ.) time out from the rising edge of WE# pulse for the last Sector Erase command pulse. Whether the sector erase window is still open can be monitored with D3 and D11. - Sector Erase does not require the user to program the chip prior to erase. The chip automatically programs "0" to all memory locations in the sector(s) prior to electrical erase. The system is not required to provide any controls or timing during these operations. - The card returns to Common Memory Read mode automatically after the chip erasing is completed. - Whether or not sector erase operation is completed successfully can be checked by sequence flug with BUSY#, Data# Polling or Toggle Bit function. The sequence flug must be read from the address of the sector involved in erase operation. See "WRITE OPERATION STATUS".
9. Erase Suspend
- Erase Suspend command allows the user to interrupt the sector erase operation and then do data reads or program from or to a non-busy sector in the chip which has the sector(s) suspended erase. This command is applicable only during the sector erase operation (including the sector erase time-out period after the sector erase commands 30H) and will be ignored if written during the chip erase or programming operation. Writing this command during the time-out will result in immediate termination of the time-out period. The addresses are "don't cares" in wrinting the Erase Suspend or Resume commands in the chip. - When the Erase Suspend command is written during a Sector Erase operation, the chip will enter the Erase Suspend Read mode. User can read the data from other sectors than those in suspention. The read operation from sectors in suspention results D2/D10 toggling. User can program to non-busy sectors by writing program commands. - A read from a sector being erase suspended may result in invalid data.
10. Intelligent Identifier (ID) Read Mode
- Each common memory can execute an Intelligent Identifier operation, initiated by writing Intelligent ID command (90H). Following the command write, a read cycle from address 00H retrieves the manufacture code, and a read cycle from address 01H returns the device code as follows. To terminate the operation, it is necessary to write Read/Reset command.
11. Hardware Reset
- The Card may be reset by driving the RESET# pin to VIL. The RESET# pin must be kept High (VIL) for at least 500 ns. Any operation in progress will be terminated and the card will be reset to the read mode 20 s after the RESET# pin is driven Low. If a hardware reset occurs during a program operation, the data at that particular location will be indeterminate. - When the RESET# pin is Low and the internal reset is complete, the Card goes to standby mode and cannot be accessed. Also, note that all the data output pins are High-Z for the duration of the RESET# pulse. Once the RESET# pin is taken high, the Card requires 500 ns of wake up time until outputs are valid for read access. - If hardware reset occurs during a erase operation, there is a possibility that the erasing sector(s) cannot be used.
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MB98D81123/81223-15
12. Data Protection
- The card has WP (Write Protect) switch for write lockout. - To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than 3.2 V. If VCC < VLKO, the command register is disabled and all internal program/erase circuits are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when VCC is above 3.2 V. - If VCC would be less than VLKO during program/erase operation, the operation will stop. And after that, the operation will not resume even if VCC returns recommended voltage level. Therefore, program command must be written again because the data on the address interrupted program operation is invalid. And regarding interrupting erase operation, there is possibility that the erasing sector(s) cannot be used. - Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# will not initiate a write cycle.
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MB98D81123/81223-15
s FUNCTION TRUTH TABLE
Data Input/Output Mode Hardware Reset Standby Read (x8 bit) L Read (x16 bit) Write (x8 bit) Write (x16 bit) H L L H Output Disable L L H : "H" level, L : "L" level , X : "H" or "L" Note: *1. WPSW = Write Protect Switch, NP = NON-PROTECT, P = PROTECT H L H L H L P L High-Z High-Z High-Z High-Z High-Z High-Z NP DIN DIN High-Z DIN L H H L L L H P or NP DOUT DOUT High-Z High-Z DOUT DIN RESET# L CEH# X H H CEL# X H L OE# X X WE# X X WPSW *1 D8 to D15 P or NP P or NP High-Z High-Z High-Z D0 to D7 High-Z High-Z DOUT
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MB98D81123/81223-15
s COMMAND DEFINITION TABLE
Command Table for 8-bit Mode
Command 1st Bus Bus Cycle Write Cycle Write Read/Reset 1 2 CA Read/Reset 2 Read Intelligent ID Codes Byte Program 4 CA 4 CA 4 CA Sector Erase 6 CA Chip Erase Sector Erase Suspend Sector Erase Resume Note: CA: SA: PA: RA: IA: 6 CA 1 CA 1 CA 30H B0H Write AAH CA 55H CA 80H CA AAH CA 55H CA 10H Write AAH CA 55H CA 80H CA AAH CA 55H SA 30H Write Write Write Write Write Write AAH CA 55H CA A0H PA PD Write Write Write Write Write Write AAH CA 55H CA 90H IA ID Write Write Write Write AAH CA 55H CA F0H RA RD Write Write Write Read F0H RA RD Write Read Write Write 2nd Bus Write/Read Cycle Read 3rd Bus Write Cycle 4th Bus Write/Read Cycle 5th Bus Write Cycle 6th Bus Write Cycle
Chip Address. (address in chip selected by A20 for MB98D81223) Sector Address (address in 64 KB selected by A16, A17, A18, A19 and A20) Program Address (address to be programmed) Read Address (address to be read) Intelligent ID read address (Manufacture Code 0000H, Device Code 0001H)
PD: Programming data RD: Read data ID: Intelligent Identifier (ID) Code
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MB98D81123/81223-15
Command Table for 16-bit Mode
Command 1st Bus Bus Cycle Write Cycle Write Read/Reset 1 2 CA Read/Reset 2 Read Intelligent ID Codes Byte Program 4 CA 4 CA 4 CA Sector Erase 6 CA Chip Erase Sector Erase Suspend Sector Erase Resume Note: CA: SA: PA: RA: IA: 6 CA 1 CA 1 CA 3030H B0B0H Write AAAAH CA 5555H CA 8080H CA AAAAH CA 5555H CA 1010H Write AAAAH CA 5555H CA 8080H CA AAAAH CA 5555H SA 3030H Write Write Write Write Write Write AAAAH CA 5555H CA A0A0H PA PD Write Write Write Write Write Write AAAAH CA 5555H CA 9090H IA ID Write Write Write Write AAAAH CA 5555H CA F0F0H RA RD Write Write Write Read F0F0H RA RD Write Read Write Write 2nd Bus Write/Read Cycle Read 3rd Bus Write Cycle 4th Bus Write/Read Cycle 5th Bus Write Cycle 6th Bus Write Cycle
Chip Address. (address in chip selected by A20 for MB98D81223) Sector Address (address in 128 KB selected by A16, A17, A18, A19 and A20) Program Address (address to be programmed) Read Address (address to be read) Intelligent ID read address (Manufacture Code 0000H, Device Code 0001H)
PD: Programming data RD: Read data ID: Intelligent Identifier (ID) Code
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MB98D81123/81223-15
s WRITE OPERATION STATUS
Hardware Sequence Flag Table
Status Programming Erasing In Progress Erase Suspend Read Erase Suspend Program Programming Exceeded Time Limits Erasing Erase Suspend Program (1) (2) D7, D15 D7#, D15# 0 1 Data D7#, D15# D7#, D15# 0 D7#, D15# D6, D14 Toggle Toggle 1 Data Toggle *2 Toggle Toggle Toggle D5, D13 0 0 0 Data 0 1 1 1 D3, D11 0 1 0 Data 0 0 1 0 D2, D10 1 Toggle Toggle *1 Data *1, *3 1 N/A N/A BUSY# 0 0 1 1 0 0 0 0
(1): Erase Suspended Sector (2): Non-Erase Suspended Sector Notes: *1. Performing successive read operations from the erase-suspended sector will cause D2, D10 to toggle. *2. Performing successive read operations from any address will cause D6, D14 to toggle. *3. Reading the byte address being programmed while in the erase-suspend program mode will indicate logic `1' at the D2, D10 bit. However, successive reads from the erase-suspended sector will cause D2, D10 to toggle.
D7, D15 (Data# Polling)
The card features Data# Polling as a method to indicate to the host that the Program/Erase Operation are in progress or completed. During the program operation an attempt to read the program address will produce the compliment of the data last written to D7/D15. Upon completion of the program operation, an attempt to read the program address will produce the true data last written to D7/D15. During the erase operation, an attempt to read the program address will produce a "0" at the D7/D15 output. Upon completion of the erase operation an attempt to read the device will produce a "1" at the D7/D15 output. For Chip Erase, the Data# Polling is valid after the rising edge of the sixth WE# pulse in the six write pulse sequence. For sector erase, the Data# Polling is valid after the last rising edge of the sector erase WE# pulse. Even if the device has completed the operation and D7/D15 has a valid data, the data outputs on D0 to D6/D8 to D14 may be still invalid. The valid data on D0 to D7/D8 to D15 will be read on the successive read attempts. The Data# Polling feature is only active during the programming operation, erase operation, sector erase timeout, Erase Suspend Read mode and Erase Supend Program mode.
D6, D14 (Toggle Bit I)
The card also features the "Toggle Bit" as a method to indicate to the host system that the Program/Erase Operation are in progress or completed. During an Program or Erase cycle, successive attempts to read (OE# or CE# toggling) data from the card will result in D6/D14 toggling between one and zero. Once the Program or Erase cycle is completed, D6/D14 will stop toggling and valid data will be read on the next successive attempts. During programming, the Toggle Bit is valid after the rising edge of the fourth WE# pulse in the four write pulse sequence. For chip erase, the Toggle Bit is valid after the rising edge of the sixth WE# pulse in the six write pulse sequence. For sector erase, the Toggle Bit is valid after the last rising edge of the sector erase WE# pulse. The Toggle Bit is also active during the sector time out. Either CE# or OE# toggling will cause the D6/D14 to toggle.
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MB98D81123/81223-15
D5, D13 (Exceeded Timing Limits)
D5/D13 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions D5/D13 will produce a "1". This is a failure condition which indicates that the program or erase cycle was not successfully completed. Data# Polling is the only operating function of the card under this condition. If this failure condition occurs during sector erase operation, it specifies that a particular sector is bad and it may not be reused, however, other sectors are still functional and may be used for the program or erase operation. The chip must be reset to use other sectors. Write the Reset command sequence to the chip, and then execute Program or Erase command sequence. This allows the system to continue to use the other active sectors in the chip. If this failure condition occurs during the chip erase operation, it specifies that the entire chip is bad or combination of sectors are bad. If this failure condition occurs during the byte programming operation, it specifies that the entire sector containing that byte is bad and this sector may not be reused, (other sectors are still functional and can be reused). The D5/D13 failure condition may also appear if a user tries to program a non blank location without erasing. In this case the card locks out and never completes the card operation. Hence, the system never reads a valid data on D7/D15 bit and D6/D14 never stops toggling. Once the card has exceeded timing limits, the D5/D13 bit will indicate a "1". Please note that this is not a device failure condition since the device was incorrectly used.
D3, D11 (Sector Erase Timer)
After the completion of the initial sector erase command sequence the sector erase time-out will begin. D3/D11 will remain low until the time-out is complete. Data# Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data# Polling or the Toggle Bit indicates the card has been written with a valid erase command, D3/D11 may be used to determine if the sector erase timer window is still open. If D3/D11 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the card will be ignored until the erase operation is completed as indicated by Data# Polling or Toggle Bit. If D3/D11 is low ("0"), the card will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of D3/D11 prior to and following each subsequent sector erase command. If D3/D11 were high on the second status check, the command may not have been accepted. Refer to Table: Hardware Sequence Flags.
D2, D10
This Toggle bit, along with D6, can be used to determine whether the card is in the Erase operation or in Erase Suspend. Successive reads from the erasing sector will cause D2 to toggle during the Erase operation. If the card is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause D2 to toggle. When the card is in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic `1' at the D2 bit. D6 is different from D2 in that D6 toggles only when the standard Program or Erase, or Erase Suspend Program operation is in progress.
BUSY#
The card provides a BUSY# open-drain output pin as a way to indicate to the system that the program or erase operation are either in progress or has been completed. If the output is low, the card is busy with either a program or erase operation. If the card is placed in an Erase Suspend mode, the BUSY# output will be high. During programming, the BUSY# pin is driven low after the rising edge of the fourth WE# pulse. During an erase operation, the BUSY# pin is driven low after the rising edge of the sixth WE# pulse. The BUSY# pin will indicate a busy condition during the RESET# pulse.
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MB98D81123/81223-15
s PROGRAM/ERASE FLOWCHART
Fig. 3 -- PROGRAM FLOWCHART
START
SET PA PD : PROGRAM DATA PA : PROGRAM ADDRESS SET ADDRESS PCMA1, PCMA2 *1
WRITE COMMAND (PCMA1/AAH or AAAAH) *1
*1. See "COMMAND DEFINITION TABLE".
INCREMENT PA
WRITE COMMAND (PCMA2/55H or 5555H) *1 WRITE COMMAND (PCMA1/A0H/A0A0H) *1
WRITE DATA (PA/PD)
DATA# POLLING, TOGGLE BIT or BUSY# (See Fig. 7, 8, 9, 10)
NO
LAST ADDRESS ? YES COMPLETED
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MB98D81123/81223-15
Fig. 4 -- CHIP ERASE FLOWCHART
START SET CA
SET ADDRESS (CCMA1, CCMA2) *1 WRITE COMMAND (CCMA1/AAH or AAAAH) *1 WRITE COMMAND (CCMA2/55H or 5555H) *1 INCREMENT CA WRITE COMMAND (CCMA1/80H or 8080H) *1 WRITE COMMAND (CCMA1/AAH or AAAAH) *1 WRITE COMMAND (CCMA2/55H or 5555H) *1 WRITE COMMAND (CCMA1/10H or 1010H) *1
CA : CHIP ADDRESS
*1. See "COMMAND DEFINITION TABLE".
DATA# POLLING, TOGGLE BIT or BUSY# (See Fig. 7, 8, 9, 10)
YES
DESIRED OTHER CHIPS ERASE ? NO COMPLETED
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MB98D81123/81223-15
Fig. 5 -- SECTOR ERASE FLOWCHART
START SET SA
SET ADDRESS SCMA1, SCMA2 *2 WRITE COMMAND (SCMA1/AAH or AAAAH) *2 WRITE COMMAND (SCMA2/55H or 5555H) *2 WRITE COMMAND (SCMA1/80H or 8080H) *2 WRITE COMMAND (SCMA1/AAH or AAAAH) *2 WRITE COMMAND (SCMA2/55H or 5555H) *2 WRITE COMMAND (SA/30H or 3030H)
SA : SECTOR ADDRESS
*1. Possible for the sectors in a chip *2. See "COMMAND DEFINITION TABLE".
DESIRED OTHER SECTORS ERASE ? *1 NO DATA# POLLING, TOGGLE BIT or BUSY# (See Fig. 7, 8, 9, 10)
YES
WRITE COMMAND (SA/30H or 3030H)
COMPLETED
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MB98D81123/81223-15
Fig. 6 -- ERASE SUSPEND FLOWCHART
EXECUTING SECTOR ERASE WRITE COMMAND (CA/B0H or B0B0H) CA : CHIP ADDRESS SA : SECTOR ADDRESS RA : READ ADDRESS *1. Detection whether suspend mode is valid can be done by Data# Polling, Toggle Bit or BUSY# also.
READ DATA (SA) *1 Yes
Toggle bit = Toggle? *1 No Read or Program
No
STOP Erase Suspend mode? Yes WRITE COMMAND (CA/30H or 3030H)
FINISHED
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MB98D81123/81223-15
Fig. 7 -- DATA# POLLING FLOWCHART: x8 bit mode
*1. User sets the time period referring to "PROGRAM AND ERASE PERFORMANCES". START *2. Program VA = PA Chip Erase VA = CA Sector Erase VA = SA *3. D5/D7 are for even chip(s). In the case of odd chip(s), D5 D13 and D7 D15 are applied.
TIMER START *1
READ (VA) *2 Yes D7 = Data? *3 No No D5 = 1 or Time-up? *3 Yes READ (VA) *2 Yes D7 = Data? *3 No ERROR COMPLETED
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MB98D81123/81223-15
Fig. 8 -- TOGGLE BIT FLOWCHART: x8 bit mode
START
*1. User sets the time period referring to "PROGRAM AND ERASE PERFORMANCES". *2. Program VA = PA Chip Erase VA = CA Sector Erase VA = SA *3. D5/D6 are for even chip(s). In the case of odd chip(s), D5 D13 and D6 D14 are applied.
TIMER START *1
READ (VA) *2 No D6 = Toggle? *3 Yes No D5 = 1 or Time-up? *3 Yes READ (VA) *2 No D6 = Toggle? *3 Yes ERROR
COMPLETED
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MB98D81123/81223-15
Fig. 9 -- DATA# POLLING FLOWCHART: x16 bit mode
START
EF = 0 TIMER START *1
*1. User sets the time period referring to "PROGRAM AND ERASE PERFORMANCES". *2. Program VA = PA Chip Erase VA = CA Sector Erase VA = SA EF: EF = 0: EF = 1: EF = 2: EF = 3: Error Flag Operation Completed Lower Byte Error Upper Byte Error Lower/Upper Byte Error
READ (VA) *2 Yes
D7 = Data? No No D5 = 1 or Time-up? Yes READ (VA) *2
1
Yes D7 = Data? No EF = 1 No
READ (VA) *1 Yes D15 = Data? No D13 = 1 or Time-up? Yes READ (VA) *2 Yes D15 = Data? No EF = EF+2
1
EF = 0? Yes COMPLETED
No
ERROR
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MB98D81123/81223-15
Fig. 10 -- TOGGLE BIT FLOWCHART: x16 bit mode
START
EF = 0
*1. User sets the time period referring to "PROGRAM AND ERASE PERFORMANCES". *2. Program VA = PA Chip Erase VA = CA Sector Erase VA = SA EF: EF = 0: EF = 1: EF = 2: EF = 3: Error Flag Operation Completed Lower Byte Error Upper Byte Error Lower/Upper Byte Error
TIMER START *1
READ (VA) *2 No
D6 = Toggle? Yes No D5 = 1 or Time-up? Yes READ (VA) *
2
1
No D6 = Toggle? Yes EF = 1 No 1
READ (VA) *1 No D14 = Toggle? Yes D13 = 1 or Time-up? Yes READ (VA) *2 No D14 = Toggle? Yes EF = EF+2
EF = 0? Yes COMPLETED
No
ERROR
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s ABSOLUTE MAXIMUM RATINGS *1
Parameter Supply Voltage Input Voltage Output Voltage Temperature under Bias Storage Temperature Symbol VCC VIN VOUT TA TSTG Value -0.5 to +5.5 -0.5 to VCC +0.5 -0.5 to VCC +0.5 0 to +60 -30 to +70 Unit V V V C C
*1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
s RECOMMENDED OPERATING CONDITIONS
Parameter VCC Supply Voltage Ground Ambient Temperature Symbol VCC GND TA 0 Min 3.135 Typ 3.30 0 55 Max 3.465 Unit V V C
s DC CHARACTERISTICS
Parameter Input Leakage Current *1 Test Conditions VCC = VCC max., VIN = GND or VCC Symbol ILI ILO ISB1 ISB2 ICC1 ICC2 ICC3 VIL VIH VOL VOH VLKO 2.4 2.3 -- 2.5 -0.5 0.7 VCC 50 60 60 -- -- -- 10 Value Min Typ Max 10 10 70 5.0 80 100 100 0.6 VCC+0.5 0.45 Unit A A A mA mA mA mA V V V V V
Output Leakage Current *2 VCC = VCC max., VIN = GND or VCC Standby Current CEL#, CEH#, RESET# = VCC0.3 V CEL#, CEH#, RESET# = VIH Active Read Current Program Current Erase Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Low VCC Lock-out Voltage VCC = VCC max., CEL#, CEH# = VIL Cycle = 150 ns, IOUT = 0 mA Program in progress (x16 mode) Erase in progress (x16 mode) -- -- IOL = 4.0 mA, VCC = VCC min. IOH = -2.0 mA, VCC = VCC min. --
Notes: *1. This value does not apply to CEL#, CEH# and WE#. *2. This value does not apply to CD# and CINS#.
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s CAPACITANCE (TA = 25C, f = 1 MHz, VIN = VI/O = GND)
Parameter Input Capacitance *1 I/O Capacitance *2 Symbol CIN CI/O Min Max 40 40 Unit pF pF
Notes: *1. This value does not apply to CEL#, CEH# and WE#. *2. This value does not apply to VS1#, CD# and CINS#.
s AC TEST CONDITIONS
* Input Pulse Levels: VIH = 3.0 V, VIL = 0.0 V * Input Pulse Rise and Fall Times: 5 ns * Timing Reference Levels Input: VIL = 1.5 V, VIH = 1.5 V Output: VOL = 1.5 V, VOH = 1.5 V Output Load: 1TTL +100 pF
s PROGRAM AND ERASE PERFORMANCES
Parameter Byte Program Time *1 Chip Programming Time *1 Sector Erase Time *2 Program/Erase Cycles 100,000 Min Typ 8 8.4 1 Max 3600 T.B.D. 15 Unit s Sec. Sec. Cycles
Notes: *1. Excludes system-level overhead. *2. Excludes 00H programming prior to erasure.
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s AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
READ CYCLE *1
Parameter Read Cycle Time Card Enable Access Time Address Access Time Output Enable Access Time Card Enable to Output in Low-Z *2 Card Disable to Output in High-Z *2 Output Enable to Output in Low-Z *2 Output Disable to Output in High-Z *2 Output Hold from Address Change Ready Time from RESET# Symbol tRC tCE tACC tOE tCLZ tCHZ tOLZ tOHZ tOH tRDY 0 20 5 60 5 75 Min 150 150 150 75 Max Unit ns ns ns ns ns ns ns ns ns s
Notes: *1. Rise/Fall time < 5 ns. *2. Transition is measured at the point of 500 mV from steady state voltage.
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MB98D81123/81223-15
PROGRAM/ERASE CYCLE
Parameter Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recovery Time (WE# control) Read Recovery Time (CE# control) Output Enable Hold Time Card Enable Setup Time Card Enable Hold Time Write Enable Pulse Width Write Enable Setup Time Write Enable Hold Time Card Enable Pulse Width Duration of Byte Program Operation (/WE Control) Duration of Erase Operation *1 (/WE Control) Duration of Byte Program Operation (/CE Control) Duration of Erase Operation *1 (/CE Control) VCC Setup Time *2 Reset Pulse Width Busy Delay Time Symbol tWC tAS tAH tDS tDH tGHWL tGHEL tOEH tCS tCH tWP tWS tWH tCP tWHWH1 tWHWH2 tEHEH1 tEHEH2 tVCS tRP tBSY 50 500 90 Min 150 20 20 50 20 10 10 10 0 10 80 0 10 100 8 1 8 1 15 15 Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s s s s ns ns
Notes: *1. These do not include the preprogramming time. *2. Not 100% tested.
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MB98D81123/81223-15
s TIMING DIAGRAM
READ CYCLE TIMING DIAGRAM (WE# = VIH, RESET# = VIH)
READ CYCLE (x8 bit mode): "CEL# = OE# = VIL, CEH# = VIH" or "CEH# = OE# = VIL, CEL# = VIH"
tRC VIH Addresses VIL tACC tOH D0-D7 or D8-D15 VOH PREVIOUS DATA VALID VOL DATA VALID
READ CYCLE (x16 bit mode): CEL# = CEH# = OE# = VIL
tRC VIH Addresses VIL tACC tOH VOH D0-D15 VOL PREVIOUS DATA VALID DATA VALID
:Undefined
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READ CYCLE TIMING DIAGRAM (continued) (WE# = VIH, RESET# = VIH)
READ CYCLE 3: x8-bit Bus Organization
VIH Addresses VIL tACC CE1# or CE2# VIH VIL tCE tCLZ VIH OE# VIL tOE tOLZ D0-D7 or D8-D15 VOH VOL High-Z DATA VALID tOHZ tCHZ
:Undefined
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READ CYCLE TIMING DIAGRAM (continued) (WE# = VIH, RESET# = VIH)
READ CYCLE 4: CEL# = CEH# = VIL: x16-bit Bus Organization
Addresses
VIH VIL tACC tCHZ VIH VIL tCE tCLZ VIH VIL tOE VOH High-Z tOLZ DATA VALID tOHZ
CEL#=CEH#
OE#
D0-D15
VOL
:Undefined
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PROGRAM CYCLE TIMING DIAGRAM (WE# = CONTROLLED, RESET# = VIH)
1st Bus Cycle VIH Addresses *1 VIL PCMA1 *2 tWC tAS VIH CE# *
1
2nd Bus Cycle PCMA2 *2
3rd Bus Cycle PCMA1 *2
4th Bus Cycle PA *2
Data# Polling Cycle PA *2 tRC tRC
tAH
VIL tCS VIH OE# VIL tGHWL VIH WE# VIL tDH tWP VIH/OH VIL/OL AAH (AAAAH) VOH RESET# VOL tVCS 55H (5555H) tDS tBSY tWPH tWHWH1 tCH tOEH
Data *
1
A0H (A0A0H)
PD *2
D7#, D15#
PD *2
Data
VCC
:Undefined
Notes: *1. See "FUNCTION TRUTH TABLE". *2. PCMA1/PCMA2 = Command Address for Program, PA = Program Address, PD = Program Data. See "COMMAND DEFINITION TABLE".
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PROGRAM CYCLE TIMING DIAGRAM (CE# = CONTROLLED, RESET# = VIH)
1st Bus Cycle VIH Addresses *1 VIL PCMA1 *2 tWC tAS VIH WE# VIL tWS OE# VIH VIL tGHEL VIH CE# *1 VIL tCPH tWH
2nd Bus Cycle PCMA2 *2
3rd Bus Cycle PCMA1 *2
4th Bus Cycle PA *2
Data# Polling Cycle PA *2 tRC tRC
tAH
tOEH
tEHEH1
tDH tCP VIH/OH VIL/OL AAH (AAAAH) VOH BUSY# VOL tVCS 55H (5555H) tDS
tBSY
Data *1
A0H (A0A0H)
PD *2
D7#, D15#
PD *2
Data
VCC
:Undefined
Notes: *1. See "FUNCTION TRUTH TABLE". *2. PCMA1/PCMA2 = Command Address for Program, PA = Program Address, PD = Program Data. See "COMMAND DEFINITION TABLE".
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ERASE CYCLE TIMING DIAGRAM (WE# = CONTROLLED, RESET# = VIH)
1st Bus Cycle VIH Addresses *1 VIL CCMA1/ SCMA1 *2 tWC tAS VIH CE# *1 VIL tCS VIH OE# VIL tGHWL VIH WE# VIL tWPH tCH
2nd Bus Cycle CCMA2/ SCMA2 *2
3rd Bus Cycle CCMA1/ SCMA1 *2
4th Bus Cycle CCMA1/ SCMA1 *2
5th Bus Cycle CCMA2/ SCMA2 *2
6th Bus Cycle CCMA1/ SA *2
tAH
tDH tWP VIH/OH VIL/OL AAH (AAAAH) tVCS VCC 55H (5555H) tDS
Data *1
80H (8080H)
AAH (AAAAH)
55H (5555H)
10H/30H (1010H/3030H)
:Undefined
Notes: *1. See "FUNCTION TRUTH TABLE". *2. CCMA1/CCMA2 = Command Address for Chip Erase, SCMA1/SCMA2 = Command Address for Sector Erase, SA = Sector Address. See "COMMAND DEFINITION TABLE".
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MB98D81123/81223-15
ERASE CYCLE TIMING DIAGRAM (CE# = CONTROLLED, RESET# = VIH)
1st Bus Cycle VIH Addresses *1 VIL CCMA1/ SCMA1 *2 tWC tAS VIH WE# VIL tWS VIH OE# VIL tGHEL VIH CE# *1 VIL tCPH tWH
2nd Bus Cycle CCMA2/ SCMA2 *2
3rd Bus Cycle CCMA1/ SCMA1 *2
4th Bus Cycle CCMA1/ SCMA1 *2
5th Bus Cycle CCMA2/ SCMA2 *2
6th Bus Cycle CCMA1/ SA *2
tAH
tDH tCP VIH/OH VIL/OL AAH (AAAAH) tVCS VCC 55H (5555H) tDS
Data *1
80H (8080H)
AAH (AAAAH)
55H (5555H)
10H/30H (1010H/3030H)
:Undefined
Notes: *1. See "FUNCTION TRUTH TABLE". *2. CCMA1/CCMA2 = Command Address for Chip Erase, SCMA1/SCMA2 = Command Address for Sector Erase, SA = Sector Address. See "COMMAND DEFINITION TABLE".
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MB98D81123/81223-15
DATA# POLLING CYCLE TIMING DIAGRAM (RESET# = VIH)
Command Write Cycle VIH Addresses *2 VIL tWC tACC
Data# Polling Read Cycle VA *1
CE# *2
VIH VIL tCE tCHZ
OE#
VIH VIL tOE tOEH VIH VIL tWHWH1,2 (tEHEH1,2) *3 VIH/OH *4 tOHZ
WE#
D7, D15 *2
D7, D15
D7#, D15#
D7, D15 Valid Data
VIL/OL
D0-D6 *2 D8-D14
VIH/OH VIL/OL
D0-D6, D8-D14
D0-D6, D8-D14 Invalid Data
D0-D6, D8-D14 Valid Data
:Undefined
Notes: *1. *2. *3. *4.
VA = PA for Programming Cycle, VA = SA for Sector Erase, VA = CA for Chip Erase. See "FUNCTION TRUTH TABLE". tEHEH1,2 for CE# Control. Program/Erase operation is finished.
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TOGGLE BIT TIMING DIAGRAM (RESET# = VIH)
Command Write Cycle VIH Addresses *2 VIL
Toggle Bit Read Cycle VA *1 tRC VA *1 VA *1 VA *1
CE# *2
VIH VIL
OE#
VIH VIL tOEH
WE#
VIH VIL tOE
Data *
2
VIH/OH *4 VIL/OL D6, D14 Toggle D6, D14 Toggle
*3
D6, D14 Stop Toggling
Valid Data
:Undefined
Notes: *1. *2. *3. *4.
VA = PA for Programming Cycle, VA = SA for Sector Erase, VA = CA for Chip Erase. See "FUNCTION TRUTH TABLE". Program/Erase operation is finished. PD, 10H (1010H) or 30H (3030H)
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MB98D81123/81223-15
BUSY# Timing Diagram During Program/Erase Operations
CE#
WE#
BUSY# tRSY
Entire programming or erase operation
RESET# Timing Diagram
RESET#
Possible next operation tRP tRDY
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MB98D81123/81223-15
s UNIQUE FEATURES
Write Protect Switch
Write Protect Switch
"Protect"
"Non Protect"
Voltage Selection
The Miniature Card voltage is identified by both a mechanical key and voltage sense signals (VS1#, VS2#). The combination of the two allow the host to determine the proper voltage required to operate the Miniature Card, as well as a physical means to keep cards out of host systems that may damage the cards because of improper operational voltage. Six different voltage key combinations are defined in "Miniature Card Specification": 5 volt only, 3.3 volt only, x.x volt only, 3V/5V, x.xV/3V, and x.xV/3V/5V. These keys consist of notches in the Miniature Card and corresponding tabs in the socket. The socket tabs are located in the front of the Miniature Card socket and are used to keep out cards that do not contain the corresponding notch. See Voltage Keying Mechanism below. (Now only defined about 5.0V and 3.3V)
Miniature Card
Host
1 2 3 4
Miniature Card
1 2 3 4
MB98D81123/ 81223 is applied for this key 3.3V Only 3.3V Only Host Miniature Card
2 3 2 3
5V Only 5V Only Host Miniature Card
1 2 1 2
3.3V/5V 3.3V/5V Host Miniature Card
1 2 3
2
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s ATTRIBUTE INFORMATION STRUCTURE (AIS)
Address 0000 0001 0002 0003 0E 0004 05 - 0D 000E 000F 0010 0011 0012 FF 00 80 F1 99 10 B5 B3 0013 0014 0015 0016 0017 0018 0019 001A 001B 001C 001D 001E 001F 0020 0021 0022 0023 0024 0025 40 46 55 4A 49 54 53 55 00 4C 49 4D 49 54 45 44 00 00 00 00 (L) (I) (M) (I) (T) (E) (D) 4 MB device size for common memory [MB98D1223] End of list [Nulltuple-ignore] [Vendor unique tuple] Link to next tuple "Miniature Card Identifier" "Level of Compliance" "AIS Checksum" (B00-A4B=B5) [MB98D81123] "AIS Checksum" (B00-A4D=B3) [MB98D81223] "Manufacture Name" (F) (U) (J) (I) (T) (S) (U) Data 01 03 53 1D Attribute [Common Memory device information tuple] Link to next tuple Flash memory with 150 ns access time 2 MB device size for common memory [MB98D1123]
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s ATTRIBUTE INFORMATION STRUCTURE (AIS) (continued)
Address 0026 0027 0028 0029 002A 002B 002C 002D 002E 002F 0030 0031 0032 0033 0034 0035 0036 0037 0038 0039 003A 003B 003C 003D 003E 003F 0040 0041 0042 0043 Data 00 4D 42 39 38 44 38 30 30 32 33 00 73 65 72 69 65 73 00 00 00 01 00 00 00 00 00 04 38 01 03 0044 00 "Technology Count" (1) "Reserved" "Reserved" "Reserved" "Reserved" "Memory Type" (Flash) "JEDEC Manufacture ID" (FUJITSU) "JEDEC Component ID" (MBM29LV080) "Memory Size" (2MB) [MB98D81123] "Memory Size" (4MB) [MB98D81223] "x.x V Access time" (Not supported) 41 (s) (e) (r) (i) (e) (s) "Card Name" (M) (B) (9) (8) (D) (8) (0) (0) (2) (3) Attribute
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s ATTRIBUTE INFORMATION STRUCTURE (AIS) (continued)
Address 0045 0046 0047 0048 0049 004A 004B 004C 004D 004E 004F 00FF 0100 0101 0102 0103 0104 0105 0106 0107 0108 0109 010A 010B 010C 010D 010E 010F 0110 0111 0112 0113 42 Data 0F 00 00 56 00 01 00 00 00 00 00 00 FF 15 1C 05 PC Card Standard, February 1995 00 46 55 4A 49 54 53 55 00 4D 42 39 38 44 38 30 (M) (B) (9) (8) (D) (8) (0) (F) (U) (J) (I) (T) (S) (U) "3.3 V Access time" (150 ns) "5.0 V Access time" (Not supported) "x.x V Read/Write" (Not supported) "3.3 V Read/Write" (50 mA/60 mA) "5.0 V Read/Write" (Not supported) "Standby Current" (100 A) "Reserved" "Reserved" "Reserved" "Reserved" "Reserved" "Reserved" End of list [Level 1 version/product-information tuple] Link to next tuple Attribute
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s ATTRIBUTE INFORMATION STRUCTURE (AIS) (continued)
Address 0114 0115 0116 0117 0118 0119 011A 011B 011C 011D 011E 011F 0120 0121 0122 0123 0124 0125 0126 0127 0128 0129 012A 012B 012C 012D 012E 012F 0130 0131 0132 0133 Data 30 32 33 73 65 72 69 65 73 00 FF 18 03 04 38 FF 1E 07 02 11 01 01 01 01 FF 12 05 00 00 Target address; stored as an unsigned long, low-order byte first 02 00 FF End of list 43 End of list [JEDEC programming information for Common Memory tuple] Link to next tuple JEDEC Manufacture ID (FUJITSU) JEDEC Device ID (MB29LV080) End of list [Device geometry information for Common Memory device tuple] Link to next tuple System bus width is 2 Bytes Erase block size is 64 KBytes Read block size is 1 Bytes Write block size is 1 Bytes No special partitioning requirements Non interleaved End of list [Longlink to Common Memory] Link to next tuple (0) (2) (3) (s) (e) (r) (i) (e) (s) Attribute
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s ATTRIBUTE INFORMATION STRUCTURE (AIS) (continued)
Address 0134 0135 0136 0137 0138 Data 1C 04 02 53 1D 0E 0139 013A FF FF Attribute [Other operating conditions device information for Common Memory] Link to next tuple Other Conditions Information: 3.3 V Operation Flash Memory with 150 ns access time 2 MB device size for common memory [MB98D81123] 4 MB device size for common memory [MB98D81223] End of list [The end-of-chain tuple]
Notice:AIS is programed from the address "0000H" of Lower Byte. This AIS may be deleted on the driver software which does not consider AIS.
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s PACKAGE DIMENSIONS
60-PIN MINIATURE CARD (CASE No.: CRD-60P-M02)
2.50 (.098)
33.000.13(1.299.005) 2.50(.098)MIN
2-R0.50(.020) 18TYP 1 PIN
5.50(.217) 12.70(.500) 7.20(.283) 3.00 (.118) 8.00(.315) 38.000.13 (1.496.005) 8.00(.315) 5.50(.217)
18.00 (.709) "B"
4.1250.05 (.162.002) 4.810.08 (.189.003) 33.000.13 (1.299.005)
7.210.08 (.283.003)
0.77(.030) 3.500.13 (.138.005) 1.52(.060) 15.24(.600) Details of "A" part R1.00(.039) 0.50(.020)
1.68(.066)
3.400.05 (.134.002)
5.95(.234) Details of "B" part 1.00(.039)TYP 0.500.036 (.020.001) 1.60 (.063)
4.25(.167)TYP 3.25(.128)TYP R0.15 (.006)
2.50(.098)TYP
"A"
7.62(.300)
2.70 1.85(.073) (.106) TYP 0.85(.033)
4.58 (.180) 9.10 (.358)
2.48 (.098) 2.60 (.102)
1.25(.049) MIN
0.500.05 (.020.002)
C
1996 FUJITSU LIMITED K60002SC-1-1
Dimension in mm (inches)
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MB98D81123/81223-15
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F9703 (c) FUJITSU LIMITED Printed in Japan
46

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