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Advanced Information
Advanced Digital Video Encoder
Y/Cb/Cr R/G/B Output Support HCMOS Technology
The MC44724A and MC44725A are advanced Digital Video Encoders (DVE). They convert ITU-601/656 standard 4:2:2 BitParalellel data into analog composite video, S-Video or analog component signals Y/Cb/Cr or R/G/B in PAL and NTSC formats. They accept the multiplexed two 8-bit or 16-bit ((CB,Y,CR)Y) signals from digital sources such as MPEG decoders and can act as a sync generator master or as a sync slave. All video processing is done digitally and requires no external adjustment. Specifically designed for digital satellite, digital cable decoders, multimedia terminals and DVD players.
MC44724A MC44725A
VFU SUFFIX 64 VQFP (0.5mm Pitch)
* World Wide Operation (PAL-BDGHI, PAL-N,PAL-M, NTSC-M) * SMPTE 170M / ITU - R 624 composite video output * Programmable Color Sub-carrier Frequencies * Analog standard timing for Horizontal, Vertical, Frame and Composite Sync Outputs * Sync Extraction From Digital Input Data (SAV, EAV) * Sync Polarity and Horizontal / Vertical Phase Control * Master or Slave Sync (H/Vsync, H/Fsync, ITU-R656 Slave) Operation * Interlaced or Non-Interlaced Support * 625/50 or 525/60 ITU-601/656 two 8-bit or 16-bit ((CB,Y,CR)Y) Digital Input * Luma 2X / Chroma 4X Output interpolating Filter * Dual Digital A / B selectable inputs * External VBI Information Data Input (Teletext Information Data) * Selectable Two sets of Signals within (CVBS/Y/C) or (Y/Cb/Cr) or (R/G/B) * Selectable Analog Component Output ( Beta Cam or MII Component Interface Level ) * Six Analog Outputs Through 10-bit DACs * Easily programmed via Serial Bus ( I2C or 4-Wired SPI Bus) * 2 Hardware selectable I2C Chip Addresses * Closed-Caption, CGMS and WSS Information data Insertion * MACROVISION ver. 7.01 Anti-Copy Signal Insertion(MC44724A Only) * On Chip Color - bar Generator * 5V Tolerante Input * +3.3V Power Supply or +3.3V(Digital)/+5V(Analog) Power Supply * Pin Compatible with MC44724/5 The MC44724A device is protected by U.S. patent number 4,631,603,4,577,216 and 4,819,098 and other intellectual property rights. The use of Macrovision's copy protection technology in the device must be authorized by Macrovision and is intended for home and other limited payper-view uses only, unless otherwise authorized in writing by Macrovision. Reverse engineering or disassembly is prohibited.
No. 1
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
[Pin Assignment]
64
62
59
56
53
60
63
57
54
51
50 Hsync
58
61
55
52
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
F/Vsync
NC
NC
TP
DVIB0
DVIB2
DVIB3
A/B_sel
DVIB1
DVIB4
DVIB5
DVIB6
DVdd
DVss
DVIB7
49
CVBS / Cb / B 1 CVBS / Cb / B 1 CVBS / Cb / B 1 Vdd Y/G1 Y/G1 Y / G 1 Vdd C / Cr / R 1 C / Cr /R 1 C / Cr / R 1 Vdd DAVss Ibias 1 VReff 1 DAVdd CVBS / Cb / B 2Vdd VReff 2 CVBS / Cb / B 2 CVBS / Cb / B 2 Ibias 2 NC
C/Fsync/VBI Vmute DVIA0 DVIA1 DVIA2 DVIA3
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
MC44724A MC44725A
DVIA4 DVIA5 DVIA6 DVIA7 DVss DVdd SEL SCL/SCK
C / Cr / R 2 Vdd
SDA/SI PAL/NTSC SO
Y / G 2 Vdd
C / Cr / R 2
Y/G2
Y/G2
C / Cr / R 2
ChipA
DVdd 30
TEST
DVss
17
19
22
25
18
21
24
27
28
31
Reset
clock
23
20
No. 2
26
29
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
32
[Pin Descriptions]
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39~46 47 48 49 50 51 52~55 56 57 58~61 62 63~64 NAME I/O DESCRIPTIONS Analog composite video signal output or Cb or B signal output current drive(positive) Analog composite video signal output or Cb or B signal output current drive(negative) Power Supply for CVBS / Cb / B DAC1 circuit Analog luminance or G signal output current drive(positive) Analog luminance or G signal output current drive(negative) Power Supply for Y / G DAC1 circuit Analog chrominance signal output or Cr or R signal output current drive(positive) Analog chrominance signal output or Cr or R signal output current drive(negative) Power Supply for C / Cr /R DAC1 circuit Ground for DAC circuit Reference current for the 1st set of 3 DACs Reference full scale voltage for the 1st set of 3 DACs Power Supply for the DACs Reference full scale voltage for the 2nd set of 3 DACs Reference current for the 2nd set of 3 DACs No Connect to pin Analog composite video signal output or Cb or B signal output current drive(positive) Analog composite video signal output or Cb or B signal output current drive(negative) Power Supply for CVBS / Cb / B DAC2 circuit Analog luminance or G signal output current drive(positive) Analog luminance or G signal output current drive(negative) Power Supply for Y / G DAC2 circuit Analog chrominance signal output or Cr or R signal output current drive(positive) Analog chrominance signal output or Cr or R signal output current drive(negative) Power Supply for C / Cr /R DAC2 circuit I2C chip address select { 0 : 40(hex)/41(hex) 1 : 1D(hex )/1E(hex) } TEST pin(Grounded) Ground for Digital circuit 27MHz clock input Power Supply for Digital circuit Reset signal, active LOW NTSC/PAL select . This pin is sampled only at Reset. (NTSC : Low PAL : High ) In SPI mode, serial data output / In I2C mode, Grounded Serial data input, Open drain output / If SPI mode, serial data input Serial clock Connect to Ground / If SPI mode, this pin is chip select Power Supply for Digital circuit Ground for Digital circuit 8-bit Multiplexed 4:2:2 data(ITU Rec656/601) input (DVIA), or Multiplexed Y data (ITU Rec656/601) input in 16-bit input mode Video mute on Reset ( 0: nomal, 1: mute ) Csync/Frame sync output, or external VBI information input Frame sync or Vertical sync input/output Horizontal sync input/output Switch control for 8-bit X 2 Multiplexed 4:2:2 data(ITU Rec656/601) input (DVIA) or (DVIB) 8-bit Multiplexed 4:2:2 data(ITU Rec656/601) input (DVIB), or Multiplexed Cr/Cb data (ITU Rec656/601) input in 16-bit input mode Ground for Digital circuit Power Supply for Digital circuit Multiplexed 4:2:2 data(ITU Rec656/601) input (DVIB), or Multiplexed Cr/Cb data (ITU Rec656/601) input in 16-bit input mode Test data input/output (Grounded) No connect to pin (Grounded)
Digital ---> 30-pin, 37-pin, 57-pin Analog ---> 3-pin, 6-pin, 9-pin, 13-pin, 19-pin, 22-pin, 25-pin No. 3
CVBS/Cb/B 1 O CVBS/Cb/B 1 O CVBS/Cb/B1Vdd Y/G 1 O Y/G 1 O Y/G 1Vdd C/Cr/R 1 O C/Cr/R 1 O C/Cr/R 1Vdd DAVss Ibias 1 O Vref 1 DAVdd Vref 2 Ibias 2 O NC CVBS/Cb/B 2 O CVBS/Cb/B 2 O CVBS/Cb/B2Vdd Y/G 2 O Y/G 2 O Y/GVdd C/Cr/R 2 O C/Cr/R 2 O C/Cr/R 2Vdd ChipA TEST I DVss CLOCK I DVdd Reset I PAL/NTSC I SO z(O) SDA/SI I/O(I) SCL/SCK I SEL I/ (I) DVdd DVss DVIA7~0 I/O Vmute C/Fsync/VBI F/Vsync Hsync A/B_sel DVIB7~4 DVss DVdd DVIB3~0 TP NC I I/O I/O I/O I I/O
I/O I/O
Note : Power Supply Group
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
[Block Diagram]
CVBS/Cb/B 2Vdd
C/Fsync/VBI
F/Vsync
Hsync
C/Cr/R 2Vdd
Y/G 2Vdd
Y/G 1Vdd
Sync_generator
DVdd DVss
CGMS, WSS_gen CC_gen BG
copy protection
bus
CVBS/Cb/B 1Vdd C/Cr/R 1Vdd
0
DAC
Y/G 1 Y/G 1 CVBS/Cb/B 1 CVBS/Cb/B 1 C/Cr/R 1 C/Cr/R 1 Vref 1 Ibias 1 Y/G 2 Y/G 2 CVBS/Cb/B 2 CVBS/Cb/B 2 C/Cr/R 2 C/Cr/R 2 Vref 2 Ibias 2
H,V
Y
0
off_set 0
DVIA [7 : 0]
demux
DVIB [7 : 0]
Cb Cr
0 Modulator 0
0
Output Selector
A/B_sel
subcarrier gen
0
0
0
TP Clock
0
Reset PAL/NTSC I2C / SPI
TEST
bus
MC44724A/5A
SEL SO SDA/SI SCL/SCK TEST DAVdd DAVss
I2C/SPI chip-address
40/41(hex) 1D/1E(hex)
No. 4
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
BIAS
ChipA
DAC
DAC
RGB matrix
DAC
BIAS
DAC
DAC
[Function Descriptions]
Clock
27.0MHz. This signal on the clock pin needs to be active and stable for 5 cycles before the reset pin is de-asserted.
Reset Procedure
RESET is a level sensitive input pin. Driving the RESET pin low causes a DVE reset. The 27Mhz DVE clock signal must be active before RESET is released. De-asserting reset will latch the status of the PAL/ NTSC, Vmute and SEL pins. The PAL/NTSC pin determines the default values for the DVE control registers. The default register values have been chosen so that standard PAL or NTSC video will appear at the DAC outputs immediately when a valid input digital video data stream is present and Vmute is Low at reset. The Vmute pin controls the "out of reset" operation of the Analog output signals. When "1" at reset, the video output is muted - output signal is "black - sync". When "0" at reset, the video output is from the input video data. This control can be used to mute the disable noise signals from a MPEG decoder at reset until a clear and stable picture is available. The value on the SEL pins determine the default serial communication mode. If Low, the DVE use I2C bus operation. If High, the DVE use 4-wired SPI operation. After reset, the VBI signals (Closed-Caption, CGMS and WSS ) are disabled. (see page --- for sub-address register descriptions.)
Fig 1 : DVIA/DVIB Data Input Timing
Input Clock 27MHz
50% Tds
Input Data DVIA/DVIB Tdh
Fig 2 : Sync Data Output Timing
Clock 27MHz Output Data TP Output data H/VF sync Td Td
No. 5
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
Input Data Format
The input digital video is in accord with the ITU-R Rec.656 and SMPTE 125M standards. It is two 8-bit or 16-bit multiplexed 4:2:2 ((CB,Y,CR)Y) data stream. Samples are latched on the rising edge of the clock signal. Data is input on pins DVIA[ 7 : 0 ] and DVIB[ 7 : 0 ] (see figures 3 and 4 for sub-address register descriptions.)
Video Timing / Sync Generator
The DVE outputs PAL-B,D,G,H,I, PAL-N, PAL-M or NTSC-M standard video signals. The DVE sync generator can be operated in two sync modes, master or slave. In master mode, the DVE generates all the correct Horizontal and Vertical or Frame sync signals internally, and outputs the Csync signal through the C/Fsync/VBI pin(C/Fsync). In slave mode, the DVE derives the sync signals from the Bit-Parallel input data stream Start Active Video (SAV) and End Active Video (EAV) data packet information. Sync signals are output on the Hsync and F/Vsync or C/Fsync/VBI pins and can be programmed for positive or negative polarity. The phase of Hsync can also be controlled. Also, the DVE allows more two slave modes. One is H/Vsync slave, and the another is H/Fsync slave mode. Vertical Blanking corresponds to the following lines. 625/50 624-22 311-335 ITU-R line numbering 525/60 1-19 264-282 SMPTE line numbering (see figures 3,4,5,6,7,8,9,10, and 11 for sub-address register descriptions.)
Fig 3 : Digital Input Timing(525/60 system) in Master Mode
Hsync phase sub-address71[2:0] +4T delay
70(hex){[1:0]=01}
-3T delay Hsync
Hsync polarity sub-address71[5]
T clock
128T
244T
1440T
8-bit input mode
DVIA[7:0] INVALID
FF 00 00 XY Cb0 Y0 Cr0 Y1 Cb2 Y2 Cb718 Y718 Cr718 Y719 FF 00 00
16-bit input mode
DVIA[7:0] INVALID DVIB[7:0] INVALID
242T
Y0 Y1 Y2 Y718 Y719
Cb0 or Cr0
Cr0 Cb0
Cb2 Cr2
Cb718 Cr718
Cr718 Cb718
No. 6
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
Fig 4 : Digital Input Timing(625/50 system) in Master Mode
Hsync phase sub-address71[2:0] +4T delay
70(hex){[1:0]=01}
-3T delay Hsync
Hsync polarity sub-address71[5]
T clock
128T
264T
1440T
8-bit input mode
DVIA[7:0] INVALID
FF 00 00 XY Cb0 Y0 Cr0 Y1 Cb2 Y2 Cb718 Y718 Cr718 Y719 FF 00 00
16-bit input mode
DVIA[7:0] INVALID DVIB[7:0] INVALID
262T
Y0 Y1 Y2 Y718 Y719
Cb0 or Cr0
Cr0 Cb0
Cb2 Cr2
Cb718 Cr718
Cr718 Cb718
Fig 5 : Sync Timing::525/60 Interlaced System in Master Mode
Fsync polarity sub-address71[3]
sub-address71[7] =0
Fsync Vsync
Vsync polarity sub-address71[4]
Hsync CSYNC 524 525 1 2 3 4 5 6 7 8 9 10 11 21 22 23
Fsync Vsync Hsync CSYNC 261 262 263 264 265 266 267 268 269 270 271 272 273 283 284 285
No. 7
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
Fig 6 : Sync Timing::625/50 Interlaced System in Master Mode
Fsync polarity sub-address71[3] Vsync polarity sub-address71[4]
sub-address71[7] =0
Fsync Vsync Hsync CSYNC 621 622 623 624 625
1
2
3
4
5
6
7
8
9
21
22
23
Fsync Vsync Hsync CSYNC 309 310 311 312 313 314 315 316 317 318 319 320 321 334 335
Fig 7 : Sync Timing::525/60 Non-interlaced System in Master Mode
Fsync polarity sub-address71[3]
sub-address71[7] =1
Fsync Vsync
Vsync polarity sub-address71[4]
Hsync CSYNC 261 262 1 2 3 4 5 6 7 8 9 10 11 21 22 23
Fig 8 : Sync Timing::625/50 Non-interlaced System in Master Mode
Fsync polarity sub-address71[3] Fsync Vsync Hsync CSYNC 308 309 310 311 312 1 2 3 4 5 6 7 Vsync polarity sub-address71[4]
sub-address71[7] =1
8
9
21
22
23
No. 8
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
Fig 9 : Analog Sync Timing::Rise and fall
0.148uS 2.37uS 29.41uS 63.56uS 27.04uS
0.148uS 4.74uS
NTSC
0.222uS 2.37uS 29.63uS 64.00uS 27.26uS
0.222uS 4.74uS
PAL
Fig 10 : Sync Timing::525/60 Interlaced System in Slave Mode Odd field
Fsync Vsync Fsync polarity sub-address71[4]
sub-address71[1:0] =10, 11
Vsync polarity sub-address71[5]
Hsync
Internal Hsync reset counter
Hsync Delay sub-address 7A[7:0], 71[3:0]
CSYNC 3 4 5 6 7
Even field
Fsync Vsync Hsync CSYNC 266 267 268 269
No. 9
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
Fig 11 : Sync Timing::625/50 Interlaced System in Slave Mode
sub-address71[1:0] =10, 11
Odd field
Fsync Vsync
Fsync polarity sub-address71[4]
Vsync polarity sub-address71[5]
Hsync
Internal Hsync reset counter
Hsync Delay sub-address 7A[7:0], 71[3:0]
CSYNC 625 1 2 3 4
Even field
Fsync Vsync Hsync CSYNC 313 314 315 316
No. 10
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
Chroma / Luma Encoding
The DVE de-multiplexes the 4:2:2 digital video data stream. The de-multiplexed Y or Luma samples are interpolated at the clock rate. Offset compensation is then added, next any VBI signals consisting of Closed-Caption, CGMS and WSS are added to the appropriate lines, then finally composite sync pulses are added to the Luma signal.(see figure 14.) De-multiplexed component color CB and CR samples are interpolated at the clock rate. The Luma and Chroma Interpolation filter compensate for the sin(x)/x attenuation to on chip D/A converter and simplify the output filter and allows more accurate encoding. A set of 3 different filters are available for each Luma(only two) and Chroma filtering. And user can select within these filters to fit a wide variety of applications. (see figure 12 and 13, and sub-address resister 6F ) The DVE generates the necessary subcarrier color frequency for PAL or NTSC encoding from the 27Mhz system clock. This color subcarrier is then modulated by the base band component color CB and CR signals to create the video Chroma signal. (see figure 15.) A 7.5 IRE pedestal is added for the 60Hz field rate. This can be added for the 50Hz field rate through serial bus control. (see sub-address register descriptions)
Fig. 12 Luma Filtering Including DAC Attenuation
6 3 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 -48 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 f3 = 2.5MHz f1 = 6MHz 6 3 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 -33 -36 -39 -42 -45 -48
Fig. 13 Chroma Filtering
Amplitude [dB]
Amplitude [dB]
f2 = 2.5MHz
f1 = 3MHz
f3 = 1.5MHz
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Frequency [MHz]
Frequency [MHz]
"CVBS and S-VIDEO" or "YCbCr" or "RGB" Outputs
The internal digital video signals drive 10-bit D/A converters. Converter outputs are bidirectional current sources where the current is proportional to the digital data with reference to the IBIAS reference current. The pins CVBS/Cb/B, Y/G and C/Cr/R are the respective composite, Luma and Chroma or Y/Cb/Cr or R/G/B signal current source pins. Each of the DACs can drive 75ohm load resister. User can select 2 sets of signals from the above 3 signal sets. (see "Application Diagram" and "sub-address register descriptions".) In Y/Cr/Cb analog component output mode, user can select one of the component interface level , Beta Cam or M2 format ( see sub-address register 6E ). Bias Current Gain DACs can be switched off through serial bus control to reduce power consumption. Both outputs of unused DACs should be connected to ground through a resister to avoid charge buildup.
No. 11
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
Fig 14 : Luminance Output Range
235 210 170 145 106 81 41 16 16
Digital Y input code(16~235) 525/60 and 625/50 system 100%amplitude,100%saturation color bar
IRE 100 89 70 59 41 30 11 7.5 0 -40 670 620 540 490 412 362 282 232 232
code 1023
IRE 100 89 70 59 41 30 11 7.5 0 -40 232 200 670 620 540 490 412 362 282 232
code 1023
56 0
12 0
Analog Y output level(525/60 system) 100%amplitude,100%saturation color bar => 7.5IRE Setup Off
Analog Y output level(525/60 system) 100%amplitude,100%saturation color bar => 7.5IRE Setup On
IRE 100 89 70 59 41 30 11 0 232 200 670 620 540 490 412 362 282 232
code 1023
IRE 100 89 70 59 41 30 11 0 232 670 620 540 490 412 362 282 232
code 1023
-33
44 0
-43
44 0
Analog Y output level(625/50 system) 100%amplitude,100%saturation color bar => 7.5IRE Setup On
Analog Y output level(625/50 system) 100%amplitude,100%saturation color bar => 7.5IRE Setup Off
No. 12
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
Fig 15 : Chrominance Output Range
240 222 166 128 146 110 54 34 16 16 128 128 90 202
240
128
Digital Cr-input code(16~240) 525/60 and 625/50 system 100%amplitude,100%saturation color bar
Digital Cb-input code(16~240) 525/60 and 625/50 system 100%amplitude,100%saturation color bar
IRE 324 228 110 302 302 324
code 1023
63 59 45 20 0 -20 -45 -59 -63
228
512
0
Analog C output level(525/60 system) 100%amplitude,100%saturation color bar => 7.5IRE Setup Off/On
IRE 302 324 302 324 228 228 110
code
1023
67 63 48 21.5 0 -21.5 -48 -6 -67 3
512
0
Analog C output level(625/50 system) 100%amplitude,100%saturation color bar => 7.5IRE Setup On/Off
No. 13
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
Fig 16 : Y/Cb/Cr Output Range ( Beta Cam Component Interface Level )
IRE 100 89 70 59 41 30 11 7.5 0 -40 232 200 670 620 540 490 412 362 282 232
code 1023
IRE 100 89 70 59 41 30 11 0 -40 232 670 620 540 490 412 362 282 232
code 1023
12 0
56 0
Analog Y output level 100%amplitude,100%saturation color bar => 7.5IRE Setup On
Analog Y output level 100%amplitude,100%saturation color bar => 7.5IRE Setup Off
IRE 960 63 59 45 20 0 -20 -45 -59 -63 64 584 512 440 136 888
code
1023
512
512
0
Digital Cr-input code 100%amplitude,100%saturation color bar
=> 7.5IRE Setup On/Off
IRE 960 63 48 21.5 0 -21.5 -48 -63 64 216 512 360 808 664 512
code 1023
512
0
Digital Cb-input code 100%amplitude,100%saturation color bar
=> 7.5IRE Setup On/Off
No. 14
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
Fig 17 : Y/Cb/Cr Output Range ( M2 Component Interface Level )
IRE 100 89 70 59 41 30 11 0 232 670 620 540 490 412 362 282 232
code 1023
IRE 100 89 70 59 41 30 11 0 232 200 670 620 540 490 412 362 282 232
code 1023
-43
44 0
-33
44 0
Analog Y output level 100%amplitude,100%saturation color bar => 7.5IRE Setup Off
Analog Y output level 100%amplitude,100%saturation color bar => 7.5IRE Setup On
IRE 960 63 59 45 20 0 -20 -45 -59 -63 64 512 584 888
code 1023
512 440 136
512
0
Digital Cr-input code 100%amplitude,100%saturation color bar => 7.5IRE Setup On/Off
IRE 960 63 48 21.5 0 -21.5 -48 -63 64 216 512 360 664 512 808
code 1023
512
0
Digital Cb-input code 100%amplitude,100%saturation color bar => 7.5IRE Setup On/Off
No. 15
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
Fig 18 : RGB Output Range for 525/60 system ( Sync On )
IRE 100 670
code 1023
IRE 100 670
code 1023
7.5 0 -40
232 200
7.5 0
232
12 0 Analog R output level(525/60 system) 100%amplitude,100%saturation color bar => 7.5IRE Set up On
-40
56 0 Analog R output level(525/60 system) 100%amplitude,100%saturation color bar => 7.5IRE Set up Off
IRE 100 670
code 1023
IRE 100 670
code 1023
7.5 0
232 200
7.5 0
232
-40
12 0 Analog G output level(525/60 system) 100%amplitude,100%saturation color bar => 7.5IRE Set up On
-40
56 0 Analog G output level(525/60 system) 100%amplitude,100%saturation color bar => 7.5IRE Set up Off
IRE 100 670
code 1023
IRE 100 670
code 1023
7.5 0
232 200
7.5 0
232
-40
12 0 Analog B output level(525/60 system) 100%amplitude,100%saturation color bar => 7.5IRE Set up On
-40
56 0 Analog B output level(525/60 system) 100%amplitude,100%saturation color bar => 7.5IRE Set up Off
Transformation a) R = Y + 1.371 (Cr-128) b) G = Y - 0.698 (Cr - 128) - 0.336 (Cb - 128) c) B = Y +1.732 (Cb - 128)
No. 16
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
Fig 19 : RGB Output Range for 625/50 system ( Sync On )
IRE 100 670
code 1023
IRE 100 670
code 1023
0
232
7.5 0
232 200
-43
44 0 Analog R output level(625/50 system) 100%amplitude,100%saturation color bar => 7.5IRE Set up Off
-33
44 0 Analog R output level(625/50 system) 100%amplitude,100%saturation color bar => 7.5IRE Set up On
IRE 100 670
code 1023
IRE 100 670
code 1023
232 0
7.5 0
232 200
-43
44 0 Analog G output level(625/50 system) 100%amplitude,100%saturation color bar => 7.5IRE Set up Off
-33
44 0 Analog G output level(625/50 system) 100%amplitude,100%saturation color bar => 7.5IRE Set up On
IRE 100 670
code 1023
IRE 100 670
code 1023
0
232
7.5 0
232 200
-43
44 0 Analog B output level(625/50 system) 100%amplitude,100%saturation color bar => 7.5IRE Set up Off
-33
44 0 Analog B output level(625/50 system) 100%amplitude,100%saturation color bar => 7.5IRE Set up On
Transformation a) R = Y + 1.371 (Cr-128) b) G = Y - 0.698 (Cr - 128) - 0.336 (Cb - 128) c) B = Y +1.732 (Cb - 128)
No. 17
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
Fig 20 : RGB Output Range for 525/60 system ( Sync Off )
code 1023 940 code 1023 940
IRE 100
IRE 100
0
64 0
0
64 0
Analog R output level (525/60 system) 100%amplitude,100%saturation color bar => 7.5IRE Set up On
IRE 100 940 code 1023 IRE 100
Analog R output level (525/60 system) 100%amplitude,100%saturation color bar => 7.5IRE Set up Off
code 1023 940
0
64 0
0
64 0
Analog G output level (525/60 system) 100%amplitude,100%saturation color bar => 7.5IRE Set up On
code IRE 100 940 1023 IRE 100
Analog G output level (525/60 system) 100%amplitude,100%saturation color bar => 7.5IRE Set up Off
code 1023 940
0
64 0
0
64 0
Analog B output level (525/60 system) 100%amplitude,100%saturation color bar => 7.5IRE Set up On Transformation
Analog B output level (525/60 system) 100%amplitude,100%saturation color bar => 7.5IRE Set up Off
a) R = Y + 1.371 (Cr-128) b) G = Y - 0.698 (Cr - 128) - 0.336 (Cb - 128) c) B = Y +1.732 (Cb - 128)
No. 18
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
Fig 21 : RGB Output Range for 625/50 system ( Sync Off )
IRE 100 940 code 1023 IRE 100 940 code 1023
64 0 0 0
64
Analog R output level (625/60 system) 100%amplitude,100%saturation color bar => 7.5IRE Set up On
IRE 100 940
Analog R output level (625/60 system) 100%amplitude,100%saturation color bar => 7.5IRE Set up Off
IRE 100 940
0
code 1023
code 1023
64 0 0 0
64 0
Analog G output level (625/60 system) 100%amplitude,100%saturation color bar => 7.5IRE Set up On
code IRE 100 940 1023 IRE 100
Analog G output level (625/60 system) 100%amplitude,100%saturation color bar => 7.5IRE Set up Off
code 1023 940
64 0 0 0
64 0
Analog B output level (625/60 system) 100%amplitude,100%saturation color bar => 7.5IRE Set up On Transformation
Analog B output level (625/60 system) 100%amplitude,100%saturation color bar => 7.5IRE Set up Off
a) R = Y + 1.371 (Cr-128) b) G = Y - 0.698 (Cr - 128) - 0.336 (Cb - 128) c) B = Y +1.732 (Cb - 128)
No. 19
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
Copy Generation Management System (CGMS) Encoding
CGMS signals can be encoded by the DVE onto output video line 20 (525 / 60 for Japan). CGMS identification signals also identify and control the TV screen presentation mode - wide screen, letter box and or normal -16:9 or 4:3. Data is Double-Buffered and is latched at the start of Field 1. (see figures 24 for sub-address register descriptions.)
Wide Screen Signaling (WSS) Encoding
WSS signals can be encoded by the DVE onto output video line 23 (625 / 50 for Europe). WSS identification signals also identify and control the TV screen presentation mode - wide screen, letter box and or normal -16:9 or 4:3. Data is Double-Buffered and is latched at the start of Field 1. (see figures 25 for sub-address register descriptions.)
Closed-Caption Encoding
Closed-Captioned or Extended Data Service signals can be encoded by the DVE onto output video line 21/284 (NTSC) and line 22/335 (PAL). The CC data is input through the serial bus interface. Two 8-bit byte data pairs are encoded for each field. There are four registers for holding the data - two bytes per field. The serial data is 7bit US-ASCII MSB first, proceeded by an odd parity bit. Total 8-bits. (P-7-6-5-4-3-2-1-0) The DVE automatically generates the required clock run in and start bit for CC encoding. (see figure 16.) When Closed-Captioning is enabled, the system micro processor (uP) should update the CC data once each frame. This DVE will automatically NULL characters when there is no CC data to encoder after the CC data has been processed by setting the $87[5] register. It is recommended to write CC data only to the inactive frame. Field1 and Field2 data are double-buffered by the Frame sync falling edge of previous Frame, updating Frame 2 data during Frame1 display and Frame1 data during Frame2 display. When the $87[4] register is set, the DVE will generate the parity bit automatically. (see figures 26 and 27 for sub-address register descriptions.)
No. 20
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
Serial Control Bus
Control of the DVE device is accomplished through the I2C-Bus or 4-wired SPI serial bus. In I2C mode, pins SDA and SCL are the respective data and clock signals. Device address can be 40(hex)/41(hex) or 1E(hex)/1F(hex) . Slave address is chosen at reset by the state of the ChipA pin signal { 0 : 40(hex)/41(hex), 1 : 1E(hex)/1F(hex) } Sub-address register read and write operations are documented in the following figures 22a - 22b. In SPI mode, pins SO, SI, SCK and SEL are the respective data input, output, serial clock and chip select signals. Register read and write operations are documented in the following figures 23a - 23b
MACROVISIONTM Copy Protection
When enabled, the Luma and Chroma signals are modified according to the MACROVISION TM copy protection process for Pay Per View (PPV) and DVD applications revision 7.01 dated Sep 6th , 1996. Enabling and control is through the serial control bus. No MC44724A parts will be sent to the customer until the customer provides MOTOROLA with written confirmation of a license, non-disclosure or a waiver from MACROVISION TM. The MC44725A device is available without MACROVISION
TM
encoding.
No. 21
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
Fig 22-a : I2C-BUS Interface Write operation Timing
SCL
SDA
D7 D6 MSB
D5
D4
D3
D2
D1
D0 LSB
D7 D6 MSB
D5
D4
D3
D2
D1
D0 LSB
Start
chip address(write)
ACK
Sub-address
ACK
SCL
SDA
D7 D6 MSB
D5
D4
D3
D2
D1
D0 LSB
D7 D6 MSB
D5
D4
D3
D2
D1
D0 LSB
Data 1
ACK
Data N
ACK
Stop
Fig 22-b : I2C-BUS Interface Read operation Timing
SCL
SDA
D7 D6 MSB
D5
D4
D3
D2
D1
D0 LSB
D7 D6 MSB
D5
D4
D3
D2
D1
D0 LSB
Start
chip address(write)
ACK
Sub-address
ACK
Stop
SCL
SDA
D7 D6 MSB
D5
D4
D3
D2
D1
D0 LSB
D7 D6 MSB
D5
D4
D3
D2
D1
D0 LSB
Start
chip address(Read)
ACK
Data 1
ACK by MCU
SCL
SDA
D7 D6 MSB
D5
D4
D3
D2
D1
D0 LSB
D7 D6 MSB
D5
D4
D3
D2
D1
D0 LSB
Data 2
ACK by MCU
Data N
Stop ACK by MCU
No. 22
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
Fig 23-a : SPI-BUS Interface Write operation Timing
SEL
SCK
SI
x
D7 D6 MSB
D5
D4
D3
D2
D1
D0 LSB
D7 D6 MSB
D5
D4
D3
D2
D1
D0 LSB
SO (Don't care)
x
x MSB
x
x
x
x
x
x
x LSB
x MSB
x
x
x
x
x
x
x LSB
Start
Write Command
Sub-address
SEL SCK
SI
D7 D6 MSB
D5
D4
D3
D2
D1
D0 LSB
D7 D6 MSB
D5
D4
D3
D2
D1
D0 LSB
SO (Don't care)
D7 x MSB
x
x
x
x
x
x LSB
x MSB
x
x
x
x
x
x
x LSB
Data 1
Data N
No. 23
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
Fig 23-b : SPI-BUS Interface Read operation Timing
SEL
SCK
SI SO (Don't care)
x
D7 D6 MSB x MSB x
D5
D4
D3
D2
D1
D0 LSB x LSB
D7 D6 MSB x MSB x
D5
D4
D3
D2
D1
D0 LSB x LSB
x
x
x
x
x
x
x
x
x
x
x
Start
Write Command
Sub-address
Stop
SEL
SCK
SI
x
D7 D6 MSB x MSB x
D5
D4
D3
D2
D1
D0 LSB x LSB
x MSB
x
x
x
x
x
x
x LSB D0 LSB
SO
x
x
x
x
x
x
D7 D6 MSB
D5
D4
D3
D2
D1
Start
Read Command
Data 1
SEL
SCK
SI
x MSB
x
x
x
x
x
x
x LSB D0 LSB
x MSB
x
x
x
x
x
x
x LSB D0 LSB
SO
D7 D6 MSB
D5
D4
D3
D2
D1
D7 D6 MSB
D5
D4
D3
D2
D1
Data 2
Data N
Stop
No. 24
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
[Specifications]
Maximum Ratings DC Supply Voltage Input Voltage, All Inputs Output Voltage, All Outputs DC Output Current, per Pin Power Dissipation Storage Temperature Vdd Vin Vout Iout Pd Tstg -0.5 ~ +7.0 -1.5 ~ Vdd+1.5 -0.5 ~ Vdd+1.5 25 750 -65 ~ +150 V V V mA mW C
Other -1.5 ~ Vdd+1.95V at Vdd=3.3V
Electrical Characteristics Characteristic Power Supply Voltage(Analog Blocks) DAVDD Power Supply Voltage(Digital Blocks) DVDD Supply Current(Analog Blocks) Supply Current(Digital Blocks) Operating Temperature
Symbol Min AVDD 3.1 4.75 DVDD 3.1 AIcc DIcc Ta 0
Typ 3.3 5.0 3.3 70 50 -
Max 3.5 5.25 3.5 70
Unit V V mA mA C
Other
Vref = 1V, Iref = 1.8K, Rl = 180
DAC Blocks Characteristics(Power Supply 3.3V,Ta=25C) Characteristics Sym. Min Typ Max Resolution 10 Integral Non-Linearity INL 2.0 Differential Non-Linearity DNL 1.0 Analog Output Voltage Vyo 0.85 1.00* 1.15 Full Scale Output Voltage Vyfs 0.85 1.00** 1.15 Zero Scale Output Voltage Vyzs 0.0*** 0.1 75 External Load Resistance RL
Note :
Unit Bit LSB LSB Vp-p V V
Other Vref = 1.0V, Ibias = 1.8k, Rl = 180 Vref = 1.0V, Ibias = 1.8k, Rl = 180 Vref = 1.0V, Ibias = 1.8k, Rl = 180 Vref = 1.0V, Ibias = 1.8k, Rl = 180 Vref = 1.0V, Ibias = 1.8k, Rl = 180
* : code 000(hex) ~code max. ** : code max. *** : code 000(hex) : Negative Outputs are not tested.
DAC Blocks Characteristics(Power Supply 5.0V,Ta=25C) Characteristics Sym. Min Typ Max Resolution 10 Integral Non-Linearity INL 2.0 Differential Non-Linearity DNL 1.0 Analog Output Voltage Vyo 1.35 1.5* 1.65 Full Scale Output Voltage Vyfs 1.35 1.5** 1.65 Zero Scale Output Voltage Vyzs 0.0*** 0.1 75 External Load Resistance RL
Note :
Unit Bit LSB LSB Vp-p V V
Other Vref = 1.5V, Ibias = 1.8k, Rl = 180 Vref = 1.5V, Ibias = 1.8k, Rl = 180 Vref = 1.5V, Ibias = 1.8k, Rl = 180 Vref = 1.5V, Ibias = 1.8k, Rl = 180 Vref = 1.5V, Ibias = 1.8k, Rl = 180
* : code 000(hex) ~code max. ** : code max. *** : code 000(hex) : Negative Outputs are not tested.
Note : D/A Converter Output Full Scale Voltage Vyts (V) = (Vref / Iref ) * K * R load (K = 10 : DAC Current Gain) ( code 3ff(fex)) Power Dissipation Pd = [ (Vref1/Iref1 * 10 * 3ch) + (Vref2 / Iref2 * 10 * 3ch) + 10mA (Bais Current)] * 3.3V (or 5V)
No. 25
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
[Specifications]
Clock Blocks Characteristics Characteristic Clock Rate Clock Duty Cycle
Symbol fc Dty
Min 45
Typ 27.0 50
Max 55
Unit MHz %
Digital Blocks Electrical Characteristics(Power Supply 3.3V,Ta=25C 3C) Characteristics Symbol Min Typ Max Input Voltage HIGH ViH 2.0 5.25 LOW ViL 0.8 Output Voltage HIGH VoH 2.4 (2.0mA) LOW VoL 0.4 Input Leakage Current Iin 2.5 Hi-Z Leakage Current Ioz 20 Input Capacitance Cin 20 Load Capacitance CL 20 Data Setup Time Tds 4 Data Hold Time Tdh 5 Input Rise Time Tr 5 Input Fall Time Tf 5 Data delay Td 27
Unit V V V V A A pF pF nS nS nS nS nS
I2C/SPI-BUS Blocks Characteristics(Power Supply 3.3V,Ta=25C 3 C) Characteristics Symbol Min Typ Max 0.8 Input Voltage LOW VILM 2.3 5.25 Input Voltage High VIHM Input Current VIM 10 VOM 0.4 SDA Output Voltage (I OM=3mA) 3 Output Current (during acknowledge) IOM SPI Maxmum Clock Rate fspi 3
Unit V V A V mA MHz
Clock
50%
50%
Tds Input Data not valid
Tdh not valid
Tr
Tf
valid
No. 26
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
[I2C-BUS Slave Address 40(hex)/41(hex) or 1E(hex)/1F(hex)]

WRITE MODE
S
Slave Address
A
Sub Address
A
DATA 0
A
--------
DATA N
AP
40(hex) or 1E(hex) if more than 1byte DATA is transmitted, then auto-increment of the Sub Address is performed
S Slave Address A Sub Address DATA 0 DATA N P
Start condition 40(hex) or 1E(hex) Acknowledge, generated by the slave Sub address byte First data byte continued data byte(Sub Address is auto increment) Stop condition
READ MODE
S
Slave Address
A
Sub Address N
AP
Slave receiver
40(hex) or 1E(hex) then S Slave Address A DATA N AM DATA N + 1 AM ------ AM P Slave transmitter
41(hex) or 1F(hex)
S Slave Address A Sub Address N DATA N DATA N + 1 AM P
Start condition Slave receiver is act transmitter is ad Acknowledge, generated by the slave Sub Address byte DATA byte of Register N DATA byte of Register N + 1 (address auto-increment) Acknowledge, generated by the micro controller Stop condition (When Last AM must be '1' )
No. 27
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
[SPI-BUS]

WRITE MODE
S
Write Command 40(hex) or 1E(hex)
Sub Address
DATA 0
--------
DATA N
P
if more than 1byte DATA is transmitted, then auto-increment of the Sub Address is performed
S Write Command Sub Address DATA 0 DATA N P
Chip select on ( Hi to Lo) 40(hex) or 1E(hex) Sub address byte First data byte continued data byte(Sub Address is auto increment) Chip select off (Lo to Hi)
READ MODE
S
Write Command 40(hex) or 1E(hex)
Sub Address N
P
Slave receiver
then S Read Command 41(hex) or 1F(hex) DATA N DATA N + 1 --------P Slave transmitter
S Sub Address N Read Command DATA N DATA N + 1 P
Chip select on (Hi to Lo) Sub Address byte set 41(hex) or 1F(hex) DATA byte of Register N DATA byte of Register N + 1 (address auto-increment) Chip select off (Lo to Hi)
No. 28
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
[Register Mapping and Description]
Sub-address 6E : Y/CbCr mode setup (write)
MSB Register 6E
CbCr mode
LSB Y mode M2/Beta[1] M2/Beta[0]
default : 0000_0000(bin)
M2/Beta
: Y select M2 type, BetaCam type 00 : BetaCam (default)* 01 : M2 ( 7.5IRE setup )* 10 : BetaCam ( 7.5IRE setup )* 11 : M2* * : Register $72 [ 4 ] = " 0 " ----> BetaCam/MII (setup level : 0 IRE ) : Register $72 [ 4 ] = " 1 " ----> BetaCam/MII (setup level : 7.5 IRE )
Y mode
: Separate switch 0 : Y/CbCr's Y is same as Y/C/CVBS's Y (default) 1 : Y/CbCr's Y is the BetaCam or M2 Y signal : Cb/Cr gain 0 : normal operation (default) 1 : 1/2 gain (disable code divided by 2)
CbCr gain
Sub-address 6F : Interpolation Filter Switch (write)
MSB Register 6F
Cb/Cr/U/V Fil mode1 Cb Fil mode0 Cr Fil mode0 U Fil mode0 V Fil mode0
LSB
Y Fil mode0
default : 0000_0000(bin)
Y Fil mode 0
: Luma Filter switch 0 : wide 6MHz (default) 1 : narrow 2.5Mhz : Chroma Filter switch 0 : wide 3.0MHz(default) 1 : narrow 1.5MHz : Cr/Cb, RGB Filter switch 0 : wide 3.0MHz(default) 1 : narrow 1.5MHz : wide Filter switch 0 : wide0 3.0MHz(default) 1 : wide1 2.5MHz
V Fil, U Fil mode0
Cr Fil, Cb Fil mode 0
Cr /Cb Fil mode 1
No. 29
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
Sub-address 70 : Variable I/O Switch (write/read) MSB Register 70 bs-off self-SW
color bar select VBLK SW
C/Fsync SW F/Vsync SW M/S mode1 M/S mode0
LSB
default : 0000_0001(bin)
bs - off
: color burst control switch On/Off 0 : color burst ON (default) 1 : color burst OFF : internal self H/V counter reset switch On / Off 0 : self counter reset OFF (default) 1 : self counter reset ON Note : this mode is ONLY valid at when 70h[1: 0] is "10(bin)" or "11(bin)". : color bar select 0 : color bar 1 : color bar Luma 100% 100% Chroma 75% 100%
self - SW
color bar select
VBLK SW
: Vertical Blanking Mask Enable switch On-Off 0 : reject VBI information data in vertical blanking period (default) 1 : through VBI information data in vertical blanking period : Composite sync/Frame sync output switch 0 : Frame sync output (default) 1 : composite sync output : Frame sync /Vertical sync output switch 0 : Vertical sync output (default) 1 : Frame sync output
C/Fsync SW
F/Vsync SW
M/S sync mode1 : Master or Slave sync mode M/S sync mode0 00 : 601 H/V master mode 01 : 656 slave mode(no H/Vsync output) (default) 10 : Fsync/Hsync slave mode 11 : Vsync/Hsync slave mode
No. 30
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
Sub-address 71 : Sync control (write/read)
MSB Register 71 non-inter VBI SW h-polarity v-polarity f-polarity h- delay2 h-delay1
LSB h-delay0
default : 0000_0100(bin)
non-inter
: non-interlaced mode select 0 : interlace mode (default) 1 : non-interlace mode : vertical blanking information signal input control switch on 48 pin 0 : VBI input Off (default) 1 : VBI input On : polarity of Hsync 0 : negative (default) 1 : positive : polarity of Vsync 0 : negative (default) 1 : positive : polarity of Fsync 0 : field1 (odd) = low level (default) 1 : field1 (odd) = high level : delay on Hsync with reference to DVIA/DVIB data in Master mode 000: + 4 clock delay 001: + 3 clock delay 010: + 2 clock delay 011: + 1 clock delay 100: + 0 clock delay 101: - 1 clock delay 110: - 2 clock delay 111: - 3 clock delay Note : this h-delay can be also related with 7A[7:0] register and can delay totally +2023 clock delay in H/V or H/Fsync slave mode.
VBI SW
h-polarity
v-polarity
f-polarity
h-delay2 h-delay1 h-delay0
No. 31
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
Sub-address 72 : PAL/NTSC setup (write / read)
MSB Register 72
phase-set TEST
C/Fsync/VBI I/O SW
LSB color bar setup75 625/525
PAL/ NTSC2 PAL/ NTSC1
default : 0000_1000(bin) NTSC (If "PAL/NTSC" pin is LOW level) 0000_0101(bin) PAL
phase-set
: color sub-carrier phase synchronization 0 : free running (default) 1 : 1 phase reset/8 field and 1 phase reset/4 frame : for test, should be "0" : Input/Output switch on 48 pin (C/Fsync/VBI pin ) 0 : VBI input(default) 1 : Csync or Frame sync output : internal color bar generator control 0 : normal operation (default) 1 : color bar generator On (need to set color bar mode on sub-address 70[5]. ) : Setup level for Luminance 0 : setup level for luminance = 0IRE 1 : setup level for luminance = 7.5IRE
TEST C/Fsync/VBI I/O SW color bar
setup75
625/525 : control line mode 0 : 525 lines / 60 Hz mode 1 : 625 lines / 50 Hz mode PAL/NTSC2 PAL/NTSC1 : subcarrier control 00 : NTSC(M) 01 : PAL (BDGHI) 10 : PAL (M) 11 : PAL (N)
No. 32
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
Sub-address 73: Vertical Blanking Information Luma (Y) Level (write only) MSB Register 73 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 LSB
default : 1000_0000(bin)
Sub-address 74: Burst Chroma (U) Level (write only)
MSB Register 74 U7 U6 default : U5 77(dec) (NTSC) 89(dec) (PAL) U4 U3 U2 U1 U0
LSB
Sub-address 75: Burst Chroma (V) Level (write only)
MSB Register 75 V7 V6 V5 V4 V3 V2 V1 V0
LSB
default : 128(dec) (NTSC) 155(dec) (PAL)
No. 33
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
Sub-address 76 : DAC set 1 signal control (write only) MSB Register 76 Cr Cb Luma dac 1pin dac 7pin
dac 4pin dac set 1 mode[1]
LSB
dac set 1 mode[0]
default : 0000_0000(bin)
Cr Cb Luma
: Cr/Cb signal control (Data path enable) 0 : Cr, Cb On (default) 1 : chrominance Off : Luminance control (Data path enable) 0 : luminance On (default) 1 : luminance Off : D/A converter (1) output On-Off control 0 : CVBS/Cb/BDAC1, C/Cr/RDAC1, Y/GDAC1 output On (default) 1 : CVBS/Cb/BDAC1, C/Cr/RDAC1, Y/GDAC1 output Off : 1~9-pin's D/A converter output signal control 01 or 11 : R/G/B output On 10 : Y/Cr/Cb output On 00 : Y/C/CVBS output On
dac 1pin dac 4pin dac 7pin dac set 1 mode
Sub-address 77 : DAC set 2 signal control (write only ) MSB Register 77 B R G dac 17pin dac 23pin dac 20pin
dac set 2 mode[0]
LSB
dac set 2 mode[0]
default : 0000_0001(bin)
B R G dac 17pin dac 20pin dac23pin dac set 2 mode
: B/R/G signal control (Data path enable ) 0 : B/R/G signal On (default) 1 : B/R/G signal Off : D/A converter (2) output On-Off control 0 : CVBS/Cb/BDAC2, C/Cr/RDAC2, Y/GDAC2 output On (default) 1 : CVBS/Cb/BDAC2, C/Cr/RDAC2, Y/GDAC2 output Off : 17~25-pin's D/A converter (2) output signal control 01 or 11 : R/G/B output On (default) 10 : Y/Cr/Cb output On 00 : Y/C/CVBS output On
No. 34
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
Sub-address 78~79 : Sub-carrier phase control (write only)
MSB Register 78 sc-ph9 sc-ph8 sc-ph7 sc-ph6 sc-ph5 sc-ph4 sc-ph3
LSB sc-ph2
default : 0000_0000(bin)
MSB Register 79 sc-ph1
LSB sc-ph0
default : 0000_0000(bin)
sc-ph9 sc-ph8 sc-ph7 sc-ph6 sc-ph5 sc-ph4 sc-ph3 sc-ph2 sc-ph1 sc-ph0
: sub-carrier phase control 00_0000_0000 : sub-carrier phase 0 degree (default) to 11_1111_1111 : sub-carrier phase 359 degree
No. 35
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
Sub-address 7A : Hsync delay control (write only) MSB Register 7A H-delay10 H-delay9 H-delay8 H-delay7 H-delay6 H-delay5 H-delay4
default : 0000_0000(bin)
LSB H-delay3
h-delay10 h-delay9 h-delay8 h-delay7 h-delay6 h-delay5 h-delay4 h-delay3
: delay on Hsync with reference to DVIA/DVIB data 0000_0000_000 : Hsync delay 0 delay to 1111_1111_000 : Hsync delay +255 delay
Note : this h-delay can be also related with 71[3:0] register and can delay totally +2023 delay(1111_1111_111) in H/V or H/ Fsync slave mode.
Sub-address 7B : Digital Video Input Select Control (write only)
MSB Register 7B Cr_tmg[1] Cr_tmg[0] Cb_tmg[1] Cb_tmg[0] Y_tmg
LSB
16-bit input mode
default : 0000_0000(bin)
Cr_tmg
: Cr clock timing delay in 16-bit Digital Input Mode 00 : Cr clock delay 0 clock (default) 01 : Cr clock delay +1 clock 10 : Cr clock delay +2 clock 11 : Cr clock delay +3 clock
(See fig 3,4 )
Cb_tmg
: Cb clock timing delay in 16-bit Digital Input Mode 00 : Cb clock delay 0 clock (default) 01 : Cb clock delay +1 clock 10 : Cb clock delay +2 clock 11 : Cb clock delay +3 clock (See fig 3,4 ) : Y clock timing delay in 16-bit Digital Input Mode 0 : Y clock delay 0 clock (default) 1 : Y clock delay +1 clock : 16-bit YY / CbCr Digital Video Input mode 0 : 8-bit Multiplexed CbYCrY Digital Video Input mode (default) 1 : 16-bit YY / CbCr Digital Video Input mode
Y_tmg
16-bit input mode
No. 36
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
Sub-address 7C : signal control 3(write only)
MSB Register 7C Ysync R/B sync G sync
R/B CGMS G CGMS RGB bf
LSB CbCr bf
Chroma bf
default : 0000_0000(bin)
Y sync
: Y sync Signal On/Off (Y/Cb/Cr mode only) 0 : Y sync On (default) 1 : Y sync Off : R/B sync signal On/Off 0 : R/B sync Off (default) 1 : R/B sync On : G sync signal On/Off 0 : G sync Off (default) 1 : G sync On : R/B CGMS data Insertion On/Off 0 : CGMS data On 1 : CGMS data off : G CGMS data Insertion On/Off 0 : CGMS data On 1 : CGMS data off : RGB burst level On/Off 0 : RGB bf data Off 1 : RGB bf data On : CbCr burst On/Off 0 : Cb/Cr bf data Off 1 : Cb/Cr bf data On : Chroma burst On/Off 0 : Chroma bf data On 1 : Chroma bf data off
R/B sync
G sync
R/B CGMS
G CGMS
RGB bf
CbCr bf
Chroma bf
No. 37
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
Sub-address 7D~7E : Vsync delay control (write only) MSB Register 7D V-delay7 V-delay6 V-delay5 V-delay4 V-delay3 V-delay2 V-delay1
default : 0000_0000(bin)
LSB V-delay0
MSB Register 7E V-delay9
LSB V-delay8
default : 0000_0000(bin)
V-delay9 V-delay8 V-delay7 V-delay6 V-delay5 V-delay4 V-delay3 V-delay2 V-delay1 V-delay0
: delay on Vsync with reference to DVIA/DVIB data in slave mode 0000_0000_00 : Vsync delay 0 delay to 1111_1111_11 : Hsync delay +1023 delay
No. 38
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
Sub-address 80~82: CGMS characters for Field1(Line20)/Field2(Line283) (write only) MSB Register 80 MSB Register 81 cgms15 b16 MSB Register 82 XX XX XX XX cgms19 b20
11.2 S 2.235 S 70IRE 49.1 S
NTSC only LSB
cgms7 b8
cgms6 b7 cgms14 b15
cgms5 b6 cgms13 b14
cgms4 b5 cgms12 b13
cgms3 b4 cgms11 b12
cgms2 b3 cgms10 b11 cgms18 b19
cgms1 b2 cgms9 b10 cgms17 b18
cgms0 b1 LSB cgms8 b9 LSB cgms16 b17
0IRE
Ref
b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b12 b14 b16 b18 b20 b11 b13 b15 b17 b19
-40IRE
Fig 24 : CGMS wave form
Sub-address 80~81: WSS characters for Line23 (write only) MSB Register 80 MSB Register 81 b16 b15 wss13 b14 wss12 b13 wss11 b12 wss10 b11 wss7 b8 wss6 b7 wss5 b6 wss4 b5 wss3 b4 wss2 b3
PAL only LSB wss1 b2 wss9 b10 wss0 b1 LSB wss8 b9
500mV
11.0 S
27.4 S 38.4 S 44.5 S
Fig 25 : WSS wave form
No. 39
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
Sub-address 83~84 :closed caption characters/extended data for Field1(Line21) (write) First byte to Encode MSB Register 83 ccp118 ccb117 b7 ccb116 b6 ccb115 b5 ccb114 b4 ccb113 b3 ccb112 b2 ccb111 b1 LSB ccb127 b7 ccb126 b6 ccb125 b5 ccb124 b4 ccb123 b3 ccb122 b2 ccb121 b1
LSB
parity Second byte to Encode MSB Register 84 ccp128 parity
Sub-address 85~86 :closed cation character/extended data for Field2(Line284) First byte to Encode MSB Register 85 ccp218 ccb217 b7 ccb216 b6 ccb215 b5 ccb214 b4 ccb213 b3 ccb212 b2
LSB ccb211 b1 LSB ccb227 b7 ccb226 b6
4.15 S 12.91 S 33.764 S 50IRE
parity Second byte to Encode MSB Register 86 ccp228 parity
ccb225 b5
ccb224 b4
ccb223 b3
ccb222 b2
ccb221 b1
10.50 S 50IRE
0IRE
-40IRE
bbbb bb bp bbbbb bb 1234 56 7a 12345 67 CHARACTER1 r CHARACTER2 i t y
p a r i t y
0IRE
Fig 26 : Closed caption wave form
Note : This Closed Caption wafeform is defined by when the register $72 [3] = "1" is set. sub-address 80, 81, 82, 83, 84, 85 and 86 (previous frame data) are double-buffered by Frame sync falling edge
Fsync
Field 1
Field 2
Fig 27 : VBI data update timing
No. 40
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
Sub-address 87 :Closed caption/CGMS
MSB Register 87 CC2_flag CC1_flag CC_null CC_parity default 00h WSS CGMS CC2 CC1
LSB
CC2_flag : Closed Caption Status Flag for field2/field1 ( Read only) CC1_flag 0 : Automatically set to " 1 " when 2-byte Closed Caption data are written, and then cleared to "0" when the data is send to doubled buffer 1 : Do NOT work " 1 " to these bits. " 0 " is correct. CC_null : Automatically set the null code when the data is send to doubled buffer 0 : Keep the current CC data in the resister. 1 : Automatically set the null code in the CC data resister CC_parity: CC Parity Generation On-Off 0 : Use parity bit in data. (default) 1 : Automatically generate parity bit. WSS : WSS information data insertion On-Off 0 : WSS information data insertion Off 1 : WSS information data insertion On
CGMS : CGMS information data insertion On-Off 0 : CGMS information data insertion Off 1 : CGMS information data insertion On CC2 : closed caption/extended data for field2 encoding On-Off 0 : closed caption/extended data for field2 encoding Off 1 : closed caption/extended data for field2 encoding On : closed caption/extended data for field1 encoding 0 : closed caption/extended data for field1 encoding Off 1 : closed caption/extended data for field1 encoding On
CC1
No. 41
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
I2C-BUS Slave Receiver Sub-address map
70h:[7] [6] [5] [4] [3] [2] [1:0] 71h:[7] [6] [5] [4] [3] [2:0] 72h:[7] [6] [5] [4] [3] [2] [1:0]
73h[7:0] 74h[7:0] 75h[7:0] 76h[7] [6] [5] [4:2] [1:0] 77h[7:5] [4:2] [1:0]
burst control (default 0:on) self counter reset switch (default 0:off) color bar select (default 0:Luma 100% Chroma 75%) vertical blanking switch(default 0:off) 48 pin output mode select (Csync:1, Flame sync:0) F/Vsync select(default 0:Vsync) Master/Slave mode select(default 01:656_slave) interlaced / non-interlaced (default 0:interlaced) VBI input control on 48 pin (default 0:off) horizontal sync polarity (default 0) vertical sync polarity (default 0) frame sync polarity (default 0) hsync delay control (default 100:0 clock delay) (In slave mode can use with 7A[7:0]) sub-carrier phase synchronization(default 0) Test mode (default 0:off) 48 pin I/O switch(default 1:cysnc output) color bar generate(default 0:off) setup level control(default 1:7.5IRE) 625lines50Hz/525Lines60Hz (default set PAL/NTSC pin) PAL/NTSC (default set PAL/NTSC pin) 00:NTSC/M 01:PAL/BDGHI (10:PAL/M) (11:PAL/N) VBI LUMA level register(default 80h) Burst U_register(default 79d:ntsc/157d:PAL) Burst V_register(default 128d:ntsc/107d:PAL) Cr on/off (default 0:on) Cb on/off (default 0:on) Luma on/off(default 0:on) (default 0: on) 1pin dac/4pin dac/7pin dac on/off(default 0: on) 1st set D/A converter output signal control (default 00 : CBVS/Y/C output) B/R/G signal control (default 0: On) 17pin dac/20pin dac/23pin dac on/off(default 0: on) 2ndt set D/A converter output signal control (default 01 : R/G/B output) sub-carrier phase control(default 00h) sub-carrier phase control(default 00) n.a.
6Eh[7:4] 6Eh[3] 6Eh[2] 6Eh[1:0] 6F[7:6] 6F[5:0] 7A[7:0] 7B[7:6] [5:2] [1] [0] 7C[7] [6] [5] [4] [3] [2:1] [0] 7D[7:0] 7E[7:2] [1:0] 7Fh 80~82h 80~81h 83h[7:0] 84h[7:0] 85h[7:0] 86h[7:0] 87h[7:6] [5] [4] [3] [2] [1] [0]
n.a. Cb/Cr gain control Y mode switch M2/Beta Cam select n.a. Interpolation filter switch hsync-delay control (In slave mode, is valid with 71h[2:0] register) n.a.. Cr/Cb clock timing delay in 16-bit digital input mode (default 00: clock delay 0) Y clock timing delay in 16-bit digital input mode (default 0: clock delay 0) 16-bit multiplexed CbYCrY digital video input mode (default 0: 8-bit YCrCb digital video input mode) Ysync signal On/Off(YCrCb mode only)(default 0: On) R/Bsync signal On/Off(default 0: Off) Gsync signal On/Off(default 0: Off) R/B CGMS data insertion On/Off(default 0: On) G CGMS data insertion On/Off(default 0: On) RGB/CbCr burst On/Off(default 0: On) Chroma burst On/Off(default 0: On) delay on Vsync with reference to DVIA/DVIB data in slave mode n.a. delay on Vsync with reference to DVIA/DVIB data in slave mode DVE Version number CGMS characters for field1(line20)/field2(line283) WSS characters for field1(line23) CC character1(line21) (default 'h80) CC character2(line21) (default 'h80) CC character1(line284) (default 'h80) CC character2(line284) (default 'h80) Closed Caption Status Flag for field2 Automatic set to null code(Closed Caption data) Automatic generate CC parity bit (default 0: off) WSS information data insertion on/off (default 0: off) CGMS on/off (default 0: off) CC closed caption/extended data for field2 encoding (default 0: off) CC closed caption/extended data for field1 encoding (default 0: off)
78h[7:0] 79h[1:0] 79h[7:2]
<<<<<<<< I2C-BUS Format >>>>>>
** WRITE MODE ** S | Slave_address(W) | A | Sub_address | A | Data0 | A | ... | DataN | A | P S Slave_address A Sub_address Data0 DataN P Start condition 40(hex) or 1E(hex) Acknowledge generated by DVE Sub_address register First data Continued data(address is auto incremented) Stop condition
<<<<<<<< SPI-Bus Format >>>>>> ** WRITE MODE ** S | Write Command | Sub_address | Data0 | ... | DataN | P S Write Command Sub_address Data0 DataN P Chip select on (High to Low) 40(hex) or 1E(hex) Sub_address byte First data Continued data byte(address is auto incremented) Chip select off (Low to High)
No. 42
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
[ Application Diagram 1 ]
DVdd
47uF 0.01uF
58
61
64
57
54
51
60
63
56
53
50 Hsync
59
62
DVss
55
DVIB4
DVIB5
DVIB6
DVIB7
DVdd
52
A/B_sel
DVIB2
DVIB1
DVIB3
CVBS
180
1 2 3 4
F / Vsync
DVIB0
NC
NC
TP
49
CVBS / Cb / B1 CVBS / Cb / B1 CVBS / Cb / B1 Vdd Y / G1 Y / G1 Y / G1 Vdd C / Cr / R1 C / Cr /R1 C / Cr / R 1Vdd DAVss Ibias1 Vreff1 DAVdd Vreff2 CVBS / Cb / B2 Vdd Ibias2 CVBS / Cb / B2 CVBS / Cb / B2 NC C / Cr / R2 Vdd
C/Fsync/VBI Vmute DVIA0 DVIA1 DVIA2 DVIA3
48 47 46 45 44 43 42 41 40 39 38 37
Y
0.01uF 47uF 180 0.01uF 47uF
MPEG DECODER
5 6
C
47uF 0.01uF
180
7 8 9 10
MC44724A MC44725A
DVIA4 DVIA5 DVIA6 DVIA7 DVss DVdd SEL SCL/SCK SDA/SI
2k
1.8K 47uF
11 12 13 14
4.7k
36 35 34 33
1k 0.01uF
0.01uF 1.8K
MCU
47uF
15 16
4.7k
Y / G 2Vdd
Y / G2
Y /2 G
ChipA
DVdd
TEST
DVss
23
20
17
24
27
30
21
18
25
28
31
Reset
clock
2k
22
19
1k 0.01uF
180 180 180
26
29
32
PAL/NTSC
SO
C / Cr / R2
C / Cr / R2
If NTSC system = "0" else PAL system = "1" 100k 10uF
0.01uF 47uF
0.01uF
47uF
47uF
0.01uF
clock
G
B
No. 43
R
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
0.01uF
[ Application Diagram 2 ]
other DECODER or OSD
DVdd
47uF 0.01uF
62
58
55
52
61
64
57
54
51
60
63
56
53
50 Hsync
59
DVss
A/B_sel
CVBS
180
1 2 3 4
F / Vsync
DVIN3
DVIB0
DVdd
DVIB2
DVIB4
DVIB1
DVIB6
TP
DVIB5
DVIB7
NC
NC
49
CVBS / Cb / B1 CVBS / Cb / B1 CVBS / Cb / B1 Vdd Y / G1 Y / G1 Y / G1 Vdd C / Cr / R1 C / Cr /R1 C / Cr / R 1Vdd DAVss Ibias1 VReff1 DAVdd VReff2 CVBS / Cb / B2 Vdd Ibias2 CVBS / Cb / B2 CVBS / Cb / B2 NC C / Cr / R2 Vdd
C/Fsync/VBI Vmute DVIA0 DVIA1 DVIA2 DVIA3
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
Y
0.01uF 47uF 180 0.01uF 47uF
MPEG DECODER
5 6
C
47uF 0.01uF
180
7 8 9 10
MC44724A MC44725A
DVIA4 DVIA5 DVIA6 DVIA7 DVss DVdd SEL SCL/SCK SDA/SI
2k
1.8K 47uF
11 12 13 14
1k 0.01uF
0.01uF 1.8K
Y / G 2Vdd
Y / G2
Y /2 G
ChipA
DVdd
TEST
DVss
19
23
26
29
20
17
24
27
30
21
18
25
28
31
Reset
clock
2k
1k 0.01uF
180 180 180
22
32
PAL/NTSC
C / Cr / R2
C / Cr / R2
16
SO
If NTSC system = "0" else PAL system = "1" 100k 10uF
0.01uF 47uF
0.01uF
47uF
47uF
0.01uF
clock
G
B
No. 44
R
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
MCU
15
0.01uF
4.7k
47uF
4.7k
64-VQFP Package
HD D
Detail A
L1 L c
HE
E
min A A1 A2 b c Detail A A2 D E e HD A1 ZD or ZE e b A HE L L1
o
max 1.70 0.15 1.40TYP
0.05
0.18 0.10 9.90 9.90 0.50 11.80 11.80 0.50TYP 0.80 0 1.25TYP 1.25TYP
0.27 0.20 10.1 10.1
12.20 12.20
1.20 10 0.10
y ZD ZE
unit : mm
No. 45
This document contains information on a new product. Specifications and information herein are subject to change without notice.
MC44724A/5A Rev 0.05 07/15/98
o

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