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| CMOS Low Power Consumption Input Frequencies : 14KHz to 35MHz Divider Ratios : 1 to 2047 divisions (laser trimming) Multiplier Ratios : 20 to 2047 multiplications (laser trimming) Comparative Frequencies : 14KHz to 500KHz Output Frequencies : 9MHz to 80MHz Mini Mold SOT-26 Package General Description The XC25BS3 series are high frequency, low power consumption PLL clock generator ICs with built-in crystal oscillator circuits, divider circuits & multiplier PLL circuits. Laser trimming gives the option of being able to select from divider ratios (M) of 1 to 2047 and multiplier ratios (N) of 20 to 2047. Output frequency (Qo) is equal to reference oscillation (f0) multiplied by N/M, within a range of 9MHz to 80MHz. Q1 output is selectable from reference oscillation, comparative frequencies, PLL output frequencies /2, comparative frequencies/2. Further, comparative frequencies, within a range of 14KHz to 500KHz, can be obtained by dividing the reference oscillation. By halting oscillation via the CE pin, consumption current can be controlled. Output will be one of high impedance. Applications Crystal Oscillation Modules Personal Computers PDAs Portable Audio Systems Various System Clocks Features Output Frequencies : 9MHz to 80MHz (Qo = f0 x N/M) Reference Oscillation (f0) : 14KHz to 35MHz Divider Ratios (M) : Selectable from divisions of 1 to 2047 Multiplier Ratios (N) : Selectable from multiplications of 20 to 2047 Output : 3 State Q1 output selectable from reference oscillation, compar ative frequencies, PLL output frequencies/2, comparative frequencies/2. Operating Voltage Range : 3.0V to 5.5V Low Power Consumption : CMOS ( standby function included) * Ultra Small Package : SOT - 26 mini mold * High output impedance during standby Pin Configuration Pin Assignment PIN NUMBER 1 2 3 4 5 6 SOT-26 (TOP VIEW) PIN NAME CE Vss Qo Q1 VDD CLKin FUNCTION Chip Enable GND PLL Output Reference Oscillation, PLL Output/2, Comparative Frequencies, Comparative Frequencies/2 Output Power Supply Standard Clock Input CE VSS Q0 1 2 3 6 5 4 C L K in VDD Q1 CE, Q0/Q1 Pin Function Block Diagram V DD 1 1 b it P L L (xN ) CE H L Open FUNCTION Qo/Q1 clock output. Standby. Output pin = high impedance Standby. Output pin = high impedance (VSS pin pull down due to IC's internal resistance) Q0 C L K in 1 1 b it 1 /M C o u n te r 1 2 1 2 CE Fuse S e le c t Q1 VSS Absolute Maximum Ratings PARAMETER Supply Voltage CLKin Pin Voltage CE Pin Voltage Qo Pin Voltage Q1 Pin Voltage Qo Output Current Q1 Output Current Power Dissipation Ambient Temp. Storage Temp. SYMBOL VDD VCK VCE VQO VQ1 IQO IQ1 PD Topr Tstg CONDITIONS VSS - 0.3 to VSS + 7.0 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to VDD + 0.3 +/- 50 +/- 50 150 -30 to +80 -40 to +125 Ta=25 OC UNITS V V V V V mA mA mW O C O C B B |
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