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74AC399 * 74ACT399 Quad 2-Port Register
June 1988 Revised October 2000
74AC399 * 74ACT399 Quad 2-Port Register
General Description
The AC/ACT399 is the logical equivalent of a quad 2-input multiplexer feeding into four edge-triggered flip-flops. A common Select input determines which of the two 4-bit words is accepted. The selected data enters the flip-flop on the rising edge of the clock.
Features
s ICC reduced by 50% s Select inputs from two data sources s Fully positive edge-triggered operation s Outputs source/sink 24 mA s AC/ACT399 has TTL-compatible inputs
Ordering Code:
Order Number 74AC399SC 74AC399PC 74ACT399SC 74ACT399SJ 74ACT399MTC 74ACT399PC Package Number M16A N16E M16A M16D MTC16 N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names S CP I0a-I0d I1a-I1d Qa-Qd Description Common Select Input Clock Pulse Input Data Inputs from Source 0 Data Inputs from Source 1 Register True Outputs
FACT is a trademark of Fairchild Semiconductor Corporation.
(c) 2000 Fairchild Semiconductor Corporation
DS009789
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74AC399 * 74ACT399
Functional Description
The AC/ACT399 is a high-speed quad 2-port register. It selects four bits of data from either of two sources (Ports) under control of a common Select input (S). The selected data is transferred to a 4-bit output register synchronous with the LOW-to-HIGH transition of the Clock input (CP). The 4-bit D-type output register is fully edge-triggered. The Data inputs (I0x, I1x) and Select input (S) must be stable only a setup time prior to and hold time after the LOW-toHIGH transition of the Clock input for predictable operation.
Function Table
Inputs S L L H H I0 L H X X I1 X X L H CP Outputs Q L H L H Q H L H L
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition

Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74AC399 * 74ACT399
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) PDIP
-0.5V to +7.0V -20 mA +20 mA -0.5V to VCC + 0.5V -20 mA +20 mA -0.5V to VCC + 0.5V 50 mA 50 mA -65C to +150C +140C
Recommended Operating Conditions
Supply Voltage (VCC) AC ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (V/t) AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (V/t) ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT circuits outside databook specifications.
2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC
-40C to +85C
125 mV/ns
DC Electrical Characteristics for AC
Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Maximum LOW Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 IIN IOZ Maximum Input Leakage Current Maximum 3-STATE Current IOLD IOHD ICC Minimum Dynamic Output Current (Note 3) Maximum Quiescent Supply Current 5.5 5.5 5.5 5.5 4.0 0.5 5.0 75 -75 40.0 A mA mA A 5.5 0.002 0.001 0.001 TA = +25C Typ 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36 0.1 TA = -40C to +85C Guaranteed Limits 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 VIN = VIL or VIH 2.46 3.76 4.76 0.1 0.1 0.1 VIN = VIL or VIH 0.44 0.44 0.44 1.0 A V IOL= 12 mA IOL = 24 mA IOL = 24 mA (Note 2) VI = VCC, GND VI (OE) = V IL, VIH VI = VCC, GND VO = VCC, GND VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND V IOUT = 50 A V IOH= -12 mA IOH= -24 mA IOH= -24 mA (Note 2) V IOUT = -50 A V VOUT = 0.1V or VCC - 0.1V V Units Conditions VOUT = 0.1V or VCC -0.1V
Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
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74AC399 * 74ACT399
DC Electrical Characteristics for ACT
Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 4.5 5.5 IIN ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum ICC/Input Minimum Dynamic (Note 6) Output Current Maximum Quiescent Supply Current
Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
TA = 25C Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.85 0.001 0.001 0.1 0.1 0.36 0.36 0.1 0.6
TA = -40C to +85C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 1.0 1.5 75 -75
Units V V V
Conditions VOUT = 0.1V or VCC -0.1V VOUT = 0.1V or VCC - 0.1V IOUT = -50 A VIN = VIL or VIH
V
IOH = -24 mA IOH = -24 mA (Note 5)
V
IOUT = 50 A VIN = VIL or VIH
V
IOL = 24 mA IOL = 24 mA (Note 5)
5.5 5.5 5.5 5.5 5.5
A mA mA mA A
VI = VCC, GND VI = VCC -2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or Ground
4.0
40.0
Note 5: All outputs loaded; thresholds on input associated with output under test.
AC Electrical Characteristics for AC
VCC Symbol Parameter (V) (Note 7) Min fMAX tPLH tPHL Input Clock Frequency Propagation Delay CP to Q Propagation Delay CP to Q
Note 7: Voltage Range 5.0 is 5.0V 0.5V
TA = +25C VCC = +5.0V CL = 50 pF Typ 160 190 7.5 5.0 7.0 5.0 10.0 8.0 9.5 7.5 Max 140 170 4.0 2.0 3.5 2.0
TA = -40C to +85C VCC = 5.0V CL = 50 pF Min 130 165 3.5 1.5 3.0 1.5 11.0 8.5 10.5 8.0 Max MHz ns ns Units
3.3 5.0 3.3 5.0 3.3 5.0
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74AC399 * 74ACT399
AC Operating Requirements for AC
VCC Symbol tS tH tS tH tW Parameter Setup Time, HIGH or LOW In to CP Hold Time, HIGH or LOW In to CP Setup Time, HIGH or LOW S to CP Hold Time, HIGH or LOW S to CP CP Pulse Width, HIGH or LOW
Note 8: Voltage Range 5.0 is 5.0V 0.5V
TA = +25C CL = 50 pF Typ 2.0 1.5 0.5 0.5 3.5 2.0 0.5 0.5 3.0 2.0 4.0 3.0 1.0 1.0 5.5 4.0 1.0 1.0 4.5 3.5
TA = -40C to +85C CL = 50 pF Guaranteed Minimum 4.0 3.0 1.0 1.0 5.5 4.0 1.0 1.0 4.5 3.5 ns ns ns ns ns Units
(V) (Note 8) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
AC Electrical Characteristics for ACT
VCC Symbol Parameter (V) (Note 9) Min fMAX tPLH tPHL Input Clock Frequency Propagation Delay CP to Q Propagation Delay CP to Q
Note 9: Voltage Range 5.0 is 5.0V 0.5V
TA = +25C VCC = +5.0V CL = 50 pF Typ 180 7.0 6.0 8.0 9.0 Max 165 1.5 2.0
TA = -40C to +85C VCC = 5.0V CL = 50pF Min 160 1.5 2.0 8.5 9.5 Max MHz ns ns Units
5.0 5.0 5.0
AC Operating Requirements for ACT
VCC Symbol Parameter (V) (Note 10) tS tH tS tH tW Setup Time, HIGH or LOW In to CP Hold Time, HIGH or LOW In to CP Setup Time, HIGH or LOW S to CP Hold Time, HIGH or LOW S to CP CP Pulse Width, HIGH or LOW
Note 10: Voltage Range 5.0 is 5.0V 0.5V
TA = +25C CL = 50 pF Typ 0.8 0 0.8 -1.0 1.7 2.5 1.0 4.0 0.5 3.5
TA = -40C to +85C CL = 50 pF Guaranteed Minimum 2.5 1.0 4.0 0.5 3.5 ns ns ns ns ns Units
5.0 5.0 5.0 5.0 5.0
Capacitance
Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 30 Units pF pF VCC = OPEN VCC = 5.0V Conditions
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74AC399 * 74ACT399
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A
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74AC399 * 74ACT399
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D
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74AC399 * 74ACT399
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16
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74AC399 * 74ACT399 Quad 2-Port Register
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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