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FEATURES +5 V, 5 V Power Supplies Ultralow Power Dissipation (<0.5 Low Leakage (<100 pA) Low On Resistance (<50 ) Fast Switching Times Low Charge Injection TTL/CMOS Compatible TSSOP Package W)
LC2MOS Precision 5 V Quad SPST Switches ADG661/ADG662/ADG663
FUNCTIONAL BLOCK DIAGRAM
S1 IN1 D1 S2 IN2 IN2 D2 S3 IN3 D3 S4 IN4 D4 S1 IN1 D1 S2 IN2 D2 S3 D3 S4 IN4 D4 SWITCHES SHOWN FOR A LOGIC "1" INPUT IN4 D4 D3 S4 IN1 D1 S2 D2 S3 S1
ADG661
IN3
ADG662
APPLICATIONS Battery Powered Instruments Single Supply Systems Remote Powered Equipment +5 V Supply Systems Computer Peripherals such as Disk Drives Precision Instrumentation Audio and Video Switching Automatic Test Equipment Precision Data Acquisition Sample Hold Systems Communication Systems
ADG663
IN3
GENERAL DESCRIPTION
The ADG661, ADG662 and ADG663 are monolithic CMOS devices comprising four independently selectable switches. These switches feature low, well-controlled on resistance and wide analog signal range, making them ideal for precision analog signal switching. They are fabricated using Analog Devices' advanced linear compatible CMOS (LC2MOS) process, which offers benefits of low leakage currents, ultralow power dissipation and low capacitance for fast switching speeds with minimum charge injection. The on resistance profile is very flat over the full analog input range ensuring excellent linearity and low distortion when switching audio signals. Fast switching speed coupled with high signal bandwidth also make the parts suitable for video signal switching. CMOS construction ensures ultralow power dissipation making the parts ideally suited for portable and battery powered instruments. The ADG661, ADG662 and ADG663 contain four independent SPST switches. The ADG661 and ADG662 differ only in that the digital control logic is inverted. The ADG661 switches are turned on with a logic low on the appropriate control input, while a logic high is required for the ADG662. The ADG663 has two switches with digital control logic similar to that of the ADG661, while the logic is inverted on the other two switches. REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Each switch conducts equally well in both directions when ON and has an input signal range that extends to the supplies. In the OFF condition, signal levels up to the supplies are blocked. All switches exhibit break-before-make switching action for use in multiplexer applications. Inherent in the design is low charge injection for minimum transients when switching the digital inputs.
PRODUCT HIGHLIGHTS
1. +5 V Single Supply Operation The ADG661, ADG662 and ADG663 offer high performance, including low on resistance and wide signal range, fully specified and guaranteed with 5 V and +5 V supply rails. 2. Ultralow Power Dissipation CMOS construction ensures ultralow power dissipation. 3. Low RON 4. Break-Before-Make Switching This prevents channel shorting when the switches are configured as a multiplexer.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1998
ADG661/ADG662/ADG663-SPECIFICATIONS1
Dual Supply (V
Parameter ANALOG SWITCH Analog Signal Range RON LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH DYNAMIC CHARACTERISTICS2 tON tOFF Break-Before-Make Time Delay, tD (ADG663 Only) Charge Injection OFF Isolation Channel-to-Channel Crosstalk CS (OFF) CD (OFF) CD, CS (ON) POWER REQUIREMENTS VDD IDD ISS +4.5/5.5 -4.5/5.5 0.0001 1 0.0001 1
NOTES 1 Temperature ranges are as follows: B Versions, -40C to +85C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice.
DD
= +5 V
10%, VSS = -5 V
10%, GND = 0 V, unless otherwise noted)
B Versions - 40 C to +85 C VDD to VSS Units V typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max ns typ ns max ns typ ns max ns typ pC typ dB typ dB typ pF typ pF typ pF typ V min/max V min/max A typ A max A typ A max VIN = VINL or VINH Test Conditions/Comments
+25 C
30 38 0.025 0.1 0.025 0.1 0.05 0.2
50
VD = -3.5 V to +3.5 V, IS = -10 mA; VDD = +4.5 V, VSS = -4.5 V VDD = +5.5 V, VSS = -5.5 V VD = 4.5 V, VS = 4.5 V; Test Circuit 2 VD = 4.5 V, VS = 4.5 V; Test Circuit 2 VD = VS = 4.5 V; Test Circuit 3
2.5 2.5 5 2.4 0.8
0.005
0.1
150 275 55 120 80 6 70 90 9 9 28
RL = 300 , CL = 35 pF; VS = 3 V; Test Circuit 4 RL = 300 , CL = 35 pF; VS = 3 V; Test Circuit 4 RL = 300 , CL = 35 pF; VS1 = VS2 = +3 V; Test Circuit 5 VS = 0 V, RS = 0 , CL = 10 nF; Test Circuit 6 RL = 50 , CL = 5 pF, f = 1 MHz; Test Circuit 7 RL = 50 , CL = 5 pF, f = 1 MHz; Test Circuit 8 f = 1 MHz f = 1 MHz f = 1 MHz
VDD = +5.5 V, VSS = -5.5 V Digital Inputs = 0 V or 5 V
-2-
REV. 0
ADG661/ADG662/ADG663 Single Supply (V
Parameter ANALOG SWITCH Analog Signal Range RON LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH DYNAMIC CHARACTERISTICS2 tON tOFF Break-Before-Make Time Delay, tD (ADG663 Only) Charge Injection OFF Isolation Channel-to-Channel Crosstalk CS (OFF) CD (OFF) CD, CS (ON) POWER REQUIREMENTS VDD IDD
DD
= +5 V
10%, VSS = 0 V, GND = 0 V, unless otherwise noted)
+25 C B Versions - 40 C to +85 C 0 V to VDD 45 68 0.025 0.1 0.025 0.1 0.05 0.2 75 Units V typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max ns typ ns max ns typ ns max ns typ pC typ dB typ dB typ pF typ pF typ pF typ +4.5/5.5 0.0001 1 V min/max A typ A max VIN = VINL or VINH Test Conditions/Comments
VD = 0 V to +3.5 V, IS = -10 mA; VDD = +4.5 V VDD = +5.5 V VD = 4.5 V/1 V, VS = 1 V/4.5 V; Test Circuit 2 VD = 4.5 V/1 V, VS = 1 V/4.5 V; Test Circuit 2 VD = VS = +4.5 V/+1 V; Test Circuit 3
2.5 2.5 5 2.4 0.8
0.005
0.1
250 400 45 100 140 12 70 90 9 9 28
RL = 300 , CL = 35 pF; VS = +2 V; Test Circuit 4 RL = 300 , CL = 35 pF; VS = +2 V; Test Circuit 4 RL = 300 , CL = 35 pF; VS1 = VS2 = +2 V; Test Circuit 5 VS = 0 V, RS = 0 , CL = 10 nF; Test Circuit 6 RL = 50 , CL = 5 pF, f = 1 MHz; Test Circuit 7 RL = 50 , CL = 5 pF, f = 1 MHz; Test Circuit 8 f = 1 MHz f = 1 MHz f = 1 MHz
VDD = +5.5 V Digital Inputs = 0 V or 5 V
NOTES 1 Temperature ranges are as follows: B Versions, -40C to +85C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice.
REV. 0
-3-
ADG661/ADG662/ADG663
ABSOLUTE MAXIMUM RATINGS 1
(TA = +25C unless otherwise noted)
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44 V VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +25 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to -25 V Analog, Digital Inputs2 . . . . . . . . . . . VSS -2 V to VDD +2 V or 30 mA, Whichever Occurs First Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA (Pulsed at 1 ms, 10% Duty Cycle max) Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150C TSSOP Package, Power Dissipation . . . . . . . . . . . . . . 450 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 115C/W JC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . 35C/W
Lead Temperature, Soldering Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2 Overvoltages at IN, S or D will be clamped by internal diodes. Current should be limited to the maximum ratings given.
ORDERING GUIDE
Model ADG661BRU ADG662BRU ADG663BRU
Temperature Range -40C to +85C -40C to +85C -40C to +85C
Package Description 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP
Package Option RU-16 RU-16 RU-16
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG661/ADG662/ADG663 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-4-
REV. 0
ADG661/ADG662/ADG663
PIN CONFIGURATION
IN1 1 D1 2 S1 3 VSS 4 GND 5
16 15
TERMINOLOGY
IN2 D2 S2 VDD
VDD VSS
12 NC TOP VIEW S4 6 (Not to Scale) 11 S3 10 9
ADG661 ADG662 ADG663
14 13
D4 7 IN4 8
D3 IN3
NC = NO CONNECT
Table I. Truth Table (ADG661/ADG662)
ADG661 In 0 1
ADG662 In 1 0
Switch Condition ON OFF
GND S D IN RON IS (OFF) ID (OFF) ID, IS (ON) VD (VS) CS (OFF) CD (OFF) CD, CS (ON) tON tOFF tD
Table II. Truth Table (ADG663)
Logic 0 1
Switch 1, 4 OFF ON
Switch 2, 3 ON OFF
Crosstalk
Off Isolation Charge Injection
Most positive power supply potential. Most negative power supply potential in dual supplies. In single supply applications, it may be connected to GND. Ground (0 V) Reference. Source Terminal. May be an input or output. Drain Terminal. May be an input or output. Logic Control Input. Ohmic resistance between D and S. Source leakage current with the switch "OFF." Drain leakage current with the switch "OFF." Channel leakage current with the switch "ON." Analog voltage on terminals D, S. "OFF" Switch Source Capacitance. "OFF" Switch Drain Capacitance. "ON" Switch Capacitance. Delay between applying the digital control input and the output switching on. Delay between applying the digital control input and the output switching off. "OFF" time or "ON" time measured between the 90% points of both switches, when switching from one address state to another. A measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. A measure of unwanted signal coupling through an "OFF" switch. A measure of the glitch impulse transferred from the digital input to analog output during switching.
REV. 0
-5-
ADG661/ADG662/ADG663 Typical Performance Characteristics
50 TA = +25 C 40 40 50 VDD = +5V VSS = -5V
40 VDD = +5V VSS = 0V 50 TA = +25C
30
RON -
RON -
30 +85 C 20 +25 C 10
RON -
30
20 VDD = +5V VSS = -5V
20
10
10
0 -5 -4 -3 -2
-1 0 1 23 4 5 VD OR VS - DRAIN OR SOURCE VOLTAGE - V
0 1 2 3 4 5 -5 -4 -3 -2 -1 0 VD OR VS - DRAIN OR SOURCE VOLTAGE - V
0
2 3 4 0 1 5 VD OR VS - DRAIN OR SOURCE VOLTAGE - V
Figure 1. On Resistance as a Function of VD (VS) Dual Supplies
Figure 2. On Resistance as a Function of VD (VS) for Different Temperatures
Figure 3. On Resistance as a Function of VD (VS) Single Supply
10mA 1mA VDD = +5V VSS = -5V
10 VDD = +5V VSS = -5V VS = 5V VD = 5V
120 VDD = +5V VSS = -5V
LEAKAGE CURRENT - nA
ID (OFF)
100 A
ISUPPLY
4 SW 10 A 1 SW 1A I-, I+
0.1
OFF ISOLATION - dB
1
100
80
ID (ON) 0.01 IS (OFF)
60
100nA
10nA
0.001
10 100 10k 100k 1M 1k FREQUENCY - Hz 10M
25
35
45 55 65 75 85 TEMPERATURE - C
95
105
40 100
1k
10k 100k FREQUENCY - Hz
1M
10M
Figure 4. Supply Current vs. Input Switching Frequency
Figure 5. Leakage Currents as a Function of Temperature
Figure 6. Off Isolation vs. Frequency
0.006 VDD = +5V VSS = -5V TA = +25 C ID(ON)
110 VDD = +5V VSS = -5V 100
0.004
LEAKAGE CURRENT - nA
0.002
ID(OFF) IS(OFF)
CROSSTALK - dB
90
0.000
80
-0.002
-0.004 -0.006 -5 -4 -3 -2 -1 0 1 2 3 4 5 VD OR VS - DRAIN OR SOURCE VOLTAGE
70
60 100
1k
10k 100k FREQUENCY - Hz
1M
10M
Figure 7. Leakage Currents as a Function of VD (VS)
Figure 8. Crosstalk vs. Frequency
-6-
REV. 0
ADG661/ADG662/ADG663 Test Circuits
IDS V1
IS (OFF) A
ID (OFF) S D A VD
VS S D
ID (ON) A VD
S VS
D
VS
RON = V1/IDS
1. On Resistance
2. Off Leakage
3. On Leakage
VDD 0.1 F 3V VDD S VS D RL 300 GND VSS VOUT CL 35pF VIN VIN ADG661 3V ADG662 50% 90% VOUT 50% 90% 50% 50%
IN
0.1 F VSS
tON
tOFF
4. Switching Times
VDD 0.1 F 3V VDD VS1 VS2 S1 S2 IN1, IN2 GND VSS D1 D2 RL2 300 VOUT2 CL2 35pF VOUT2 0V 0.1 F VSS 90% 90% RL1 300 CL1 35pF VOUT1 VOUT1 0V VIN 0V 50% 90% 50% 90%
VIN
tD
tD
5. Break-Before-Make Time Delay
VDD 3V VDD RS VS S D CL 10nF VOUT GND VSS VSS QINJ = CL VOUT VOUT VOUT VIN
IN
6. Charge Injection
REV. 0
-7-
ADG661/ADG662/ADG663 Test Circuits (Continued)
VDD 0.1 F
APPLICATION
S
D RL 50
VOUT
VS
VIN
IN GND VSS
Due to switch and capacitor leakage, the voltage on the hold capacitor will decrease with time. The ADG661/ADG662/ ADG663 minimizes this droop due to its low leakage specifications. The droop rate is further minimized by the use of a polystyrene hold capacitor. The droop rate for the circuit shown is typically 15 V/s. A second switch SW2, which operates in parallel with SW1, is included in this circuit to reduce pedestal error. Since both switches will be at the same potential, they will have a differential effect on the op amp OP07 which will minimize charge injection effects. Pedestal error is also reduced by the compensation network RC and CC. This compensation network also reduces the hold time glitch while optimizing the acquisition time. Using the illustrated op amps and component values, the pedestal error has a maximum value of 5 mV over the 3 V input range. The acquisition time is 2.5 ms while the settling time is 1.85 s.
+5V 2200pF
0.1 F VSS
7. Off Isolation
VDD 0.1 F
VDD S D 50
VS VOUT RL 50
VIN1 VIN2
SW1
+5V D RC 75 CC 1000pF CH 2200pF
D GND
S VSS
NC
VIN
+5V AD845
S SW2 S
OP07
VOUT
D
0.1 F VSS
CHANNEL TO CHANNEL CROSSTALK = 20 LOG VS/VOUT
-5V
-5V
8. Channel-to-Channel Crosstalk
ADG661 ADG662 ADG663
-5V
Figure 9. Accurate Sample-and-Hold
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead TSSOP (RU-16)
PRINTED IN U.S.A.
0.028 (0.70) 0.020 (0.50) 0.201 (5.10) 0.193 (4.90)
16 9
0.177 (4.50) 0.169 (4.30)
1
8
PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX 0.0118 (0.30) 0.0075 (0.19)
0.0256 SEATING (0.65) PLANE BSC
-8-
0.256 (6.50) 0.246 (6.25)
8 0 0.0079 (0.20) 0.0035 (0.090)
REV. 0
C3257-8-1/98
VDD
Figure 9 illustrates a precise, sample-and-hold circuit. An AD845 is used as the input buffer while the output operational amplifier is an OP07. During the track mode, SW1 is closed and the output VOUT follows the input signal VIN. In the hold mode, SW1 is opened and the signal is held by the hold capacitor CH.

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