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MA9264 MA9264
Radiation Hard 8192x8 Bit Static RAM
Replaces June 1999 version, DS3692-6.0 DS3692-7.0 January 2000
The MA9264 64k Static RAM is configured as 8192x8 bits and manufactured using CMOS-SOS high performance, radiation hard, 1.5m technology. The design uses a 6 transistor cell and has full static operation with no clock or timing strobe required. Address input buffers are deselected when chip select is in the HIGH state. See Application Note "Overview of the Dynex Semiconductor Radiation Hard 1.5m CMOS/SOS SRAM Range". Operation Mode Read Write Output Disable Standby CS L L L H X CE H H H X L OE WE L X H X X H L H X X I/O D OUT D IN High Z High Z X ISB2 ISB1 Power
FEATURES
s 1.5m CMOS-SOS Technology s Latch-up Free s Fast Access Time 70ns Typical s Total Dose 106 Rad(Si) s Transient Upset >1011 Rad(Si)/sec s SEU 4.3 x 10-11 Errors/bitday s Single 5V Supply s Three State Output s Low Standby Current 100A Typical s -55C to +125C Operation s All Inputs and Outputs Fully TTL or CMOS Compatible s Fully Static Operation
Figure 1: Truth Table
A12 A9 A8 A4 A3 A6 A5 A7
A D D R E S S B U F F E R
R O W D E C O D E R
CS CE WE OE
A10
A0
A1
A2
A11
Figure 2: Block Diagram
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SIGNAL DEFINITIONS
A0-12 Address input pins which select a particular eight bit word within the memory array. D0-7 Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write operation. CS Chip Select, which, at low level, activates a read or write operation. When at a high level it defaults the SRAM to a prechargencondition and holds the data output drivers in a high impedance state. WE Write Enable which when at a low level enables a write and holds data output drivers in a high impedance state. When at a high level, it enables a read. OE Output Enable which when at a high level holds the data output drivers in a high impedance state. When at a low level, data output driver state is defined by CS, WE and CE. If this signal is not used it must be connected to VSS. CE Chip Enable which when at a high level allows normal operation. When at a low level it defaults the SRAM to a precharge condition, disables the input circuits on all input pins and holds the data output drivers in a high impedance state. If this signal is not used it must be connected to VDD.
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CHARACTERISTICS AND RATINGS
Symbol VCC VI TA TS Parameter Supply Voltage Input Voltage Operating Temperature Storage Temperature Min. -0.5 -0.3 -55 -65 Max. 7.0 VDD+0.3 125 150 Units V V C C Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functlonal operation of the device at these condltions, or at any other condition above those indicated in the operations section of this specification, is not Implied Exposure to absolute maxlmum rating conditions for extended perlods may affect device reliability.
Figure 3: Absolute Maximum Ratings
Notes for Tables 4 and 5: Characteristics apply to pre radiation at TA = -55C to +125C with VDD = 5V 10% and to post 100k Rad(Si) total dose radiation at TA = 25C with VDD = 5V 10% (characteristics at higher radiation levels available on request). GROUP A SUBGROUPS 1, 2, 3. Symbol VDD VlH VlL VOH1 VOH2 VOL ILI ILO ISB1 Parameter Supply voltage Logical `1' Input Voltage Logical `0' Input Voltage Logical `1' Output Voltage Logical `1' Output Voltage Logical `0' Output Voltage Input Leakage Current Output Leakage Current Selected Static Current (CMOS) Conditions IOH1 = -2mA IOH2 = -1mA IOL = 4mA VIN = VDD or VSS All inputs Chip disabled, VOUT = VDD or VSS All inputs = VDD -0.2V except CS = VSS +0.2V fRC = 1MHz, all inputs switching, VIH = VDD -0.2V CS = VDD -0.2V CE = VSS +0.2V (TTL) (CMOS) (TTL) (CMOS) (Option) Min. 4.5 VDD/2 0.8 VDD VSS VSS 2.4 VDD -0.5 Typ. 5.0 0.1 Max. 5.5 VDD VDD 0.8 0.2 VDD 0.4 10 10 10 Units V V V V V V V V A A mA
IDD
Dynamic Operating Current (CMOS) Standby Supply Current
-
6
18
mA
ISB2
-
0.1
10
mA
Figure 4: Electrical Characteristics
Symbol VDR IDDR
Parameter VCC for Data Retention Data Retention Current
Conditions CS = VDR, CE = VSS CS = VDR, VDR = 2.0V CE = VSS
(Option)
Min. 2.0 -
Typ. 0.05
Max. 4
Units V mA
Figure 5: Data Retention Characteristics
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AC CHARACTERISTICS
Conditions of Test for Tables 5 and 6: 1. Input pulse = VSS to 3.0V (TTL) and VSS to 4.0V (CMOS). 2. Times measurement reference level = 1.5V. 3. Input Rise and Fall times 5ns. 4. Output load 1TTL gate and CL = 60pF. 5. Transition is measured at 500mV from steady state. 6. This parameter is sampled and not 100% tested. Notes for Tables 6 and 7: Characteristics apply to pre-radiation at TA = -55C to +125C with VDD = 5V10% and to post 100k Rad(Si) total dose radiation at TA = 25C with VDD = 5V 10%. GROUP A SUBGROUPS 9, 10, 11. Symbol TAVAVR TAVQV TEHQV TSLQV TEHQX (5,6) TSLQX (5,6) TELQZ (5,6) TSHQZ (5,6) TAXQX TGLQV TGLQX (5,6) TGHQZ (5,6) Parameter Read Cycle Time Address Access Time Chip Select Access Time Chip Enable Access Time Chip Selection to Output in Low Z Chip Enable to Output in Low Z Chip Deselection to Output in High Z Chip Disable to Output in High Z Output Hold from Address Change Output Enable Access Time Output Enable to Output in Low Z Output Enable to Output in High Z MAX9264X70 Min Max 70 15 15 0 0 30 15 0 65 70 70 20 20 25 20 MAX9264X95 Min Max 95 15 15 0 0 40 15 0 90 95 95 20 20 30 20 Units ns ns ns ns ns ns ns ns ns ns ns ns
Figure 6: Read Cycle AC Electrical Characteristics
Symbol TAVAVW TEHWH TSLWH TAVWH TAVWL TWLWH TWHAV TWLQZ (5,6) TDVWH TWHDX TWHQX (5,6)
Parameter Write Cycle Tlme Chip Selection to End of Write Chip Enable to End of Write Address Valid to End of Write Address Set Up Time Write Pulse Width Write Recovery Time Wnte to Output in High Z Data to Write Time Overlap Data Hold from Write Output Active from End to Write
MAX9264X70 Min Max 55 50 50 50 0 40 0 0 25 0 0 20 20
MAX9264X95 Min Max 60 60 60 55 0 45 0 0 30 0 0 20 20
Units ns ns ns ns ns ns ns ns ns ns ns
Figure 7: Write Cycle AC Electrical Characteristics
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Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions Vl = 0V VI/O = 0V Min. Typ. 3 5 Max. 5 7 Units pF pF
Note: TA = 25C and f = 1MHz. Data obtained by characterisation or analysis; not routinely measured.
Figure 8: Capacitance
Symbol FT
Parameter Basic Functionality
Conditions VDD = 4.5V - 5.5V, FREQ = 1MHz VIL = VSS, VIH = VDD, VOL 1.5V, VOH 1.5V TEMP = -55C to +125C, GPS PATTERN SET GROUP A SUBGROUPS 7, 8A, 8B
Figure 9: Functionality
Subgroup 1 2 3 7 8A 8B 9 10 11
Definition Static characteristics specified in Tables 4 and 5 at +25C Static characteristics specified in Tables 4 and 5 at +125C Static characteristics specified in Tables 4 and 5 at -55C Functional characteristics specified in Table 9 at +25C Functional characteristics specified in Table 9 at +125C Functional characteristics specified in Table 9 at -55C Switching characteristics specified in Tables 6 and 7 at +25C Switching characteristics specified in Tables 6 and 7 at +125C Switching characteristics specified in Tables 6 and 7 at -55C
Figure 10: Definition of Subgroups
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TIMING DIAGRAMS
TAVAVR ADDRESS TAVQV TSLQV CS TSLQX
HIGH IMPEDANCE
TAXQX
TSHQZ
DATA OUT
DATA VALID
TEHQX TEHQV CE TGLQX TGLQV TGHQZ TELQZ
OE
1. WE is high for Read Cycle. 2. Address Vaild prior to or coincident with CS transition low or CE transition high.
Figure 11a: Read Cycle 1
TAVAVR ADDRESS TAVQV DATA OUT
1. WE is high for Read Cycle. 2. Device is continually selected. CS, OE low, CE high.
TAXQX
DATA VALID
Figure 11b: Read Cycle 2
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TAVAVW
ADDRESS
TAVWH TAVWL
(4)
TWHAV (3) TWLWH (2)
WE
TAXQX TWLQZ TWLQX
(5) (6) (7)
DATA OUT
(8)
HIGH IMPEDANCE
TDVWH
DATA IN DATA VALID
TWHDX
TSLWH
CS
TEHWH
CE
1. WE must be high during all address transitions. 2. A write occurs during the overlap (TWLWH) of a low CS, a high CE and a low WE. 3. TWHAV is measured from either CS or WE going high or CE going low, whichever is the earlier, to the end of the write cycle. 4. If the CS low or CE high transition occurs simultaneously with, or after, the WE low transition, the output remains in the high impedance state. 5. DATA OUT is in the active state, so DATA IN must not be in the opposing state. 6. DATA OUT is the write data of the current cycle, if selected. 7. DATA OUT is the read data of the next address,if selected. 8. OE is low. (If OE is high then DATA OUT remains in the high impedance state throughout the cycle).
Figure 12: Write Cycle
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TYPICAL PERFORMANCE CHARACTERISTICS MAx9264x70
55
53
51
49
47
45
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72 68 64 60 56 52 48 44 40
64 62 60 58 56 54 52 50
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25
16 14
20
12 10
15
8 6
10
4 2
5
58 57 56 55 54 53 52 51 50 49 48
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OUTLINES AND PIN ASSIGNMENTS
D
14
1
15
28
W Seating Plane ME
A1 A
H e b Z 15
C e1
NC
1 2 3 4 5 6 7 8 9 Top View
28 VCC 27 W 26 CE 25 A8 24 A9 23 A11 22 OE 21 A10 20 CS 19 D/Q7 18 D/Q6 17 D/Q5 16 D/Q4 15 D/Q3
Ref A A1 b c D e e1 H Me Z W
Millimetres Min. 0.38 0.35 0.20 4.71 Nom. 2.54 Typ. 15.24 Typ. Max. 5.715 1.53 0.59 0.36 36.02 5.38 15.90 1.27 1.53 Min. 0.015 0.014 0.008 0.185 -
Inches Nom. 0.100 Typ. 0.600 Typ. Max. 0.225 0.060 0.023 0.014 1.418 0.212 0.626 0.050 0.060
A12 A7 A6 A5 A4 A3 A2 A1
A0 10 D/Q0 11 D/Q1 12 D/Q2 13 GND 14
XG404
Figure 13: 28-Lead Ceramic DIL (Solder Seal) - Package Style C
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MA9264
M b
D
Z
e L A c
ME Q
VCC 28 W 27 CE 26 A8 25
1 NC 2 A12 3 A7 4 A6 5 A5 6 A4 Bottom View 7 A3 8 A2 9 A1 10 A0 11 D/Q0 12 D/Q1 13 D/Q2 14 GND
Pin 1
A9 24 A11 23 OE 22 A10 21 CS 20 D/Q7 19 D/Q6 18 D/Q5 17 D/Q4 16 D/Q3 15
Ref A Q b c D e L M
Millimetres Min. 0.66 0.38 0.10 18.08 7.62 12.50 Nom. 1.27 Max. 3.18 0.48 0.18 18.49 9.91 12.09 Min. 0.026 0.015 0.004 0.712 0.300 0.492
Inches Nom. 0.050 Max. 0.125 0.019 0.007 0.728 0.390 0.508
XG530
Figure 14: 28-Lead Ceramic Flatpack (Solder Seal) - Package Style F
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MA9264
Pin N umbe r Option D a nd F A12 2 A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 A1 9 A0 10 D/Q0 11 D/Q1 12 D/Q2 13 GND(VSS) 14 D/Q3 15 D/Q4 16 D/Q5 17 D/Q6 18 D/Q7 19 CSB 20 A10 21 OEB 22 A11 23 A9 24 A8 25 CE 26 WB 27 VDD 28 Function Via R R R R R R R R R R R R Direct R R R R R R R R R R R R R Direct S ta tic 1 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 0V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V S ta tic 2 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 5V D yna mic Ra dia tion F14 F7 F9 F8 F11 F10 F5 F4 F3 F1 F1 F1 0V F1 F1 F1 F1 F1 F15 F2 F15 F6 F13 F12 F15B F0 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 0V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V
1. F0=150KHz, F1=F0/2, F2=F0/4, F3=F0/8 etc. 2. Static 1, Static 2 and Dynamic: R=4k7. 3. Radiation: R=10k.
Figure 15: Burnin and Radiation Configuration
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RADIATION TOLERANCE
Total Dose Radiation Testing For product procured to guaranteed total dose radiation levels, each wafer lot will be approved when all sample devices from each lot pass the total dose radiation test. The sample devices will be subjected to the total dose radiation level (Cobalt-60 Source), defined by the ordering code, and must continue to meet the electrical parameters specified in the data sheet. Electrical tests, pre and post irradiation, will be read and recorded. Dynex Semiconductor can provide radiation testing compliant with MIL-STD-883 test method 1019, Ionizing Radiation (Total Dose). Total Dose (Function to specification)* Transient Upset (Stored data loss) Transient Upset (Survivability) Neutron Hardness (Function to specification) Single Event Upset** Latch Up 1x105 Rad(Si) 5x1010 Rad(Si)/sec >1x1012 Rad(Si)/sec >1x1015 n/cm2 4.3x10-11 Errors/bit day Not possible
* Other total dose radiation levels available on request ** Worst case galactic cosmic ray upset - interplanetary/high altitude orbit
Figure 16: Radiation Hardness Parameters
SINGLE EVENT UPSET CHARACTERISTICS
UPSET BIT CROSS-SECTION (cm2/bit)
Ion LET (MeV.cm2/mg)
Figure 17: Typical Per-Bit Upset Cross-Section vs Ion LET
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ORDERING INFORMATION
Unique Circuit Designator
70 95
70ns Speed 95ns Speed
Radiation Tolerance S R Q Radiation Hard Processing 100 kRads (Si) Guaranteed 300 kRads (Si) Guaranteed
For radiation levels above those stated please contact Marketing
MAx9264xxxxxxxx
QA/QCI Process (See Section 9 Part 4)
Test Process (See Section 9 Part 3)
T C
TTL CMOS
Assembly Process (See Section 9 Part 2)
Package Type C F L N Ceramic DIL (Solder Seal) Flatpack (Solder Seal) Leadless Chip Carrier Naked Die
Reliability Level L C D E B S Rel 0 Rel 1 Rel 2 Rel 3/4/5/STACK Class B Class S
For details of reliability, QA/QC, test and assembly options, see `Manufacturing Capability and Quality Assurance Standards' Section 9.
http://www.dynexsemi.com e-mail: power_solutions@dynexsemi.com
HEADQUARTERS OPERATIONS DYNEX SEMICONDUCTOR LTD Doddington Road, Lincoln. Lincolnshire. LN6 3LF. United Kingdom. Tel: 00-44-(0)1522-500500 Fax: 00-44-(0)1522-500550 DYNEX POWER INC. Unit 7 - 58 Antares Drive, Nepean, Ontario, Canada K2E 7W6. Tel: 613.723.7035 Fax: 613.723.1518 Toll Free: 1.888.33.DYNEX (39639) CUSTOMER SERVICE CENTRES France, Benelux, Italy and Spain Tel: +33 (0)1 69 18 90 00. Fax: +33 (0)1 64 46 54 50 North America Tel: 011-800-5554-5554. Fax: 011-800-5444-5444 UK, Germany, Scandinavia & Rest Of World Tel: +44 (0)1522 500500. Fax: +44 (0)1522 500020 SALES OFFICES France, Benelux, Italy and Spain Tel: +33 (0)1 69 18 90 00. Fax: +33 (0)1 64 46 54 50 Germany Tel: 07351 827723 North America Tel: (613) 723-7035. Fax: (613) 723-1518. Toll Free: 1.888.33.DYNEX (39639) / Tel: (831) 440-1988. Fax: (831) 440-1989 / Tel: (949) 733-3005. Fax: (949) 733-2986. UK, Germany, Scandinavia & Rest Of World Tel: +44 (0)1522 500500. Fax: +44 (0)1522 500020 These offices are supported by Representatives and Distributors in many countries world-wide. (c) Dynex Semiconductor 2000 Publication No. DS3692-7 Issue No. 7.0 January 2000 TECHNICAL DOCUMENTATION - NOT FOR RESALE. PRINTED IN UNITED KINGDOM
Datasheet Annotations: Dynex Semiconductor annotate datasheets in the top right hard corner of the front page, to indicate product status. The annotations are as follows:Target Information: This is the most tentative form of information and represents a very preliminary specification. No actual design work on the product has been started. Preliminary Information: The product is in design and development. The datasheet represents the product as it is understood but details may change. Advance Information: The product design is complete and final characterisation for volume production is well in hand.
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company reserves the right to alter without prior notice the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request. All brand names and product names used in this publication are trademarks, registered trademarks or trade names of their respective owners.
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