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Preliminary Technical Data
FEATURES
100 MSPS sample rate SNR of 85 dBFS @10 MHz SFDR of 85 dBFS @10 MHz VSWR of 1:1.5 AC-coupled input signal conditioning Enhanced signal-to-noise ratio Differential ENCODE signal LVDS output levels Twos complement output data
16-Bit, 100 MSPS A/D Converter AD10680
FUNCTIONAL BLOCK DIAGRAM
ENCODE
AD10680
2 OVER RANGE DIGITAL POST PROCESSING ADC B 32 D0 TO D15 2 DATA CLOCK OUTPUT
ADC A AIN
Communications test equipment Radar and satellite subsystems Phased array antennas--digital beams Multichannel, multimode receivers Secure communications Wireless and wired communications
ENCODE
Figure 1.
PRODUCT HIGHLIGHTS
1. 2. 3. Guaranteed sample rate up to 100 MSPS. Input signal conditioning with optimized dynamic performance to 40 MHz. Additional performance options are available, such as increased SNR performance with digitally selectable input bandwidths, digitally selectable full-scale input ranges, and digitally selectable Nyquist zones. Contact sales for more information.
GENERAL DESCRIPTION
The AD10680 is a 16-bit analog-to-digital converter (ADC) with a transformer-coupled, analog input and digital postprocessing for enhanced signal-to-noise ratio (SNR). The product operates at a 100 MSPS conversion rate with outstanding dynamic performance. Internal filters can be digitally selected for the appropriate bandwidth or externally programmed. The AD10680 requires 5.0 V analog, 3.3 V analog, 3.3 V digital, 2.5 V digital, and a 1.2V digital supply, and a differential encode signal. No external reference is required. Performance is rated over a 0C to 60C case temperature range.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
06188-001
APPLICATIONS
AD10680 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 DC Specifications ......................................................................... 3
Preliminary Technical Data
AC Specifications ..........................................................................4 Pin Configurations and Function Descriptions ............................5 Theory of Operation .........................................................................6 Input Stage......................................................................................6 Encoding the AD10680 ................................................................6 Analog and Digital Power Supplies.............................................6 Analog and Digital Grounding....................................................6
REVISION HISTORY
6/06--Revision PrA: Initial Version
Rev. PrA | Page 2 of 8
Preliminary Technical Data SPECIFICATIONS
DC SPECIFICATIONS
AD10680
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD1 = 1.2 V, DRVDD2 = 2.5 V, DRVDD3 = 3.3 V, ENCODE = 100 MSPS, unless otherwise noted. Table 1.
Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error @ 10 MHz Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Gain Error ANALOG INPUT (AIN) Full-Scale Input Voltage Range Frequency Range Flatness (5 MHz to 45MHz) Input VSWR (50 ) (300 KHz to 50 MHz) Analog Input Bandwidth POWER SUPPLY Supply Voltage AVDD1 AVDD2 DRVDD1 DRVDD2 DRVDD3 Supply Current IAVDD1 (AVDD1 = 3.3 V) IAVDD2 (AVDD2 = 5.0 V) IDRVDD1 (DRVDD1 = 1.2 V) IDRVDD2 (DRVDD2 = 2.5 V) IDRVDD3 (DRVDD3 = 3.3 V) Total Power Dissipation ENCODE INPUTS Differential Inputs (ENC, ENC) Input Voltage Range Input Resistance Input Capacitance Common-Mode Voltage LOGIC INPUTS (RESET) Logic 1 Voltage Logic 0 Voltage Source IIH Source IIL LOGIC OUTPUTS (DRA, Output Bits) Differential Output Voltage Output Drive Current Output Common-Mode Voltage Start-Up Time Case Temp Test Level Min AD10680KWS Typ 12 Guaranteed 7 0.6 TBD TBD TBD 2.2 5 0.5 1.5 100 45 1.5 Max Unit Bits
60C 60C 60C 60C 60C 60C Full Full 60C 60C
IV I I V V V V IV IV V V
LSB %FS LSB LSB %/C V p-p MHz dB
MHz
Full Full Full Full Full 60C 60C 60C 60C 60C 60C
IV IV IV IV IV I I I I I I
3.3 5.0 1.2 2.5 3.3 750 450 600 500 140 7.15
V V V V V mA mA mA mA mA W
Full 60C 60C 60C Full Full 60C 60C Full Full Full Full
IV V V V IV IV V V IV IV IV IV
Rev. PrA | Page 3 of 8
0.4 100 4 3 2.0 0.8 10 1 247 -4 1.125 600 454 +4 1.375
V pF V V V A mA mV mA V ms
AD10680
AC SPECIFICATIONS
Preliminary Technical Data
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD1 = 1.2 V, DRVDD2 = 2.5 V, DRVDD3 = 3.3 V, ENCODE = 100 MSPS, unless otherwise noted. Table 2.
Parameter DYNAMIC PERFORMANCE SNR Analog Input @ -1.0 dBFS SINAD Analog Input @ -1.0 dBFS Spurious-Free Dynamic Range Analog Input @ -1.0 dBFS Two-Tone IMD 1 F1, F2 @ -6 dBFS SWITCHING SPECIFICATIONS Conversion Rate ENCODE Pulse Width High (tEH) ENCODE Pulse Width Low (tEL) DIGITAL OUTPUT PARAMETERS Valid Time (tV) Propagation Delay (tPD) Rise Time (tR) Fall Time (tF) DR PROPAGATION DELAY (tEDR) Data to DR Skew (tEDR - tPD) Pipeline Latency 2 Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ)
1 2
Conditions
Case Temp
Test Level
Min
AD10680KWS Typ Max
Unit
10 MHz 30 MHz 40 MHz 10 MHz 30 MHz 40 MHz 10 MHz 30 MHz 40 MHz
60C 60C Full 60C 60C Full 60C 60C Full 60C Full 60C 60C Full 60C 60C 60C 60C 60C Full 60C 60C
I I V I I V I I V V IV V V IV V V V V V IV V V
TBD TBD
85 84.5 83.5 84 83.5 83 85 83 83 -75
dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc MSPS ns ns ns ns ns ns ns ns Cycles ns ps rms
TBD TBD
TBD TBD
100 5 5 TBD TBD TBD TBD TBD TBD TBD TBD TBD
(20% to 80%) (20% to 80%)
F1 = 10 MHz, F2 = 12 MHz. Pipeline latency is exactly TBD cycles.
Rev. PrA | Page 4 of 8
Preliminary Technical Data PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AGND 1 3.3V 3 3.3V 5 AGND 7 5.0V 9
2 4 6
AD10680
AGND AIN AGND AGND
NC 1 NC 3 DGND 5 DCO 7 DCO 9 DOUT15 (MSB) 11 DOUT15 (MSB) 13 DOUT13 15
06188-002
2 4 6 8
NC NC 1.2VD 1.2VD
DOUT7 1 DOUT7 3 DOUT5 5 DOUT5 7 DOUT3 9 DOUT3 11 DOUT1 13 DOUT1 15 OR 19 3.3VD 21 RESET 23 NC 25
06188-003
2 4 6 8
DOUT6 DOUT6 DOUT4 DOUT4
10 AGND TOP VIEW 5.0V 11 (Not to Scale) 12 AGND AGND 13 14 AGND
AD10680
8
10 1.2VD 12 DOUT14
10 DOUT2 12 DOUT2 14 DOUT0 (LSB)
AD10680
14 DOUT14
AD10680
ENCODE 15 ENCODE 17 AGND 19
16 18 20
AGND AGND AGND
16 DOUT12 TOP VIEW DOUT13 17 (Not to Scale) 18 DOUT12
16 DOUT0 (LSB) TOP VIEW OR 17 (Not to Scale) 18 DGND 20 DGND 22 2.5VD 24 2.5VD 26 NC
06188-004
DOUT11 19 DOUT11 21 DOUT9 23 DOUT9 25 NC 27 NC 29
20 DOUT10 22 DOUT10 24 DOUT8 26 DOUT8 28 DGND 30 DGND
Figure 2. Pin Configuration P1
NC 27 NC 29
28 NC 30 NC
NC = NO CONNECT
Figure 4. Pin Configuration P3
Figure 3. Pin Configuration P2
Table 3. Pin Function Descriptions
P1 Pin No. 1 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 3, 5 9, 11 1, 2, 6, 7, 8, 10, 12, 13, 14, 16, 18, 19, 20 4 15 17
1 2
P2 Pin No. 2 5, 28, 30 11 to 26 N/A N/A N/A 6, 8, 10 N/A N/A 1 to 4, 27, 29 7 9 N/A N/A N/A N/A N/A N/A
P3 Pin No. 3 18, 20 1 to 16 17 19 23 N/A 22, 24 21 25 to 30 N/A N/A N/A N/A N/A N/A N/A N/A
Mnemonic DGND DOUTx, DOUTx OR OR RESET 1.2VD 2.5VD 3.3VD NC DCO DCO 3.3V 5.0V AGND AIN ENCODE ENCODE
Description Digital Ground Data Bit Output, Complement Overrange Overrange, Complement Reset Digital Voltage Digital Voltage Digital Voltage (VDD) No Connection Data Clock Output Data Clock Output, Complement Encode Voltage (EVCC) Analog Voltage (AVCC) Analog Ground Analog Input ENCODE Input ENCODE Input, Complement
Equivalent pin configuration is J1. Equivalent pin configuration is J2. 3 Equivalent pin configuration is J3.
Rev. PrA | Page 5 of 8
AD10680 THEORY OF OPERATION
The AD10680 uses two, high speed 16 bit ADCs with an interleaved-averaging algorithm to improve the SNR. The AD10680 is optimized for a 40 MHz bandwidth centered in the first Nyquist zone. The AD10680 provides a single-ended, analog input pin with a full-scale input range of 2.2 V p-p. The analog input is designed for 50 input impedance. The AD10680's differential ENCODE inputs are ac-coupled and internally supplied to the two16 bit ADCs. The digital outputs from the two ADCs are applied to the field-programmable gate array (FPGA) for postprocessing. The result is a 16-bit parallel LVDS word coded as twos complement.
Preliminary Technical Data
The 3.3 V digital supply provides power to the digital output section of the ADCs. The 1.2 V and 2.5 V digital supplies provide power for the FPGA. The digital supplies should be decoupled to digital ground (DGND). The 5.0 V and 3.3 V analog supplies provide power to the analog sections of the ADCs. Decoupling capacitors are strategically placed throughout the circuit to provide low impedance noise shunts to ground. The analog supplies should be decoupled to analog ground (AGND).
ANALOG AND DIGITAL GROUNDING
Although the AD10680 provides separate analog and digital ground pins, the device should be treated as an analog component. Proper grounding is essential in high speed, high resolution systems. Multilayer printed circuit boards (PCBs) are recommended to provide optimal grounding and power distribution. The use of power and ground planes provides distinct advantages. Power and ground planes minimize the loop area encompassed by a signal and its return path, minimize the impedance associated with power and ground paths, and provide a distributed capacitor formed by the power plane, printed circuit board material, and ground plane. The AD10680 unit has five metal standoffs used to fasten the AD10680 to the customer's PCB. The AD10680 pin connections mate to a connector (FSI-115-06-L-D-AD-TR for J2 and J3 and FSI-110-06-L-D-AD-TR for J1).
INPUT STAGE
The user is provided with a single-to-differential, transformercoupled input. The input impedance is 50 and requires a 2.2 V p-p input level to achieve full scale.
ENCODING THE AD10680
The AD10680's differential ENCODE signal must be a high quality, low phase noise source to prevent performance degradation. The clock input must be treated as an analog input signal because aperture jitter can affect dynamic performance. For optimum performance, the AD10680 must be clocked differentially.
ANALOG AND DIGITAL POWER SUPPLIES
Care must be taken when selecting a power source. Linear supplies are recommended. Switching supplies tend to have radiated components that can be coupled into the ADCs. The AD10680 features separate analog and digital supply and ground currents, helping to minimize digital corruption of sensitive analog signals.
Rev. PrA | Page 6 of 8
Preliminary Technical Data NOTES
AD10680
Rev. PrA | Page 7 of 8
AD10680 NOTES
Preliminary Technical Data
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06188-0-6/06(PrA)
Rev. PrA | Page 8 of 8

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