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| SSM07N70CP,R-A N-channel Enhancement-mode Power MOSFET Dynamic dv/dt rating Repetitive Avalanche Rated Fast Switching Simple Drive Requirement G S D BVDSS R DS(ON) I D 675V 1.2 7A DESCRIPTION The SSM07N70C series is specially designed as a main switching device for universal 90~265VAC off-line AC/DC converter applications. Both TO-220 and TO-262 type provide high blocking voltage to overcome voltage surge and sag in the toughest power system with the best combination of fast switching,ruggedized design and cost-effectiveness. G D S TO-220 (P) The TO-220 and TO-262 packages are widely preferred for all commercial and industrial applications. The device is well suited for switch-mode power supplies, AC-DC converters and high-current high-speed switching circuits. G D ABSOLUTE MAXIMUM RATINGS Symbol VDS VGS ID @ TC=25C ID @ TC=100C IDM PD @ TC=25C EAS IAR EAR TSTG TJ Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current 1 S TO-262 (R) Units V V A A A W W/C mJ A mJ C C Rating 675 30 7 4.4 18 89 0.7 2 Total Power Dissipation Linear Derating Factor Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Storage Temperature Range Operating Junction Temperature Range 140 7 7 -55 to 150 -55 to 150 THERMAL DATA Symbol Rthj-c Rthj-a Parameter Thermal Resistance Junction-case Thermal Resistance Junction-ambient Max. Max. Value 1.4 62 Unit C/W C/W 3/21/2005 Rev.2.01 www.SiliconStandard.com 1 of 6 SSM07N70CP,R-A Electrical Characteristics@Tj=25oC(unless otherwise specified) Symbol BVDSS Parameter Drain-Source Breakdown Voltage Test Conditions VGS=0V, ID=1mA Min. 675 2 Typ. 0.6 4.5 32 8.6 9 17 15 35 18 2075 120 8 Max. Units 1.2 4 10 100 100 V V/C V S uA uA nA nC nC nC ns ns ns ns pF pF pF BV DSS/Tj RDS(ON) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Breakdown Voltage Temperature Coefficient Reference to 25C, ID=1mA Static Drain-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (Tj=25 C) Drain-Source Leakage Current (Tj=150 C) o o VGS=10V, ID=3.5A VDS=VGS, ID=250uA VDS=10V, ID=3.5A VDS=675V, VGS=0V VDS=480V, VGS=0V VGS= 30V ID=7A VDS=480V VGS=10V VDD=300V ID=7A RG=10, VGS=10V RD=43 VGS=0V VDS=25V f=1.0MHz Gate-Source Leakage Total Gate Charge 3 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 3 Source-Drain Diode Symbol IS ISM VSD Notes: 1.Pulse width limited by safe operating area. 2.Starting Tj=25oC , VDD=50V , L=5mH , RG=25 , IAS=7A. 3.Pulse width <300us , duty cycle <2%. Parameter Continuous Source Current ( Body Diode ) Test Conditions VD=VG=0V , VS=1.5V 1 Min. - Typ. - Max. Units 7 18 1.5 A A V Pulsed Source Current ( Body Diode ) Forward On Voltage 3 Tj=25C, IS=7A, VGS=0V 3/21/2005 Rev.2.01 www.SiliconStandard.com 2 of 6 SSM07N70CP,R-A 12 T C =25 o C 10 V G =10V V G =6.0V ID , Drain Current (A) V G =5.5V 8 T C =150 o C V G =10V V G =6.0V ID , Drain Current (A) 8 6 V G =5.5V V G =5.0V 6 V G =5.0V 4 4 2 2 V G =4.0V V G =4.0V 0 0 5 10 15 20 25 0 0 10 20 30 40 V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 1.2 3 I D =3.5A 2.5 1.1 V G =10V Normalized BVDSS (V) Normalized R DS(ON) -50 0 50 100 150 2 1 1.5 1 0.9 0.5 0.8 0 -50 0 50 100 150 T j , Junction Temperature ( o C) T j , Junction Temperature ( o C) Fig 3. Normalized BVDSS vs. Junction Temperature Fig 4. Normalized On-Resistance vs. Junction Temperature 3/21/2005 Rev.2.01 www.SiliconStandard.com 3 of 6 SSM07N70CP,R-A 8 100 7 80 6 ID , Drain Current (A) 5 60 4 PD (W) 40 20 0 3 2 1 0 25 50 75 100 125 150 0 50 100 150 T c , Case Temperature ( C) o Tc , Case Temperature( C) o Fig 5. Maximum Drain Current vs. Case Temperature Fig 6. Typical Power Dissipation 100 1 Normalized Thermal Response (R thjc) DUTY=0.5 0.2 10 ID (A) 10us 100us 1 0.1 0.1 0.05 PDM 0.02 0.01 SINGLE PULSE t T 1ms T c =25 C Single Pluse o 10ms 100ms Duty factor = t/T Peak Tj = P DM x Rthjc + TC 0 1 10 100 1000 10000 0.01 0.00001 0.0001 0.001 0.01 0.1 1 10 V DS (V) t , Pulse Width (s) Fig 7. Maximum Safe Operating Area Fig 8. Effective Transient Thermal Impedance 3/21/2005 Rev.2.01 www.SiliconStandard.com 4 of 6 SSM07N70CP,R-A 16 10000 f=1.0MHz 14 I D =7A V DS =320V V DS =400V Ciss VGS , Gate to Source Voltage (V) 12 10 V DS =480V 8 C (pF) Coss 100 6 4 Crss 2 0 0 5 10 15 20 25 30 35 40 45 50 1 1 5 9 13 17 21 25 29 Q G , Total Gate Charge (nC) V DS (V) Fig 9. Gate Charge Characteristics Fig 10. Typical Capacitance Characteristics 100 5 4 10 T j = 150 o C IS (A) 1 T j = 25 o C VGS(th) (V) 3 2 0.1 1 0.01 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 0 -50 0 50 100 150 V SD (V) T j , Junction Temperature ( o C) Fig 11. Forward Characteristic of Reverse Diode Fig 12. Gate Threshold Voltage vs. Junction Temperature 3/21/2005 Rev.2.01 www.SiliconStandard.com 5 of 6 SSM07N70CP,R-A VDS 90% RD D VDS TO THE OSCILLOSCOPE 0.5x RATED VDS RG G + 10 V - S VGS 10% VGS td(on) tr td(off) tf Fig 13. Switching Time Circuit Fig 14. Switching Time Waveform VG VDS TO THE OSCILLOSCOPE QG 10V D G S + 0.8 x RATED VDS QGS QGD VGS 1~ 3 mA IG ID Charge Q Fig 15. Gate Charge Circuit Fig 16. Gate Charge Waveform Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 3/21/2005 Rev.2.01 www.SiliconStandard.com 6 of 6 |
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