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| Ordering number : EN*4909A CMOS LSI LC8220 JPEG Still Color Image Compression/Decompression LSI Preliminaly Overview The LC8220 JPEG LSI implements digital still image compression and decompression conforming to the JPEG (Joint Photographic Expert Group) standard. The LC8220 includes the baseline system of the ISO 10918 (JPEG) standard, and requires no external components to construct an application that performs JPEG compliant compression/decompression. Package Dimensions unit: mm 3153A-QFP160 [LC8220] Features * Conforms to the ISO 10918-1 baseline system * Four quantization tables and four Huffman tables (two for AC and two for DC) are built in. * Hardware support for JPEG marker codes * Built-in bidirectional YUV - RGB converter * Many color component sampling ratios are supported. (e.g., YUV 4:1:1 and YMCK 1:1:1:1, etc.) * Level shift function that can be defined for each component * Built-in dual buffers for reduced data transfer load * Bus sizing function that allows direct connection to 8-, 16-, and 32-bit busses * Endian control function * Three independent data buses SANYO: QFP160 SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 32896HA (OT)/D1694TH (OT) No. 4909-1/13 LC8220 Block Diagram The LC8220 has three independent buses. Pin Assignment No. 4909-2/13 LC8220 Pin Functions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 VSS CTLCS CTLRD CTLWR CTLRDY CTLERR CTLINT CPUCTL CTLSIZE VDD VSS CTLA7 CTLA6 CTLA5 CTLA4 CTLA3 CTLA2 CTLA1 CTLA0 VDD VSS CTLD15 CTLD14 CTLD13 CTLD12 CTLD11 CTLD10 CTLD9 CTLD8 VDD VSS CTLD7 CTLD6 CTLD5 CTLD4 CTLD3 CTLD2 CTLD1 CTLD0 VDD VSS CLK CLKSEL RESET TEST TESTOUT MDD10 MDD9 MDD8 VDD VSS MDD7 MDD6 MDD5 Symbol I/O -- I I I O O O I I -- -- I I I I I I I I -- -- I/O I/O I/O I/O I/O I/O I/O I/O -- -- I/O I/O I/O I/O I/O I/O I/O I/O -- -- I I I I O I/O I/O I/O -- -- I/O I/O I/O Test mode data bus*7 +5 V power supply Ground Test mode data bus*7 +5 V power supply Ground System clock Clock divisor selection (0: no divisor, 1: divisor used)*6 System reset Test mode selection (0: normal operation, 1: test mode)*6 Test result output*8 Control data bus +5 V power supply Ground Control data bus (D15 to D8 are unused if an 8-bit CPU is used.*7) +5 V power supply Ground Control address bus Ground Control bus chip select*2 Control bus read request*3 Control bus write request*4 Control bus ready for read/write requests*5 Error interrupt request Control bus interrupt request Connected CPU type setting for the control bus*1 Bus width selection for the control bus (0: 8 bits, 1: 16 bits) +5 V power supply Ground Function Continued on next page. No. 4909-3/13 LC8220 Continued from preceding page. Pin No. 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 Symbol MDD4 MDD3 MDD2 MDD1 MDD0 VDD VSS TESTI1 TESTI2 TESTI3 TESTI4 TESTI5 TESTO1 TESTO2 TESTI6 TESTO3 CPUPX PXCS PXRD PXWR PXRDY PXINT PXRLS PXEND (NC) VDD VSS PXD31 PXD30 PXD29 PXD28 PXD27 PXD26 PXD25 PXD24 VDD VSS PXD23 PXD22 PXD21 PXD20 PXD19 PXD18 PXD17 PXD16 VDD VSS PXD15 PXD14 PXD13 PXD12 PXD11 PXD10 PXD9 PXD8 I/O I/O I/O I/O I/O I/O -- -- I I I I I O O I O I I I I O O I O -- -- -- I/O I/O I/O I/O I/O I/O I/O I/O -- -- I/O I/O I/O I/O I/O I/O I/O I/O -- -- I/O I/O I/O I/O I/O I/O I/O I/O Pixel data bus (D31 to D16 are unused if a 16-bit CPU is used and D31 to D8 are unused if an 8-bit CPU is used.*7) +5 V power supply Ground Pixel data bus (D31 to D16 are unused if a 16-bit CPU is used and D31 to D8 are unused if an 8-bit CPU is used.*7) +5 V power supply Ground Pixel data bus (D31 to D16 are unused if a 16-bit CPU is used and D31 to D8 are unused if an 8-bit CPU is used.*7) +5 V power supply Ground Test mode output pins*8 Test mode input pin*9 Test mode output pin*8 Connected CPU type setting for the pixel bus*1 Pixel bus chip select*2 Pixel bus read request*3 Pixel bus write request*4 Pixel bus ready for read/write requests*5 Pixel bus interrupt request Pixel bus interrupt release Pixel bus last data output indicator Test mode input pins*9 +5 V power supply Ground Test mode data bus*7 Function Continued on next page. No. 4909-4/13 LC8220 Continued from preceding page. Pin No. 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Symbol VDD VSS PXD7 PXD6 PXD5 PXD4 PXD3 PXD2 PXD1 PXD0 VDD VSS PXSIZE0 PXSIZE1 (NC) CDCS CDRD CDWR CDRDY CDINT CDRLS CDEND CDFLSH (NC) (NC) (NC) (NC) (NC) CPUCD CDSIZE VDD VSS CDD15 CDD14 CDD13 CDD12 CDD11 CDD10 CDD9 CDD8 VDD VSS CDD7 CDD6 CDD5 CDD4 CDD3 CDD2 CDD1 CDD0 VDD I/O -- -- I/O I/O I/O I/O I/O I/O I/O I/O -- -- I I -- I I I O O I O I -- -- -- -- -- I I -- -- I/O I/O I/O I/O I/O I/O I/O I/O -- -- I/O I/O I/O I/O I/O I/O I/O I/O -- +5 V power supply Z**CS2 8086 family CPU (CPU = 1) 68000 family CPU (CPU = 0) CS AS Z**RD3 RD R/W Z**WR4 Z**RDY5 WR DS RDY ACK Code data bus +5 V power supply Ground Code data bus (D15 to D8 are unused if an 8-bit CPU is used.*7) Connected CPU type setting for the code bus*1 Bus width setting for the code bus (0: 8 bits, 1: 16 bits) +5 V power supply Ground Code bus chip select*2 Code bus read request*3 Code bus write request*4 Code bus ready for read/write requests*5 Code bus interrupt request Code bus interrupt release Code bus last data output Code bus forcible buffer flush +5 V power supply Ground Bus width selection for the pixel bus (PXSIZE [1,0] = 00: 8 bits, 01: 16 bits, 1*: 32 bits) Pixel data bus +5 V power supply Ground Function Note 1, 2, 3, 4, 5: 6: 7: 8: 9: These items are related to the CPU type. Connect to VSS (ground). Must be pulled up. These are NC pins. Connect to VDD. No. 4909-5/13 LC8220 Specifications Absolute Maximum Ratings at Ta = 25C, GND = 0 V Parameter Maximum supply voltage I/O voltages Operating temperature Storage temperature Soldering temperature Symbol VDD max VI, VO Topr Tstg Hand soldering: 3 seconds Reflow soldering: 10 seconds Conditions Ratings -0.3 to +7.0 -0.3 to VDD + 0.3 -30 to +70 -55 to +125 350 235 Unit V V C C C C Allowable Operating Ranges at Ta = -30 to +70C, GND = 0 V Parameter Supply voltage Input voltage Symbol VDD VIN Conditions min 4.5 0 typ max 5.5 VDD Unit V V DC Characteristics at Ta = -30 to +70C, VDD = 4.5 to 5.5 V, GND = 0 V Parameter Input high level voltage Symbol VIH Conditions TTL compatible: CTLCS, CTLRD, CTLWR, CPUCTL, CTLSIZE, CTLA7 to CTLA0, CLKSEL, RESET, TEST, CTLD15 to CTLD0 TTL compatible: CPUPX, PXCS, PXRD, PXWR, PXD31 to PXD0, PXRLS, PXSIZE0 PXSIZE1, CDCS, CDRD, CDWR, CDRLS, CDFLSH, CPUCD, CDSIZE, CDD15 to CDD0 IOH = -3 mA, TTL compatible: CTLRDY, CTLERR, CTLINT, TESTOUT, CTLD15 to CTLD0, PXRDY, PXINT, PXEND, PXD31 to PXD0, CDRDY, CDINT, CDEND, CDD15 to CDD0 IOH = -3 mA, TTL compatible: CTLRDY, CTLERR, CTLINT, TESTOUT, CTLD15 to CTLD0, PXRDY, PXINT, PXEND, PXD31 to PXD0, CDRDY, CDINT, CDEND, CDD15 to CDD0 For high impedance outputs: CTLD15 to CTLD0, PXD31 to PXD0, CDD15 to CDD0 CLK VDD = 5.0 V 145 -10 -10 min 2.2 typ max Unit V Input low level voltage Input leakage current VIL IL 0.8 +10 V A Output high level voltage VOH VDD - 2.1 V Output low level voltage VOL 0.4 V Output leakage current Oscillator frequency Current drain IOZ fOSC IDD +10 16.67 A MHz mA No. 4909-6/13 LC8220 AC Characteristics Code Bus Interface Timing Code Bus Read Cycle Code Bus Read Cycle (type 1) Code Bus Read Cycle (type 2) Item t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 T Read signal assert setup time (referenced to CLK) Read signal assert hold time (referenced to CLK) Chip select stabilization time (referenced to the read signal) Chip select hold time (referenced to the read signal) Ready signal response delay time (referenced to the read signal) Ready signal release delay time (referenced to the read signal) Read signal negate setup time (referenced to CLK) Read signal negate hold time (referenced to CLK) Data output delay time (referenced to the ready signal) Data output hold time (referenced to the read signal) Clock period Minimum 8 15 0 0 Maximum Unit ns ns ns ns T + t1 + 20 t7 + 27 8 15 15 t7 + 15 60 ns ns ns ns ns ns ns No. 4909-7/13 LC8220 Code Bus Write Cycle Code Bus Write Cycle (type 1) Code Bus Write Cycle (type 2) Item t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 T Write signal assert setup time (referenced to CLK) Write signal assert hold time (referenced to CLK) Chip select stabilization time (referenced to the write signal) Chip select hold time (referenced to the write signal) Write cycle selection signal stabilization time (referenced to the write signal) Write cycle selection signal hold time (referenced to the write signal) Ready signal response delay time (referenced to the write signal) Ready signal release delay time (referenced to the write signal) Write signal negate setup time (referenced to CLK) Write signal negate hold time (referenced to CLK) Data setup time (referenced to the ready signal) Data hold time (referenced to the ready signal) Clock period Minimum 8 15 0 0 0 0 Maximum Unit ns ns ns ns ns ns T + t1 + 20 t9 + 27 8 15 45 15 60 ns ns ns ns ns ns ns No. 4909-8/13 LC8220 Pixel Bus Interface Timing Pixel Bus Read Cycle Pixel Bus Read Cycle (type 1) Pixel Bus Read Cycle (type 2) Item t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 T Read signal assert setup time (referenced to CLK) Read signal assert hold time (referenced to CLK) Chip select stabilization time (referenced to the read signal) Chip select hold time (referenced to the read signal) Ready signal response delay time (referenced to the read signal) Ready signal release delay time (referenced to the read signal) Read signal negate setup time (referenced to CLK) Read signal negate hold time (referenced to CLK) Data output delay time (referenced to the ready signal) Data output hold time (referenced to the read signal) Clock period Minimum 8 15 5 5 Maximum Unit ns ns ns ns T + t1 + 20 t7 + 28 8 15 15 t7 + 18 60 ns ns ns ns ns ns ns No. 4909-9/13 LC8220 Pixel Bus Write Cycle Pixel Bus Write Cycle (type 1) Pixel Bus Write Cycle (type 2) Item t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 T Write signal assert setup time (referenced to CLK) Write signal assert hold time (referenced to CLK) Chip select stabilization time (referenced to the write signal) Chip select hold time (referenced to the write signal) Write cycle selection signal stabilization time (referenced to the write signal) Write cycle selection signal hold time (referenced to the write signal) Ready signal response delay time (referenced to the write signal) Ready signal release delay time (referenced to the write signal) Write signal negate setup time (referenced to CLK) Write signal negate hold time (referenced to CLK) Data setup time (referenced to the ready signal) Data hold time (referenced to the ready signal) Clock period Minimum 8 15 5 5 5 5 Maximum Unit ns ns ns ns ns ns T + t1 + 20 t9 + 28 8 15 60 20 60 ns ns ns ns ns ns ns No. 4909-10/13 LC8220 Control Bus Interface Timing Control Bus Read Cycle Control Bus Register Read Cycle (type 1) Control Bus Register Read Cycle (type 2) Item t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 T Read signal assert setup time (referenced to CLK) Read signal assert hold time (referenced to CLK) Chip select stabilization time (referenced to the read signal) Chip select hold time (referenced to the read signal) Address stabilization time (referenced to the read signal) Address hold time (referenced to the read signal) Ready signal response delay time (referenced to the read signal) Ready signal release delay time (referenced to the read signal) Read signal negate setup time (referenced to CLK) Read signal negate hold time (referenced to CLK) Data output delay time (referenced to the ready signal) Data output hold time (referenced to the read signal) Clock period Minimum 10 15 10 15 0 5 Maximum Unit ns ns ns ns ns ns T + t1 + 24 t9 + 30 12 15 0 t9 + 30 60 ns ns ns ns ns ns ns No. 4909-11/13 LC8220 Control Bus Write Cycle Control Bus Register Write Cycle (type 1) Control Bus Register Write Cycle (type 2) Item t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 T Write signal assert setup time (referenced to CLK) Write signal assert hold time (referenced to CLK) Chip select stabilization time (referenced to the write signal) Chip select hold time (referenced to the write signal) Write cycle selection signal stabilization time (referenced to the write signal) Write cycle selection signal hold time (referenced to the write signal) Address stabilization time (referenced to the write signal) Address hold time (referenced to the write signal) Ready signal response delay time (referenced to the write signal) Ready signal release delay time (referenced to the write signal) Write signal negate setup time (referenced to CLK) Write signal negate hold time (referenced to CLK) Data setup time (referenced to the ready signal) Data hold time (referenced to the ready signal) Clock period Minimum 12 15 10 15 10 10 0 5 Maximum Unit ns ns ns ns ns ns ns ns T + t1 + 24 t11 + 32 5 15 60 20 60 ns ns ns ns ns ns ns No. 4909-12/13 LC8220 Hardware Reset Timing Hardware Reset Timing Item t1 t2 T Reset signal pulse width LSI access disabled time Clock period Minimum 2T 5T 60 Maximum Unit ns ns ns s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 1997. Specifications and information herein are subject to change without notice. No. 4909-13/13 |
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