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CS3302 High-Z Programmable Gain Differential Amplifier
Features
Signal bandwidth: DC to 2 kHz Selectable gain: x1, x2, x4, x8, x16, x32, x64 Differential inputs, differential outputs
* * * * Multiplexed inputs: INA, INB, 800 termination Rough / fine charge outputs for CS5371/72 Max signal amplitude: 5 Vp-p differential Ultra-low input bias: < 1 pA
Description
The CS3302 is a high input impedance differential in, differential out amplifier with programmable gain, optimized for amplifying signals from high impedance sensors such as hydrophones. The gain settings are binary weighted (x1, x2, x4, x8, x16, x32, x64) and are selected using simple pin settings. Two sets of external inputs, INA and INB, simplify system design as inputs from a sensor and test DAC. An internal 800 termination can also be selected for noise tests. Amplifier input impedance is very high, requiring less than 1 pA of input current. Noise performance is very good at 1 Vp-p between 0.1 Hz and 10 Hz, and a noise density of 8.5 nV/ Hz over the 200 Hz to 2 kHz bandwidth. Distortion performance is also extremely good, typically -118 dB THD. Low input current, low noise, and low total harmonic distortion make this amplifier ideal for high impedance differential sensors requiring maximum dynamic range. ORDERING INFORMATION -40C to +85C 24-pin SSOP
Excellent noise performance
* 1 Vp-p between 0.1 Hz and 10 Hz * 8.5 nV/ Hz from 200 Hz to 2 kHz
Low total harmonic distortion
* -118 dB THD typical (0.000126%) * -112 dB THD maximum (0.000251%)
Low power consumption
* Normal / LPWR / PWDN: 5 mA, 3.3 mA, 10 A
Single or dual power supply configurations
* VA+ = +5 V; VA- = 0 V; VD = +3.3 V to +5 V CS3302-IS * VA+ = +2.5 V;VA- = -2.5 V;VD = +3.3 V
VA+ INA+ INB+
400
GUARD
VD
750 500
+ -
OUTR+ OUTF+
750 500
MUX0 MUX1
400
GAIN0 GAIN1 GAIN2
500 750 +
750 500
INAINBVA-
OUTFOUTR-
LPWR
PWDN
DGND
Preliminary Product Information
Cirrus Logic, Inc. www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
JUN `03 DS596PP2 1
CS3302
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS........................................................................ 4 SPECIFIED OPERATING CONDITIONS ................................................................................ 4 ABSOLUTE MAXIMUM RATINGS .......................................................................................... 4 THERMAL CHARACTERISTICS ............................................................................................. 5 ANALOG CHARACTERISTICS ............................................................................................... 5 DIGITAL CHARACTERISTICS ................................................................................................ 8 POWER SUPPLY CHARACTERISTICS ................................................................................. 9 2. GENERAL DESCRIPTION..................................................................................................... 10 2.1. Analog Signals .............................................................................................................. 10 2.2.1.Analog Inputs ....................................................................................................... 10 2.3.2.Analog Outputs..................................................................................................... 10 2.4.3.Differential Signals ............................................................................................... 11 2.5.4.Guard Output........................................................................................................ 11 2.6. Digital Signals................................................................................................................ 11 2.7.1.Gain Selection ...................................................................................................... 11 2.8.2.Mux Selection ....................................................................................................... 11 2.9.3.Low Power Selection ............................................................................................ 11 2.10.4.Power Down Selection ....................................................................................... 11 2.11. Power Supplies ............................................................................................................. 11 2.12.1.Analog Power Supplies ...................................................................................... 11 2.13.2.Digital Power Supplies ....................................................................................... 12 2.14. Connection Diagram...................................................................................................... 13 3. PIN DESCRIPTION ................................................................................................................ 14 4. PACKAGE DIMENSIONS ...................................................................................................... 15
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.com
IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade Law and is to be exported or taken out of the PRC. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
2
CS3302
LIST OF FIGURES
Figure 1. CS3302 Noise Performance ............................................................................................ 5 Figure 2. Digital Input Rise and Fall Times ..................................................................................... 8 Figure 3. System Architecture....................................................................................................... 10 Figure 4. CS3302 Amplifier Connections ...................................................................................... 13 Figure 5. CS3302 Pin Assignments .............................................................................................. 14
LIST OF TABLES
Table 1. Digital Selection for Gain and Input Mux Control ............................................................. 8 Table 2. Pin Descriptions ............................................................................................................. 14
3
CS3302
1.
* * *
CHARACTERISTICS AND SPECIFICATIONS
Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25C.
DGND = 0 V, all voltages with respect to 0 V.
SPECIFIED OPERATING CONDITIONS
Parameter Unipolar Power Supplies Positive Analog Negative Analog Positive Digital Bipolar Power Supplies Positive Analog Negative Analog Positive Digital Thermal Ambient Operating Temperature Industrial (-IS) TA -40 85 C (Note 1) (Note 2) VA+ VAVD 2.375 -2.625 3.135 2.5 -2.5 3.3 2.625 -2.375 3.465 V V V (Note 1) (Note 2) VA+ VAVD 4.75 -0.25 3.135 5.0 0 3.3 5.25 0.25 5.25 V V V Symbol Min Nom Max Unit
Notes: 1. VA- must be the most negative voltage to avoid potential SCR latch-up conditions. 2. VD must conform to Digital Supply Differential under Absolute Maximum Ratings.
ABSOLUTE MAXIMUM RATINGS
CS3302 Parameter DC Power Supplies Positive Analog Negative Analog Digital [(VA+) - (VA-)] [(VD) - (VA-)] (Note 3) (Note 3) (Note 3) Symbol VA+ VAVD VADIFF VDDIFF IIN IIN IOUT PDN VINA VIND TA TSTG Min -0.3 -6.8 -0.3 (VA-)-0.3 -0.3 -40 -65 Max 6.8 0.3 6.8 6.8 6.8 +10 +50 +25 500 (VA+)+0.3 (VD)+0.3 85 150 Unit V V V V V mA mA mA mW V V C C
Analog Supply Differential Digital Supply Differential Input Current, Power Supplies Output Current Power Dissipation Analog Input Voltages Digital Input Voltages
Input Current, Any Pin Except Supplies
Ambient Operating Temperature (Power Applied) Storage Temperature Range
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 3. Transient currents up to 100mA will not cause SCR latch-up.
4
CS3302
THERMAL CHARACTERISTICS
CS3302 Parameter Allowable Junction Temperature Junction to Ambient Thermal Impedance Ambient Operating Temperature (Power Applied) JA TA Symbol Min -
Typ 65 -
Max 135
-
Unit C C / W C
-40
+85
ANALOG CHARACTERISTICS
CS3302 Parameter Noise Performance, Normal Power Input Voltage Noise Input Voltage Noise Density Input Current Noise Density Noise Performance, Low Power (LPWR=1) Input Voltage Noise Input Voltage Noise Density Input Current Noise Density Distortion Performance, Normal Power Total Harmonic Distortion Linearity Total Harmonic Distortion Linearity (Note 5, 6) (Note 5, 6) (Note 5, 6) (Note 5, 6) THD LIN THD LIN -118
0.000126
Symbol f0 = 0.1 Hz to 10 Hz f0 = 200 Hz to 2 kHz (Note 4) f0 = 0.1 Hz to 10 Hz f0 = 200 Hz to 2 kHz (Note 4) VN PP VND IND VN PP VND IND
Min -
Typ 1 8.5 1 1 10 1
Max 1.5 12 1.5 15 -112
0.000251
Unit Vp-p
nV/ Hz fA/ Hz
Vp-p
nV/ Hz fA/ Hz
dB % dB %
Distortion Performance, Low Power (LPWR=1) -118
0.000126
-110
0.000316
Notes: 4. Guaranteed by design and/or characterization. 5. Tested with a full scale input signal of 31.25 Hz. 6. Noise in the harmonic bins dominates THD and linearity measurements for x16, x32, and x64 gains.
CS3302 In-Band Noise
20 Noise Density (nV/rtHz)
Noise Density (nV/rtHz) 300 250 200 150 100 50 0
CS3302 Wide Band Noise
15
10 5
0 0 200 400 600 800 1000 1200 1400 1600 1800 2000 Frequency (Hz)
0.1
1
10
100
1000
10000 100000 1E+06
Frequency (Hz)
Figure 1. CS3302 Noise Performance
5
CS3302
ANALOG CHARACTERISTICS (CONT.)
CS3302 Parameter Gain Gain, Differential Gain, Common Mode Gain Accuracy, Absolute Gain Accuracy, Relative Gain Drift Offset Offset Voltage, Input Referred Offset After Calibration, Absolute Offset Calibration Range Offset Voltage Drift (Note 9, 10) OFST +250 +1 100 1 +750 V V % F.S. V / C (Note 11) OFSTCAL (Note 12) OFSTRNG (Note 4) OFSTTC (Note 7, 9) (Note 8, 9) (Note 4) GAINDM GAINCM GAABS GAREL GAIN TC x1 x1 +1 +0.4 5 x64 +2 +0.8 % % ppm / C Symbol Min Typ Max Unit
Notes: 7. Absolute gain accuracy tests the matching of x1 gain across multiple CS3302 devices. 8. Relative gain accuracy tests the tracking of x2 - x64 gain relative to x1 gain on a single CS3302 device. 9. Specification is for the parameter over the specified temperature range and is for the CS3302 device only. It does not include the effects of external components. 10. Offset voltage is tested with the amplifier inputs connected to the internal 800 termination. 11. The absolute offset after calibration specification applies to the effective offset voltage of the CS3302 output when used with the CS5371/72 modulator and CS5376A digital filter, and is measured from the digitally calibrated output codes of the CS5376A. 12. The CS3302 offset calibration is performed digitally with the CS5371/72 modulator and CS5376A digital filter and includes the full scale signal range. Calibration offsets of greater than + 5% of full scale will begin to subtract from system dynamic range.
6
CS3302
ANALOG CHARACTERISTIC (Cont.)
CS3302 Parameter Analog Input Characteristics Input Signal Frequencies Input Voltage Range (Signal + Vcm) (Note 13) Full Scale Input, Differential x1 x2 - x64 x1 x2 x4 x8 x16 x32 x64 BW VIN VINFS DC
(VA-)+0.7 (VA-)+0.7
Symbol
Min
Typ 1, 20 0.5, 40 1 -130 100 750 Vcm 500 40 -
Max 2000
(VA+)-1.25 (VA+)-1.75
Unit Hz V Vp-p Vp-p Vp-p mVp-p mVp-p mVp-p mVp-p T, pF T, pF pA dB dB V Vp-p mA nF V A pF
90
(VA-)+0.5
5 2.5 1.25 625 312.5 156.25 78.125 40 (VA+)-0.5
Input Impedance, Differential Input Impedance, Common Mode Input Bias Current Crosstalk, Multiplexed Inputs Analog Output Characteristics Output Voltage Range (Signal + Vcm) Full Scale Output, Differential Output Impedance Output Current Load Capacitance Guard Output Characteristics Guard Output Voltage Guard Output Impedance Guard Output Current Guard Load Capacitance (Note 15) (Note 4) Common Mode to Differential Mode Rejection (Note 14)
ZINDIFF ZINCM IIN XT CDMR VOUT VOUTFS ZOUT IOUT CL VGUARD ZGOUT IG OUT CGL
-
5 3.33 100 100
Notes: 13. No signal sources operating from external supplies should be applied to pins of the device prior to its own supplies being established. Connecting any terminal to voltages greater than VA+ or less than VAmay cause destructive latch-up. 14. Common-to-differential mode rejection tested with a 50 Hz, 500 mVp-p common mode sine wave applied to the analog inputs. 15. Output impedance is primarily determined by the integrated anti-alias resistors. Value is approximate and can vary +/- 30% depending on process parameters.
7
CS3302
DIGITAL CHARACTERISTICS
CS3302 Parameter Digital Characteristics High Level Input Drive Voltage Low Level Input Drive Voltage Input Leakage Current Digital Input Capacitance Rise Times Fall Times (Note 16) (Note 16) VIH VIL IIN CIN tRISE tFALL 0.6*VD 0.0 +1 9 VD 0.8 +10 100 100 V V A pF ns ns Symbol Min Typ Max Unit
Notes: 16. Device is intended to be driven with CMOS logic levels.
t risein
t fallin (0.8*VD) (0.2*VD)
Figure 2. Digital Input Rise and Fall
Input Selection 800 termination INA only INB only INA + INB
MUX1 0 1 0 1
MUX0 0 0 1 1
Gain Selection x1 x2 x4 x8 x16 x32 x64 Reserved
GAIN2 0 0 0 0 1 1 1 1
GAIN1 0 0 1 1 0 0 1 1
GAIN0 0 1 0 1 0 1 0 1
Table 1. Digital Selection for Gain and Input Mux Control
8
CS3302
POWER SUPPLY CHARACTERISTICS
CS3302 Parameter Power Supply Current, Normal Mode Analog Power Supply Current Digital Power Supply Current Power Supply Current, Low Power Mode Analog Power Supply Current, LPWR = 1 Digital Power Supply Current, LPWR = 1 Power Supply Current, Power Down Mode Analog Power Supply Current, PWDN = 1 Digital Power Supply Current, PWDN = 1 Power Supply Rejection Power Supply Rejection Ratio (Note 18) PSRR 95 120 dB (Note 17) (Note 17) IA ID 9 2 11 8 A A (Note 17) (Note 17) IA ID 3.4 0.1 4.0 0.2 mA mA (Note 17) (Note 17) IA ID 5.0 0.1 5.75 0.2 mA mA Symbol Min Typ Max Unit
Notes: 17. All outputs unloaded. Analog inputs connected to the internal 800 termination. Digital inputs forced to VD or DGND respectively. 18. Power supply rejection tested with a 50 Hz, 400 mVp-p sine wave applied separately to each supply.
9
CS3302
2. GENERAL DESCRIPTION
2.1
2.1.1
The CS3302 is a high impedance low-noise CMOS differential input, differential output amplifier for precision analog signals between DC and 2 kHz. It has multiplexed inputs, rough/fine charge outputs, and programmable gains of x1, x2, x4, x8, x16, x32, and x64. The amplifier's performance makes it ideal for low-frequency, high dynamic range applications requiring low distortion and minimal power consumption. It's optimized for use in acquisition systems designed around the CS5371/72 single/dual modulators and the CS5376A quad digital filter. Figure 3 shows the system level architecture of a 4-channel acquisition system using four CS3302, two CS5372, and one CS5376A.
Analog Signals
Analog Inputs
The amplifier analog inputs are designed for high impedance differential sensors. Input multiplexing simplifies system connections by providing separate inputs for a sensor and test DAC (INA, INB) as well as an internal termination for noise tests. The MUX0, MUX1 digital pins determine which multiplexed input is connected to the amplifier.
2.1.2 Analog Outputs
The amplifier analog outputs are separated into rough charge / fine charge signals to easily connect to the CS5371/72 inputs. Each output also includes a series resistor, requiring only two differential capacitors to create the CS5371/72 input anti-alias filter.
Differential Sensor
CS3302
M U X
AMP
CS5371/72
CS89712
Modulator Differential Sensor
CS3302
EP7312
M U X
AMP
CS5376 CS5376A
Controller or Configuration EEPROM
Digital Filter Differential Sensor
CS3302 CS8900A CS5371/72
M U X
AMP
System Telemetry Modulator
Differential Sensor
CS3302
CS4373
M U X
AMP Test DAC
Figure 3. System Architecture
10
CS3302
2.1.3 Differential Signals
Analog signals into and out of the CS3302 are differential, consisting of two halves with equal but opposite magnitude varying about a common mode voltage. A full scale 5 Vpp differential signal centered on a 2.5 V common mode can have: SIG+ = 2.5 V + 1.25 V = 3.75 V SIG- = 2.5 V - 1.25 V = 1.25 V SIG+ is +2.5 V relative to SIGFor the reverse case: SIG+ = 2.5 V - 1.25 V = 1.25 V SIG- = 2.5 V + 1.25 V = 3.75 V SIG+ is -2.5 V relative to SIGThe total swing for SIG+ relative to SIG- is (+2.5 V) - (-2.5 V) = 5 Vpp. A similar calculation can be done for SIG- relative to SIG+. Note that a 5 Vpp differential signal centered on a 2.5 V common mode voltage never exceeds 3.75 V and never drops below 1.25 V on either half of the signal.
2.1.4 Guard Output
GAIN0, GAIN1, and GAIN2 pins as shown in Table 1 on page 8.
2.2.2 Mux Selection
The analog inputs to the amplifier are multiplexed, with external signals applied to the INA+, INA- or INB+, INB- pins. An internal termination is also available for noise tests. Input mux selection is made using the MUX0 and MUX1 pins as shown in Table 1 on page 8. Although a mux selection is provided to enable the INA and INB switches simultaneously, significant current should not be driven through them in this mode. The CS3302 mux switches will maintain good linearity only with minimal signal current.
2.2.3 Low Power Selection
For applications where power is critical, a lowpower mode can be selected. This mode reduces amplifier power consumption at the expense of slightly degraded performance. Low power mode is selected using the LPWR pin, which is active high.
2.2.4 Power Down Selection
The GUARD pin outputs the common mode voltage of the currently selected analog signal input. It can be used to drive the cable shield between a high impedance sensor and the amplifier inputs. Driving the cable shield with the analog signal common mode voltage minimizes leakage and improves signal integrity from high impedance sensors. The GUARD output is defined as the midpoint voltage between the + and - halves of the currently selected differential input signal, and will vary as the signal common mode varies. The GUARD output will not drive a significant load, it only provides a shielding voltage. 2.2
2.2.1
A power-down mode is available to shut down the amplifier when not in use. When enabled, all internal circuitry is disabled, the analog inputs and outputs go high-impedance, and the device enters a micro-power state. Power down mode is selected using the PWDN pin, which is active high. 2.3
2.3.1
Power Supplies
Analog Power Supplies
Digital Signals
Gain Selection
The CS3302 supports gain ranges of x1, x2, x4, x8, x16, x32, and x64. They are selected using the
The analog power pins of the CS3302 are to be supplied with a total of 5 V between VA+ and VA-. This voltage can be from a unipolar +5 V / 0 V supply or a bipolar +2.5 V / -2.5 V supply. When using a unipolar supply, analog signal common mode should be biased to 2.5 V, and when using bipolar supplies it should be biased to 0 V. The analog power supplies are recommended to be bypassed to system ground using 0.1 F X7R type capacitors.
11
CS3302
The VA- supply is connected to the CMOS substrate and as such must remain the most negative applied voltage to prevent potential latch-up conditions. Care should be taken to ensure analog input voltages do not drop more than -0.3 V below the VA- supply. Care should also be taken to establish the VA- supply before analog signals are applied to the device. It is recommended to clamp the VAsupply to system ground using a reverse biased Schottky diode to prevent possible latch-up conditions related to mismatched supply rail initialization.
2.3.2 Digital Power Supplies
The digital power supply across the VD and DGND pins is flexible and can be set to interface with 3.3 V or 5 V logic. The digital power supply should be bypassed to system ground using a 0.01 F X7R type capacitor.
12
CS3302
2.4 Connection Diagram Figure 4 shows a connection diagram for the CS3302 amplifier when used with the CS5372 dual modulator and CS5376A digital filter. The diagram shows differential sensors, a test DAC, and analog outputs with anti-alias capacitors; power supply connections including recommended bypassing; and digital control connections back to the CS5376A GPIO pins.
3 2
G PIO (x3) G PIO (x2) G PIO G PIO PWDN LPW R VD VA +
0 .1 F 0.0 1 F
To CS 5376 A D ig ital C on tro l
GA IN VA + VA +
0 .1 F
MUX
VD
0 .0 1F
VD C S3302 D ifferential Am p lifier
VA VA 0 .1 F
VA + D GN D IN A GU AR D IN B IN B + O UT R OU TF OU T F+ O UT R+ INR + INF +
0 .0 2F C 0G 0.0 2 F C0 G
VD M DA TA 1 M FL A G1 PW DN 1
IN A +
D ifferential Senso r
CS4373
INF INR V RE F+ 2.5 V R eference
M C LK M SYN C
Test DAC
C S5372 M o du lator V RE F-
D ifferential Senso r
0 .0 2F C 0G 0.0 2 F C0 G
INR INF INF + INR + IN A + IN A G U AR D IN B IN B + O UT R OU TF OU T F+ O UT R+ VD V A+ VD VA C S3302 D ifferential Am p lifier V AD GN D G A IN M UX PW D N LP W R G PIO G PIO G PIO (x2) G PIO (x3)
0.0 1 F
LP W R OF ST
M DA TA 2 M FL A G2 PW DN 2 D GN D
VA +
0 .1 F
V A0.1F
VA 0 .1 F
2 3
To CS 5376 A D ig ital C on tro l
Figure 4. CS3302 Amplifier Connections
13
CS3302
3. PIN DESCRIPTION
Positive Analog Power Supply Negative Analog Rough Output Negative Analog Fine Output Negative Analog Power Supply Non-Inverting Input A Inverting Input A Inverting Input B Non-Inverting Input B Test Mode Output Positive Analog Fine Output Positive Analog Rough Output Test Mode Select
VA+ OUTROUTFVAINA+ INAINBINB+ TESTOUT OUTF+ OUTR+ TEST0
1 2 3
4
24 23 22
21
MUX0 MUX1 GAIN0 GAIN1 GAIN2 PWDN LPWR TEST1 VD DGND TEST2 GUARD
Input Mux Select Input Mux Select Gain Range Select Gain Range Select Gain Range Select Power Down Mode Enable Low Power Mode Enable Test Mode Select Positive Digital Power Supply Digital Ground Test Mode Select Guard Voltage Output
5 6
7
20 19
18
8 9 10 11 12
17 16 15 14 13
Figure 5. CS3302 Pin Assignments
Pin Name VA+ VAVD DGND INA+, INAINB+, INBGUARD OUTR+, OUTROUTF+, OUTFGAIN0, GAIN1, GAIN2 LPWR PWDN MUX0, MUX1 TEST0 TEST1, TEST2 TESTOUT Pin # I/O Pin Description
1 4 16 15 5, 6 8, 7 13 11, 2 10, 3 22, 21, 20 18 19 24, 23 12 17, 14 9
I I I I I I O O O I I I I I I O
Positive analog supply voltage. Negative analog supply voltage. Positive digital supply voltage. Digital ground. Channel A differential analog inputs. Selected via MUX pins. Channel B differential analog inputs. Selected via MUX pins. Guard voltage output. Rough charge differential analog outputs. Fine charge differential analog outputs. Gain range select. See Gain Selection table in Digital Characteristics section. Low power mode enable. Active high. Power down mode enable. Active high. Analog input select. See Input Selection table in Digital Characteristics section. Test mode select, factory use only. Connect to VA- during normal operation. Test mode select, factory use only. Connect to DGND during normal operation. Test mode output, factory use only. Connect to VA- during normal operation. Table 2. Pin Descriptions
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CS3302
4. PACKAGE DIMENSIONS 24 PIN SSOP PACKAGE DRAWING
N
D
E11 A2 A1
L
E
A
e
b2 SIDE VIEW
END VIEW
SEATING PLANE
123
TOP VIEW
INCHES DIM A A1 A2 b D E E1 e L MIN -0.002 0.064 0.009 0.311 0.291 0.197 0.024 0.025 0 MAX 0.084 0.010 0.074 0.015 0.335 0.323 0.220 0.027 0.040 8
MILLIMETERS MIN MAX -0.05 1.62 0.22 7.90 7.40 5.00 0.61 0.63 0 2.13 0.25 1.88 0.38 8.50 8.20 5.60 0.69 1.03 8
NOTE
2,3 1 1
Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
15

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