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CY28381
High-Performance SiS645DX/648DX/650/651 Intel Pentium 4 Clock Synthesizer
Features
* * * * * * * Supports Pentium(R) 4-type CPUs 3.3V power supply Eight copies of PCI clocks One 48-MHz USB clock Two copies of ZCLK cocks One 48-MHz/24-MHz Programmable SIO clock Two differential CPU clock pairs * SMBus support with readback capabilities * Spread Spectrum electromagnetic interference (EMI) reduction * Dial-A-Frequency(R) features * Dial-A-RatioTM features * Dial-A-dBTM features * 48-pin SSOP Package * Watchdog function
Block Diagram
XIN XOUT PLL1 CPU_STP# IREF FS[0:4] MULT0 VTT_PWRGD PCI_STP# PLL2 Power on Latch
/2
Pin Configuration[1]
REF(0:2) CPUT[0:1] CPUC[0:1] SDCLK AGP[0:1] ZCLK[0:1] PCI[0:5] PCIF[0:1] 48M 48M_24M#
VDDR **FS0/REF0 **FS1/REF1 **FS2/REF2 VSSR XIN XOUT VSSZ ZCLK0 ZCLK1 VDDZ *SRESET#/PCI_STP# VDDP **FS3/PCIF0 **FS4/PCIF1 PCI0 PCI1 VSSP VDDP PCI2 PCI3 PCI4 PCI5 VSSP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
PD# SDATA SCLK
WD Logic I2C Logic
SRESET#
VDDSD SDCLK VSSSD CPU_STP#* CPUT1 CPUC1 VDDC VSSC CPUT0 CPUC0 IREF VSSA VDDA SCLK SDATA PD#/VTT_PWRGD* VSSAGP AGP0 AGP1 VDDAGP VDD48M 48M 24_48M/MULT0* VSS48M
48 pin SSOP
CY28381
Note: 1. Pins marked with [*] have internal 150K pull-up resistors. Pins marked with [**] have internal 150K pull-down resistors.
Cypress Semiconductor Corporation Document #: 38-07546 Rev. **
*
3901 North First Street
*
San Jose, CA 95134
* 408-943-2600 Revised May 20, 2003
CY28381
Pin Description[2]
Pin 6 7 40,44 39,43 XIN XOUT CPU[0:1] CPUC[0:1] VDDR VDDC VDDC VDDP VDDP Name PWR I/O I O O O O I/O PD I/O PD I/O PD I/O PD I/O PD I VDDAGP I PU Description Oscillator Buffer Input. Connect to a crystal or to an external clock. Oscillator Buffer Output. Connect to a crystal. Do not connect when an external clock is applied at XIN. "True" Host Output Clocks. See Table 1 for frequencies and functionality. "Complementary" Host Output Clocks. See Table 1 for frequencies and functionality. PCI Clock Outputs. See Table 1. Power-on Bidirectional Input/Output. At power-up, FS3 is the input. When VTT_PWRGD transitions to a logic high, FS3 state is latched and this pin becomes PCIF0 Clock Output. See Table 1. Power-on Bidirectional Input/Output. At power-up, FS4 is the input. When VTT_PWRGD transitions to a logic high, FS4 state is latched and this pin becomes PCIF1 Clock Output. See Table 1. Power-on Bidirectional Input/Output. At power-up, FS0 is the input. When VTT_PWRGD transitions to a logic high, FS0 state is latched and this pin becomes REF0, buffered Output copy of the device's XIN clock. Power-on Bidirectional Input/Output. At power-up, FS1 is the input. When VTT_PWRGD is transited to logic low, FS1 state is latched and this pin becomes REF1, buffered Output copy of the device's XIN clock. Power-on Bidirectional Input/Output. At power-up, FS2 is the input. When VTT_PWRGD is transited to logic low, FS2 state is latched and this pin becomes REF2, buffered Output copy of the device's XIN clock. Current Reference Programming Input for CPU Buffers. A resistor is connected between this pin and VSS. See Figure 9. Power-down Input/VTT Power Good Input. At power-up, VTT_PWRGD is the input. When this input is transitions initially from low to high, the FS (0:4) and MULT0 are latched. After the first low to high transition, this pin become a PD# input with an internal pull-up. When PD# is asserted low, the device enters power down mode. See power management function. Fixed 48MHz USB Clock Output. Power-on Bidirectional Input/Output. At power-up, MULT0 is the input. When VTT_PWRGD is transited to logic low, MULT0 state is latched and this pin becomes 24_48M, SIO programmable clock output. HyperZip Clock Outputs. See Table 1. Serial Data Input. Conforms to the SMBus specification of a Slave Receive/Transmit device. It is an input when receiving data. It is an open drain output when acknowledging or transmitting data. Serial Clock Input. Conforms to the SMBus specification. PCI Clock Disable Input. If Byte12 Bit7 = 0, this pin becomes an SRESET# open drain output, and the internal pulled up is not active. See system reset description. System Reset Control Output. If Byte12 Bit7 = 1 (Default), this pin becomes PCI Clock Disable Input. When PCI_STP# is asserted low, PCI (0:5) clocks are synchronously disabled in a low state. This pin does not affect PCIF (0:1) if they are programmed to be free-running clocks via the device's SMBus interface. CPU Clock Disable Input. When asserted low, CPU (0:1)T clocks are synchronously disabled in a high state and CPU (0:1)C clocks are synchronously disabled in a low state. SDRAM Clock Output. AGP Clock Outputs. See Table 1 for frequencies and functionality.
16,17,20,23 PCI [0:5] 14 FS3/PCIF0
15
FS4/PCIF1
VDDP
2
FS0/REF0
VDDR
3
FS1/REF1
VDDR
4
FS2/REF2
VDDR
38 33
IREF PD#/ VTT_PRGD
27 26
48M 24_48M/ MULT0 ZCLK (0:1) SDATA
VDD48M VDD48M
O I/O PU O I/O
9,10 34
VDDZ VDDAGP
35 12
SCLK SRESET#
VDDAGP VDDZ
I O
PCI_STP#
VDDZ
I PU
45
CPU_STP#
VDDSD
I PU O O
47 30,31
SDCLK AGP (0:1)
VDDSD VDDAGP
Note: 2. PU = internal pull-up. PD = internal pull-down. T = Tri-level logic input with valid logic voltages of LOW =<0.8V, T =1.0 -1.8V and HIGH => 2.0V.
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Pin Description[2] (continued)
Pin 48 29 11 1 13,19 42 28 36 18,24 41 8 25 5 46 32 37 Name VDDSD VDDAGP VDDZ VDDR VDDP VDDC VDD48M VDDA VSSP VSSC VSSZ VSS48M VSSR VSSSD VSSAGP VSSA PWR I/O Description PWR 3.3V Power Supply for SDRAM Clock Output. PWR 3.3V Power Supply for AGP Clock Outputs. PWR 3.3V Power Supply for HyperZip Clock Outputs. PWR 3.3V Power Supply for REF Clock Outputs. PWR 3.3V Power Supply for PCI Clock Outputs. PWR 3.3V Power Supply for CPU Clock Outputs. PWR 3.3V Power Supply for 48-MHz/24-MHz Clock Outputs. PWR 3.3V Analog Power Supply. PWR GND for PCI Clocks Outputs. PWR GND for CPU Clocks Outputs. PWR GND for HyperZip Clock Outputs. PWR GND for 48-MHz/24-MHz Clock Outputs. PWR GND for REF Clock Outputs. PWR GND for SDRAM Clock Output. PWR GND for AGP Clock Outputs. PWR GND for Analog.
Table 1. Frequency Table FS(4:0) 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 CPU(MHz) 100.2 100.2 100.2 100.2 133.6 133.6 133.6 133.6 166.7 166.7 166.7 166.7 200.1 200.1 200.1 200.1 100.2 100.2 100.2 100.2 133.6 133.6 133.6 133.6 166.7 SDRAM(MHz) 100.2 133.6 200.4 167.0 100.2 133.6 200.4 167.0 100.0 133.4 222.3 166.7 100.0 133.4 200.1 150.0 100.2 133.6 200.4 167.0 100.2 133.6 200.4 167.0 100.0 ZCLK(MHz) 80.2 80.2 80.2 83.5 80.2 80.2 80.2 83.5 83.4 83.4 83.4 83.4 80.0 80.0 80.0 75.0 133.6 133.6 133.6 125.3 133.6 133.6 133.6 133.6 125.0 AGP(MHz 66.8 66.8 66.8 62.6 66.8 66.8 66.8 66.8 62.5 66.7 66.7 66.7 66.7 66.7 66.7 66.7 66.8 66.8 66.8 62.6 66.8 66.8 66.8 66.8 62.5 PCI(MHz) 33.4 33.4 33.4 31.3 33.4 33.4 33.4 33.4 31.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.4 33.4 33.4 31.3 33.4 33.4 33.4 33.4 31.3 VCO(MHz) 400.8 400.8 400.8 501.0 400.8 400.8 400.8 668.0 500.1 666.8 666.8 666.8 400.1 400.1 400.1 600.2 400.8 400.8 400.8 501.0 400.8 400.8 400.8 668.0 500.1
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Table 1. Frequency Table (continued) FS(4:0) 11001 11010 11011 11100 11101 11110 11111 CPU(MHz) 166.7 166.7 166.7 200.1 200.1 200.1 200.1 SDRAM(MHz) 133.4 222.3 166.7 100.0 133.4 200.1 150.0 ZCLK(MHz) 133.4 133.4 133.4 133.4 133.4 133.4 120.0 AGP(MHz 66.7 66.7 66.7 66.7 66.7 66.7 66.7 PCI(MHz) 33.3 33.3 33.3 33.3 33.3 33.3 33.3 VCO(MHz) 666.8 666.8 666.8 400.1 400.1 400.1 600.2
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 2. The block write and block read protocol is outlined in Table 3 while Table 4 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h).
Table 2. Command Code Definition Bit 7 (6:0) Description 0 = Block read or block write operation, 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Table 3. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 .... .... .... .... .... Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits `00000000' stands for block operation Acknowledge from slave Byte Count - 8 bits Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data byte 2 - 8 bits Acknowledge from slave ...................... Data Byte (N-1) -8 bits Acknowledge from slave Data Byte N -8 bits Acknowledge from slave Description Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39:46 47 48:55 56 .... Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits `00000000' stands for block operation Acknowledge from slave Repeat start Slave address - 7 bits Read = 1 Acknowledge from slave Byte count from slave - 8 bits Acknowledge Data byte from slave - 8 bits Acknowledge Data byte from slave - 8 bits Acknowledge Data bytes from slave/Acknowledge Block Read Protocol Description
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Table 3. Block Read and Block Write Protocol (continued) .... Stop .... .... .... Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 2:8 9 10 11:18 Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits `1xxxxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte from master - 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits `1xxxxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address - 7 bits Read = 1 Acknowledge from slave Data byte from slave - 8 bits Not Acknowledge Stop Byte Read Protocol Description Data byte N from slave - 8 bits Not Acknowledged Stop
19 20:27 28 29
19 20 21:27 28 29 30:37 38 39
Since SDR and DDR Zero Delay Buffers, will share this same address, this device starts from Byte 4. Byte 4: CPU Clock Register Bit 7 6 5 4 3 2 1 0 @Pup H/W Setting H/W Setting H/W Setting H/W Setting 0 H/W Setting 1 0 Name FS3 FS2 FS1 FS0 SW/HW Frequency Setting Selection FS4 SSCG Description For selecting frequencies in Table 1 For selecting frequencies in Table 1 For selecting frequencies in Table 1 For selecting frequencies inTable 1 If this bit is programmed to a "1", it enables writes to bits (7:4, 2) for selecting the frequency via software (SMBus) If this bit is programmed to a "0" it enables only reads of bits (7:4, 2), which reflect the hardware setting of FS(0:4). For selecting frequencies in Table 1 Spread Spectrum Enable. 0 = Spread Off, 1 = Spread On. This is a Read and Write control bit. Master Output Control. 0 = running, 1 = three-state all outputs
Byte 5: CPU Clock Register Bit 7 6 5 4 3 @Pup 0 0 X X X MULT0 FS4 FS3 Name Reserved Reserved MULT0 (pin 26) Value. This bit is Read-Only FS4 read back. This bit is Read-Only FS3 read back. This bit is Read-Only. Description
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Byte 5: CPU Clock Register (continued) Bit 2 1 0 @Pup X X X Name FS2 FS1 FS0 Description FS2 read back. This bit is Read-Only. FS1 read back. This bit is Read-Only. FS0 read back. This bit is Read-Only.
Byte 6: CPU Clock Register Bit 7 6 5 4 3 @Pup 0 0 0 0 1 PCIF0 PCIF1 CPU[T/C]0 Name Reserved PCI_STP# control of PCIF0. 0 = Free-Running, 1 = Stopped when PCI_STP# is LOW. PCI_STP# control of PCIF1. 0 = Free-Running, 1 = Stopped when PCI_STP# is LOW. Controls CPUT0 and CPUC0 functionality when CPU_STP# is asserted LOW 0 = Free-Running, 1 + Stopped with CPU_STP# asserted LOW This is a Read and Write Control bit. Controls CPUT1 and CPUC1 functionality when CPU_STP# is asserted LOW 0 = Free-Running, 1 Stopped with CPU_STP# asserted to LOW This and Read and Write Control Bit. CPUT0, CPUC0 Output Control, 1 = enabled, 0 = disabled. This is a Read and Write Control bit. CPUT1, CPUC1 Output Control, 1 = enabled, 0 = disabled. This is a Read and Write Control bit. Description Function Test Bit, always program to 0.
2
0
CPU[T/C]1
1 0
1 1
CPU0T/C CPU1T/C
Byte 7: PCI Clock Register Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Name PCIF0 PCIF1 PCI5 PCI4 PCI3 PCI2 PCI1 PCI0 Description PCIF0 Output Control 1 = enabled, 0 = forced LOW PCIF1 Output Control 1 = enabled, 0 = forced LOW PCI5 Output Control 1 = enabled, 0 = forced LOW PCI4 Output Control 1 = enabled, 0 = forced LOW PCI3 Output Control 1 = enabled, 0 = forced LOW PCI2 Output Control 1 = enabled, 0 = forced LOW PCI1 Output Control 1 = enabled, 0 = forced LOW PCI0 Output Control 1 = enabled, 0 = forced LOW
Byte 8: Silicon Signature Register Bit 7 6 5 4 3 2 1 0 @Pup 1 0 0 0 0 0 0 0 Revision ID Vendor ID 1000 = Cypress Description
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Byte 9: Peripheral Control Register Bit 7 6 5 4 3 2 1 0 @Pup 1 0 1 1 0 0 0 0 Name PD# PD# output control 48M 48M_24M 48M_24M SS2 SS1 SS0 Description PD# Enable. 0 = enable, 1 = disable 0 = when PD# is asserted LOW, CPU(0:1)T stop in a high state, CPUC[0:1] stop in a low state. 1 = when PD# is asserted LOW, CPUT[0:1] and CPUC[0:1] stop in H-Z. 48M Output Control 1 = enabled, 0 = forced LOW 48M_24M Output Control 1 = enabled, 0 = forced LOW 48M_24M, 0 = pin28 output is 24 MHz, 1 = pin26 output is 48 MHz. SS2 Spread Spectrum control bit (0 = down spread, 1 = center spread) SS1 Spread Spectrum control bit. See Table 5. SS0 Spread Spectrum control bit. See Table 5.
Table 5. Spread Spectrum SS2 0 0 0 0 1 1 1 1 SS1 0 0 1 1 0 0 1 1 SS0 0 1 0 1 0 1 0 1 Spread Mode Down Down Down Down Center Center Center Center Spread% -0.50 -0.75 -1.00 -1.50 +0.25, -0.25 +0.37, -0.37 +0.50, -0.50 +0.75, -0.75
Byte 10: Peripheral Control Register Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Name SDCLK REF2 REF1 REF0 ZCLK1 ZCLK0 AGP1 AGP0 Description SDCLK Output Enable 1 = enabled, 0 = disabled REF2 Output Control 1 = enabled, 0 = forced LOW REF1 Output Control 1 = enabled, 0 = forced LOW REF0 Output Control 1 = enabled, 0 = forced LOW ZCLK1 Output Enable 1 = enabled, 0 = disabled ZCLK0 Output Enabled 1 = enabled, 0 = disabled AGP1 Output Enabled 1 = enabled, 0 = disabled AGP0 Output Enabled 1 = enabled, 0 = disabled
Byte 11: Dial-a-SkewTM and Dial-a-Ratio Control Register Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name DARZCK2 DARZCK1 DARZCK0 DARAG2 DARAG1 DARAG0 DASSD1 DASSD0 Programming these bits allow shifting skew between CPU and SDCLK signals. See Table 8. Programming these bits allow modifying the frequency ratio of the AGP(1:0), PCI(5:0) and PCIF(0:1) clocks relative to the VCO. See Table 7 Description Programming these bits allow modifying the frequency ratio of the ZCLK clock relative to the VCO. See Table 6.
Table 6. Dial-a-Ratio for ZCLK DARZCK(2:0) 000 Document #: 38-07546 Rev. ** VC0/ZCLK Ratio Frequency Selection Default Page 7 of 19
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Table 6. Dial-a-Ratio for ZCLK (continued) 001 010 011 100 101 110 111 Table 7. Dial-a-Ratio for AGP(0:1)[3] DARAG(2:0) 000 001 010 011 100 101 110 111 Table 8. Dial-a-Skew SDCLK CPU DASSD(1:0) 00 01 10 11 Byte 12: Watchdog Time Stamp Register Bit 7 @Pup 1 Name SRESET#/ PCI_STP# Selection Description SRESET#/PCI_STP#. 1 = Pin 12 is the input pin as PCI_STP# signal. 0 = Pin 12 is the output pin as SRESET# signal. Frequency Revert. This bit allows setting the Revert Frequency once the system is rebooted due to Watchdog time out only. 0 = selects frequency of existing H/W setting1 = selects frequency of the second to last S/W setting. (the software setting prior to the one that caused a system reboot). WDTEST. For WD-Test, ALWAYS program to `0' WD Alarm. This bit is set to "1" when the Watchdog times out. It is reset to "0" when the system clears the WD time stamps (WD3:0). WD3 WD2 WD1 WD0 This bits selects the Watchdog Time Stamp Value. See Table 9 SDCLK-CPU Skew 0ps (Default)[4] +150ps (CPU lag)* +300ps (CPU lag)* +450ps (CPU lag)* VC0/AGP Ratio Frequency Selection Default 6 7 8 9 10 10 10 2 3 4 5 6 8 9
6 5 4 3 2 1 0
0 0 0 0 0 0 0
Notes: 3. The ratio of AGP to PCI is retained at 2:1. 4. See Figure 9 for CPU test measurement point. See Figure 10 for SDCLK test measurement point.
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Table 9. Watchdog Time Stamp Table WD(3:0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 FUNCTION Off 1 second 2 seconds 3 seconds 4 seconds 5 seconds 6 seconds 7 seconds 8 seconds 9 seconds 10 seconds 11 seconds 12 seconds 13 seconds 14 seconds 15 seconds
Byte 13: Dial-a-Frequency Control Register N (all bits are read- and write-functional)[5] Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Reserved N6, MSB N5 N4 N3 N2 N3 N0, LSB Description
Byte 14: Dial-a-Frequency Control Register R (all bits are read- and write-functional)[5, 6] Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Reserved R5 MSB R4 R3 R2 R1 R0, LSB R and N register mux selection. 0 = R and N values come from the ROM. 1 = data is loaded from the Dial-a-Frequency registers into R and N. Description
Notes: 5. Byte 13 and Byte 14 should be written together in every case. 6. The range of R = (20...60), The range of N = (21...125) and N > R > N/2.
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Dial-A-Frequency Feature
SMBus Dial-A-frequency feature is available in this device via Byte13 and Byte14. P is a large value PLL constant that depends on the frequency selection achieved through the hardware selectors (FS4, FS0). P value may be determined from the following table. Table 10. FS(4:0) 00100, 00101, 00110, 01000, 01111,10100,10101,10110,11000,11111 00000, 00001, 00010, 01001, 01010, 01011, 10000, 10001,10010,11001,11010,11011 00011, 00111,10011,10111 01100, 01101, 01110,11100,11101,11110 Dial-A-Frequency Formula Fcpu = (P*N)/R and Range of R = (20..60), Range of N = (21..125) where N > R > N/2. For a more detail programming guide, please refer to Cypress "genapp.pfd" file AN-0025. Spread Spectrum Clock Generation (SSCG) Spread Spectrum is a modulation technique used to minimizing EMI radiation generated by repetitive digital signals. A clock presents the greatest EMI energy at the center frequency it is generating. Spread Spectrum distributes this energy over a specific and controlled frequency bandwidth therefore causing the average energy at any one point in this band to decrease in value. This technique is achieved by modulating the clock away from its resting frequency by a certain percentage (which also determines the amount of EMI reduction). In this device, Spread Spectrum is enabled by setting specific register bits in the SMBus control Bytes. See the SMBus register section of this data sheet for the exact bit and byte functionally. The following table is a listing of the modes and percentages of Spread Spectrum modulation that this device incorporates. P 127994666.7 95996000 76796800 191992000 PD# (Power-down) Clarification The PD# (Power-down) pin is used to shut off ALL clocks prior to shutting off power to the device. PD# is an asynchronous active LOW input. This signal is synchronized internally to the device powering down the clock synthesizer. PD# is an asynchronous function for powering up the system. When PD# is low, all clocks are driven to a LOW value and held there and the VCO and PLLs are also powered down. All clocks are shut down in a synchronous manner so has not to cause glitches while transitioning to the low `stopped' state. PD# - Assertion When PD# is sampled low by two consecutive rising edges of CPUC clock then all clock outputs (except CPUT) clocks must be held low on their next high to low transition. CPUT clocks must be hold with CPUT clock pin driven high with a value of 2x Iref and CPUC undriven. Due to the state of internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete PD# Deassertion The power-up latency between PD# rising to a valid logic `1' level and the starting of all clocks is less than 3.0 ms. CPU_STP# Clarification The CPU_STP# signal is an active low input used for synchronous stopping and starting the CPU output clocks while the rest of the clock generator continues to function. CPU_STP# Assertion When CPU_STP# pin is asserted, all CPU outputs that are set with the SMBus configuration to be stoppable via assertion of CPU_STP# will be stopped after being sampled by two falling CPU clock edges. The final state of the stopped CPU signals is CPU = HIGH and CPUC0 = LOW. There is no change to the output drive current values during the stopped state. The CPU is driven HIGH with a current value equal to (Mult 0 `select') x (Iref), and the CPUC signal will not be driven. Due to external pull-down circuitry CPUC will be LOW during this stopped state.
CPU_STP#
CPUT
CPUC CPU Internal
CPU# Internal
Figure 1. Power-down Assertion/Deassertion Timing Waveforms - Nonbuffered Mode Document #: 38-07546 Rev. ** Page 10 of 19
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CPU_STP# CPUT CPUC
Figure 2. Assertion CPU_STP# Waveforms CPU_STP# Deassertion The de-assertion of the CPU_STP# signal will cause all CPU outputs that were stopped to resume normal operation in a synchronous manner. Synchronous manner meaning that no short or stretched clock pulses will be produce when the clock resumes. The maximum latency from the Deassertion to active outputs is no more than two CPU clock cycles.
CPU_STP# CPUT CPUC CPUT CPUC
Figure 3. Deassertion CPU_STP# Waveforms PCI_STP# Assertion The PCI_STP# signal is an active LOW input used for synchronous stopping and starting the PCI outputs while the rest of the clock generator continues to function. The set-up time for capturing PCI_STP# going LOW is 10 ns (tsetup). (See Figure 4.) The PCIF (clocks will not be affected by this pin if their control bits in the SMBus register are set to allow them to be free running.
t setup
PC I_STP # PC I_F 33M PC I 33M
Figure 4. Assertion PCI_STP# Waveforms
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PCI_STP# Deassertion The deassertion of the PCI_STP# signal will cause all PCI and stoppable PCIF clocks to resume running in a synchronous manner within two PCI clock periods after PCI_STP# transitions to a high level.
t setup
P C I_S T P # P C I_F PCI
Figure 5. Deassertion PCI_STP# Waveforms[7]
FS VTT_PWRGD PWRGD_VRM
VDD Clock Gen Clock State State 0
0.2-0.3mS Delay State 1
Wait for VTT_PWRGD
Sample FS State 2 State 3
Device is not affected, VTT_PWRGD is ignored
Clock Outputs
Off
On
Clock VCO
Off
On
Figure 6. VTT_PWRGD Timing Diagram
S1 S2 VTT_PWRGD = Low
Delay >0.25mS
VDD_A = 2.0V
Sample Inputs straps
Wait for <1.8ms S0 S3 VDD_A = off
Power Off
Normal Operation
VTT_PWRGD = toggle
Enable Outputs
Figure 7. Clock Generator Power-up/Run State Diagram
Note: 7. The PCI STOP function is controlled by two inputs. One is the device PCI_STP# pin number 34 and the other is SMBus byte 0 bit 3. These two inputs are logically ANDed. If either the external pin or the internal SMBus register bit is set low then the stoppable PCI clocks will be stopped in a logic low state. Reading SMBus Byte 0 Bit 3 will return a 0 value if either of these control bits are set LOW thereby indicating the device's stoppable PCI clocks are not running.
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Watchdog Self-Recovery Sequence
This feature is designed to allow the system designer to change frequency while the system is running and reboot the operation of the system in case of a hang up due to the frequency change. When the system sends an SMBus command requesting a frequency change through the Dial-a-Frequency Control Registers, it must have previously sent a command to the Watchdog Timer to select which time out stamp the Watchdog must perform, otherwise the System Self-recovery feature will not be applicable. Consequently, this device will change frequency and then the Watchdog timer starts timing. Meanwhile, the system BIOS is running its operation with the new frequency. If this device receives a new SMBus command to clear the bits originally programmed in the Watchdog Timer bits (reprogram to 0000) before the Watchdog times out, then this device will keep operating in its normal condition with the new selected frequency. The Watchdog timer will also be triggered if you program the software frequency select bits (FSEL) to a new frequency selection. If the Watchdog times out before the new SMBus reprograms the Watchdog Timer bits to (0000), then this device will send a low system reset pulse, on SRESET# and changes WD Time-out bit to "1."
RESET W ATCHDOG TIMER Set WD(0:3) Bits = 0
INITIALIZE W ATCHDOG TIMER Set Frequency Revert Bit Set WD(0:3) = (# of Sec ) x 2
SET SOFTW ARE FSEL Set SW Freq_Sel = 1 Set FS(0:4)
SET DIAL-A-FREQUENCY Load M and N Registers Set Pro_Freq_EN = 1
Wait for 6msec For Clock Output to Ramp to Target Frequency
Hang?
N
CLEAR W D Set WD(0:3) Bits = 0
Exit
Y
W ATCHDOG TIMEOUT
Frequency Revert Bit = 0 Set Frequency to FS_HW_Latched
Frequency Revert Bit = 1 Set Frequency to FS_SW
Set SRESET# = 0 for 6 msec
Reset
Figure 8. Watchdog Self-recovery Sequence Flowchart
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CY28381
Absolute Maximum Conditions
Parameter VDD VDDA VIN TS TA TJ ESDHBM OJC OJA UL-94 MSL Description Core Supply Voltage Analog Supply Voltage Input Voltage Temperature, Storage Temperature, Operating Ambient Temperature, Junction ESD Protection (Human Body Model) Dissipation, Junction to Case Dissipation, Junction to Ambient Flammability Rating Moisture Sensitivity Level Relative to V SS Non Functional Functional Functional MIL-STD-883, Method 3015 Mil-Spec 883E Method 1012.1 JEDEC (JESD 51) At 1/8 in. Condition Min. -0.5 -0.5 -0.5 -65 0 - 2000 15 45 V-0 1 Max. 4.6 4.6 VDD + 0.5 +150 70 150 - Unit V V VDC C C C V C/W C/W
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter VDDSD, VDDAGP, VDDZ, VDDR, VDDP, VDDC, VDD48M, VDDA VILI2C VIHI2C VIL VIH IIL VOL VOH IOZ CIN COUT LIN VXIH VXIL IDD IPD CXTAL Description 3.3V Operating Voltage 3.3V 5% Condition Min. 3.135 Max. 3.465 Unit V
Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Leakage Current Output Low Voltage Output High Voltage High-Impedance Output Current Input Pin Capacitance Output Pin Capacitance Pin Inductance Xin High Voltage Xin Low Voltage Dynamic Supply Current Power-down Supply Current Crystal Pin Capacitance
SDATA, SCLK SDATA, SCLK
- 2.2 VSS - 0.5 2.0
- - 0.8 VDD + 0. 5 5 0.4 - 10 5 6 7 VDD 0.3VDD 300 1 42
1.0 - V V A V V A pF pF nH V V mA mA pF
except Pull-ups or Pull downs 0 < VIN < VDD IOL = 1 mA IOH = -1 mA
-5 - 2.4 -10 2 3 - 0.7VDD 0
At 200 MHz and all outputs loaded per Table 11 and Figure 7 PD# Asserted Nominal = 36 pF
- - 30
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CY28381
AC Electrical Specifications
Parameter Crystal TDC Description XIN Duty Cycle Condition The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification When Xin is driven from an external clock source Min. Max. Unit
47.5 69.841 0.7VDD 0
52.5 71.000 VDD 0.3VDD 10.0 500 55 10.2 7.65 150 200 900 20 125 125 430 55 15.3 175 1.6 - - 500 55 1.6 175 500 55 30.0 - - 2.0 500 500 55
% ns V V ns ps % ns ns ps ps ps % ps ps mv % ns ps ns ns ns ps % ns ps ps % ns ns ns ns ps ps %
TPERIOD VXIH VXIL TR / TF TCCJ
XIN period Xin High Voltage Xin Low Voltage XIN Rise and Fall Times XIN Cycle to Cycle Jitter
Measured between 0.3VDD and 0.7VDD As an average over 1s duration Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured from Vol = 0.175 to Voh = 0.525V Determined as a fraction of 2*(TR-TF)/(TR+TF)
- - 45 9.8 7.35 - - 175 - - - 280
CPU at 0.7V TDC CPUT and CPUC Duty Cycle TPERIOD100 100-MHz CPUT and CPUC Period TPERIOD133 133-MHz CPUT and CPUC Period TSKEW TCCJ TR / TF TRFM TR TF VOX AGP TDC TPERIOD TSKEWUNBUFFERED
Any CPUT/C to CPUT/C Clock Skew CPUT/C Cycle to Cycle Jitter CPUT and CPUC Rise and Fall Times Rise/Fall Matching Rise Time Variation Fall Time Variation Crossing Point Voltage at 0.7V Swing AGP Duty Cycle AGP Period Any AGP to Any AGP Clock Skew AGP Rise and Fall Times AGP High Time AGP Low Time AGP Cycle to Cycle Jitter ZCLK Duty Cycle ZCLK Rise and Fall Times Any ZCLK to Any ZCLK Clock Skew ZCLK Cycle to Cycle Jitter PCI/PCIF Duty Cycle PCIF/PCI Period PCIF and PCI High Time PCIF and PCI Low Time PCIF and PCI Rise and Fall Times Any PCI clock to Any PCI Clock Skew PCIF and PCI Cycle to Cycle Jitter SDCLK Duty Cycle
Measured at crossing point VOX Measured at crossing point VOX Measurement at 1.5V Measured from Vol= 0.175 to Voh = 0.525V
45 15.0 - 0.5 5.25 5.05
TR / TF THIGH TLOW TCCJ ZCLK TDC TR / TF TSKEW TCCJ PCI/PCIF TDC TPERIOD THIGH TLOW TR / TF TSKEW TCCJ SDCLK TDC
Measured at crossing point VOX Measurement at 1.5V Measured between 0.4V and 2.4V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.4V and 2.4V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V
- 45 0.5 - - 45 30.0 12.0 12.0 0.5 - - 45
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CY28381
AC Electrical Specifications (continued)
Parameter TPERIOD THIGH100 THIGH133 TLOW100 TLOW133 TR / TF TCCJ 48M TDC TPERIOD TR / TF TCCJ 24M TDC TPERIOD TR / TF TCCJ REF TDC TPERIOD TR / TF TCCJ Description SDCLK Period SDCLK High Time SDCLK High Time SDCLK Low Time SDCLK Low Time SDCLK Rise and Fall Times SDCLK Cycle to Cycle Jitter 48M Duty Cycle 48M Period 48M Rise and Fall Times 48M Cycle to Cycle Jitter 24M Duty Cycle 24M Period 24M Rise and Fall Times 24M Cycle to Cycle Jitter REF Duty Cycle REF Period REF Rise and Fall Times REF Cycle to Cycle Jitter Condition Measurement at 1.5V Measurement at 2.4V Measurement at 2.4V Measurement at 0.4V Measurement at 0.4V Measured between 0.4V and 2.4V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured between 0.4V and 2.4V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured between 0.4V and 2.4V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured between 0.4V and 2.4V Measurement at 1.5V Min. 7.4 3.0 1.87 2.8 1.67 0.4 - 45 20.829 1.0 - 45 41.66 1.0 - 45 69.841 1.0 - 1.0 1.0 - 10.0 0 1.6 800 55 20.834 2.0 500 55 41.67 4.0 800 55 71.00 4.0 1000 10.0 10.0 1.5 - - Max. 15.0 Unit ns ns ns ns ns ns ps % ns ns ps % ns ns ps % ns V/ns ps ns ns ms ns ns
ENABLE/DISABLE and SET-UP tpZL,tpZH Output Enable Delay(all outputs) tpLZ,tpZH TSTABLE TSS TSH Output Disable Delay (all outputs) Clock Stabilization from Power-up Stopclock Set-up Time Stopclock Hold Time
Table 11. Maximum Lumped Capacitive Output Loads Clock PCI, PCIF AGP, SDCLK ZCLK 48M_24, 48M Clock REF CPUT,CPUC Max Load 30 30 10 20 30 2 Units pF pF pF pF pF pF
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CY28381
Test and Measurement Set-up
For Differential CPU Output Signals The following diagram shows lumped test load configurations for the differential Host Clock Outputs.
T PCB
49.9 2pF
33
CPUT
Measurem ent Point
MULTSEL
33
T PCB
49.9 2pF
Measurem ent Point
CPUC IREF
475
Figure 9. 0.7V Configuration
O u tp u t u n d e r T e s t P ro b e
Load Cap
3 .3 V s ig n a l s
tD C
-
3 .3 V
2 .4 V
1 .5 V
0 .4 V 0V
Tr
Tf
Figure 10. Lumped Load for Single-Ended Output Signals (for AC Parameters Measurement) Table 12. CPU Clock Current Select Function Mult0 0 1 Board Target Trace/Term Z 50 Ohms (not used) 50 Ohms Reference R, Iref - Vdd (3*Rr) Rr = 221 1%, Iref = 5.00mA Rr = 475 1%, Iref = 2.32mA Output Current Ioh = 4*Iref Ioh = 6*Iref Voh @ Z 1.0V @ 50 0.7V @ 50
Table 13. Group Timing Relationship and Tolerances Offset CPU to SDCLK CPU to AGP CPU to ZCLK CPU to PCI TypicaL 0 ns TypicaL 2 ns TypicaL 2 ns Typical 2 ns Tolerance (or Range) 2 ns 1-4 ns 1-4 ns 1-4 ns Conditions CPU leads CPU leads CPU leads CPU leads Notes See Note 8 See Note 8 See Note 8 See Note 8
Note: 8. See Figure 9 for CPU clocks measurement point. SeeFigure 10 for SDCLK, AGP, ZCLK and PCI Outputs measurement point.
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CY28381
Ordering Information
Part Number CY28381OC CY28381OCT Package Type 48-pin Shrunk Small Outline package (SSOP) 48-pin Shrunk Small Outline package (SSOP) - Tape and Reel Product Flow Commercial, 0 to 70C Commercial, 0 to 70C
Package Drawing and Dimensions
48-lead Shrunk Small Outline Package O48
51-85061-*C
Pentium is a registered trademark of Intel Corporation. Dial-a-Frequency is a registered trademark, and Dial-a-dB, Dial-a-Skew, and Dial-a-Ratio are trademarks, of Cypress Semiconductor. All product and company names mentioned in this document are trademarks of their respective owners.
Document #: 38-07546 Rev. **
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(c) Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY28381
Document History Page
Document Title: CY28381 High-Performance SiS645DX/648DX/650/651 Intel Pentium 4 Clock Synthesizer Document Number: 38-07511 REV. ** ECN NO. 126496 Issue Date 05/23/03 Orig. of Change RGL New Data Sheet Description of Change
Document #: 38-07546 Rev. **
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