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Integrated Circuit Systems, Inc.
ICS853L022
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 3.3V LVPECL TRANSLATOR
FEATURES
* 2 differential LVPECL outputs * LVCMOS/LVTTL clock inputs * Output frequency: 350MHz (typical) * Part-to-part skew: 400 (maximum) * Propagation Delay: 450ps (typical) * Additive phase jitter, RMS: 0.03ps (typical) * LVPECL mode operating voltage supply range: VCC = 3.0V to 3.8V, VEE = 0V * ECL mode operating voltage supply range: VCC = 0V, VEE = -3.8V to -3.0V * -40C to 85C ambient operating temperature * Lead-Free package RoHS compliant
GENERAL DESCRIPTION
The ICS853L022 is a Dual LVCMOS / LVTTL-toDifferential 3.3V LVPECL translator and a memHiPerClockSTM ber of the HiPerClocksTM family of High Performance Clocks Solutions from ICS. The ICS853L022 has single ended clock inputs. The single ended clock input accepts LVCMOS or LVTTL input levels and translate them to LVPECL levels. The small outline 8pin TSSOP package makes this device ideal for applications where space, high performance and low power are important.
ICS
BLOCK DIAGRAM
D0 Q0 nQ0 Q1 nQ1
PIN ASSIGNMENT
Q0 nQ0 Q1 nQ1 1 2 3 4 8 7 6 5 VCC D0 D1 VEE
D1
ICS853L022
8-Lead TSSOP, 118 mil 3mm x 3mm x 0.95mm package body G Package Top View 8-Lead SOIC, 150 mil 3.90mm x 4.90mm x 1.37mm package body M Package Top View
853L022AG
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1
REV. A FEBRUARY 23, 2005
Integrated Circuit Systems, Inc.
ICS853L022
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 3.3V LVPECL TRANSLATOR
Type Output Output Power Input Input Power Description Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Negative supply pin. LVCMOS / LVTTL clock input. LVCMOS / LVTTL clock input. Positive supply pin.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 4 5 6 7 8 Name Q0, nQ0 Q1, nQ1 VEE D1 D0 VCC
853L022AG
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2
REV. A FEBRUARY 23, 2005
Integrated Circuit Systems, Inc.
ICS853L022
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 3.3V LVPECL TRANSLATOR
4.6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage -4.6V (ECL mode, VCC = 0) to the device. These ratings are stress specifi-0.5V to VCC + 0.5 V 0.5V to VEE - 0.5V 50mA 100mA -65C to 150C 101.7C/W (0 m/s) TSSOP 112.7C/W (0 lfpm) SOIC cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Negative Supply Voltage, VEE Inputs, VI (LVPECL mode) Inputs, VI (ECL mode) Outputs, IO Continuous Current Surge Current Storage Temperature, TSTG Package Thermal Impedance, JA
(Junction-to-Ambient)
Operating Temperature Range, TA -40C to +85C
TABLE 2A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.0V TO 3.8V; VEE = 0V
Symbol VCC IEE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 3.0 Typical 3.3 Maximum 3.8 30 Units V mA
TABLE 2B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 3.0V TO 3.8V; VEE = 0V
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current VCC = VIN = 3.8V VCC = 3.8V, VIN = 0V Test Conditions Minimum 0.7 * VCC 0.3 * VCC 100 -0.6 Typical Maximum Units V V A mA
TABLE 2C. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
Symbol VOH Parameter Output High Voltage; NOTE 1 Min
2.175
-40C Typ
2.275
Max
2.38
Min
2.225 1.425
25C Typ
2.295 1.52
Max
2.37 1.615
Min
2.295 1.44
85C Typ
2.33 1.535
Max
2.365 1.63
Units
V V
1.405 1.545 1.68 VOL Output Low Voltage; NOTE 1 Output parameters var y 1:1 with VCC. VCC can var y 3.8V to 3.0V. NOTE 1: Outputs terminated with 50 to VCC - 2V.
853L022AG
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3
REV. A FEBRUARY 23, 2005
Integrated Circuit Systems, Inc.
ICS853L022
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 3.3V LVPECL TRANSLATOR
-40C Min
-1.125 -1.895
TABLE 2D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -3.0V
Symbol VOH VOL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 25C Max
-0.92 -1.62 1200
85C Max
-0.93 -1.685 1200
Typ
-1.025 -1.755 800
Min
-1.075 -1.875 150
Typ
-1.005 -1.78 800
Min
-1.005 -1.86 150
Typ
-0.97 -1.765 800
Max
-0.935 -1.67 1200
Units V V mV
150 VPP Peak-to-Peak Input Voltage Output parameters vary 1:1 with VCC. NOTE 1: Outputs terminated with 50 to VCC - 2V.
TABLE 3. AC CHARACTERISTICS, VCC = 0V; VEE = -3.8V TO -3.0V OR VCC = 3.0V TO 3.8V; VEE = 0V
Symbol fMAX t pLH Parameter Output Frequency Propagation Delay, Low to High; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section Output Rise/Fall Time 20% to 80% 100 300 -40C Min Typ 350 525 10 750 45 225 0.03 325 550 100 0.03 325 550 100 300 Max Min 25C Typ 350 450 10 600 45 225 0.03 325 550 300 Max Min 85C Typ 350 450 10 600 45 225 Max Units MHz ps ps ps ps ps
tsk(o) tsk(pp) tjit
tR/tF
All parameters are measured 350MHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
853L022AG
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4
REV. A FEBRUARY 23, 2005
Integrated Circuit Systems, Inc.
ICS853L022
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 3.3V LVPECL TRANSLATOR
PARAMETER MEASUREMENT INFORMATION
2V
nQx
VCC
Qx
SCOPE
Qx nQy
LVPECL
VEE
nQx
Qy
tsk(o)
-1.8V to -1.0V
OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
nQx PART 1 Qx nQy PART 2 Qy
D0, D1
nQ0, nQ1
tsk(pp)
Q0, Q1
tpLH
PART-TO-PART SKEW
PROPAGATION DELAY
80% Clock Outputs
80% VSW I N G
20% tR tF
20%
OUTPUT RISE/FALL TIME
853L022AG
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5
REV. A FEBRUARY 23, 2005
Integrated Circuit Systems, Inc.
ICS853L022
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 3.3V LVPECL TRANSLATOR APPLICATION INFORMATION
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 1A and 1B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50
125
FOUT FIN
125
Zo = 50
Zo = 50 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FOUT
FIN
Zo = 50 84 84
FIGURE 1A. LVPECL OUTPUT TERMINATION
FIGURE 1B. LVPECL OUTPUT TERMINATION
853L022AG
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6
REV. A FEBRUARY 23, 2005
Integrated Circuit Systems, Inc.
ICS853L022
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 3.3V LVPECL TRANSLATOR POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853L022. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS853L022 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.8V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 30mA = 114mW Power (outputs)MAX = 30.94mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30.94mW = 61.88mW
Total Power_MAX (3.8V, with all outputs switching) = 114mW + 61.88mW = 175.88mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 1 meters per second and a multi-layer board, the appropriate value is 90.5C/W per Table 4A below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.176W * 90.5C/W = 100.9C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 4A. THERMAL RESISTANCE JA
FOR
8-PIN TSSOP, FORCED CONVECTION
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 101.7C/W
1
90.5C/W
2
89.8C/W
TABLE 4B. THERMAL RESISTANCE JA
FOR
8 LEAD SOIC
JA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 153.3C/W 128.5C/W 115.5C/W Multi-Layer PCB, JEDEC Standard Test Boards 112.7C/W 103.3C/W 97.1C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
853L022AG
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7
REV. A FEBRUARY 23, 2005
Integrated Circuit Systems, Inc.
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 4.
ICS853L022
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 3.3V LVPECL TRANSLATOR
VCC
Q1
VOUT
RL
50 VCC - 2V
Figure 4. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = V (V
CC_MAX
OH_MAX
=V
CCO_MAX
- 0.935V
-V
OH_MAX
) = 0.935V =V - 1.67V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CCO_MAX
-V
OL_MAX
) = 1.67V
Pd_H = [(V
OH_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
L
CCO _MAX
-V
OH_MAX
)=
[(2V - 0.935V)/50] * 0.935V = 19.92mW
Pd_L = [(V
OL_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
))/R ] * (V
L
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.67V)/50] * 1.67V = 11.02mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
853L022AG
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8
REV. A FEBRUARY 23, 2005
Integrated Circuit Systems, Inc.
ICS853L022
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 3.3V LVPECL TRANSLATOR RELIABILITY INFORMATION
TABLE 5A. JAVS. AIR FLOW TABLE
FOR
8 LEAD TSSOP
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 101.7C/W
1
90.5C/W
2
89.8C/W
TABLE 5B.
JAVS. AIR FLOW TABLE FOR 8 LEAD SOIC
JA by Velocity (Linear Feet per Minute)
0 200
128.5C/W 103.3C/W
500
115.5C/W 97.1C/W
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards
153.3C/W 112.7C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853L022 is: 92 Pin compatible with MC100LVELT22
853L022AG
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9
REV. A FEBRUARY 23, 2005
Integrated Circuit Systems, Inc.
ICS853L022
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 3.3V LVPECL TRANSLATOR
FOR
PACKAGE OUTLINE - G SUFFIX
8 LEAD TSSOP
PACKAGE OUTLINE - M SUFFIX
FOR
8 LEAD SOIC
TABLE 6A. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e e1 L aaa 0.40 0 --0 0.79 0.22 0.08 3.00 BASIC 4.90 BASIC 3.00 BASIC 0.65 BASIC 1.95 BASIC 0.80 8 0.10 Millimeters Minimum 8 1.10 0.15 0.97 0.38 0.23 Maximum
TABLE 6B. PACKAGE DIMENSIONS
SYMBOL N A A1 B C D E e H h L 5.80 0.25 0.40 1.35 0.10 0.33 0.19 4.80 3.80 1.27 BASIC 6.20 0.50 1.27 Millimeters MINIMUN 8 1.75 0.25 0.51 0.25 5.00 4.00 MAXIMUM
0 8 Reference Document: JEDEC Publication 95, MS-012
Reference Document: JEDEC Publication 95, MO-187
853L022AG
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10
REV. A FEBRUARY 23, 2005
Integrated Circuit Systems, Inc.
ICS853L022
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 3.3V LVPECL TRANSLATOR
Marking 022A 022A L2AL L2AL 53L022A 53L022A 53L022AL 53L022AL Package 8 lead TSSOP 8 lead TSSOP 8 lead "Lead-Free" TSSOP 8 lead "Lead-Free" TSSOP 8 lead SOIC 8 lead SOIC 8 lead "Lead-Free" SOIC 8 lead "Lead-Free" SOIC Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel tube 2500 tape & reel tube 2500 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 7. ORDERING INFORMATION
Part/Order Number ICS853L022AG ICS853L022AGT ICS853L022AGLF ICS853L022AGLFT ICS853L022AM ICS853L022AMT ICS853L022AMLF ICS853L022AMLFT
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 853L022AG
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11
REV. A FEBRUARY 23, 2005

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