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Integrated Circuit Systems, Inc.
ICS94235
Recommended Application: Output Features: * 1 - Differential pair open drain CPU clocks * 1 - Single-ended open drain CPU clock * 13 - SDRAM @ 3.3V * 7 - PCI @ 3.3V * 2 - AGP @ 3.3V * 1 - 48MHz, @3.3V * 1 - REF @ 3.3V, (selectable strength) through I2C Features: * Programmable ouput frequency * Programmable ouput rise/fall time * Programmable CPU, SDRAM, PCI and AGP skew * Real time system reset output * Spread spectrum for EMI control typically by 7dB to 8dB, with programmable spread percentage * Watchdog timer technology to reset system if over-clocking causes malfunction * Uses external 14.318MHz crystal Skew Specifications: * CPUT - CPUC: <250ps * PCI - PCI: <500ps * CPU - SDRAM: <350ps * SDRAM - SDRAM: <250ps * AGP - AGP: <250ps * AGP - PCI: <750ps * CPU - PCI: <3ns
RESET# *PD# GND X1 X2 AVDD **FS0/REF0 VDD **FS1/AGP0 AGP1 GND *FS2/PCICLK_F PCICLK0 PCICLK1 PCICLK2 GND VDD *MODE/PCICLK3 PCICLK4 PCICLK5 AVDD48 **FS3/48MHz GND SCLK
Pin Configuration
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 GND CPUCLKT0 CPUCLKC0 CPUCLKT1 SDATA SDRAM0 SDRAM1 GND VDD SDRAM2 SDRAM3 SDRAM4 SDRAM5 VDD GND SDRAM6 SDRAM7 SDRAM8 SDRAM9 GND VDD SDRAM10(PCI_STOP#)* SDRAM11 SDRAM12
48-Pin 300mil SSOP & 240mil TSSOP package
Block Diagram
PLL2 48MHz
Functionality
FS 3 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 1 FS 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CP U S DRAM 66.66 66.66 66.66 100.00 100.00 66.66 100.00 100.00 100.00 133.33 120.00 120.00 133.33 100.00 133.33 133.33 90.00 90.00 100.90 100.90 100.00 66.66 100.00 100.00 100.00 133.33 126.00 126.00 133.33 100.00 133.33 133.33 PCI 33.33 33.33 33.33 33.33 33.33 30.00 33.33 33.33 30.00 33.63 33.33 33.33 33.33 31.50 33.33 33.33 AGP 66.66 66.66 66.66 66.66 66.66 60.00 66.66 66.66 60.00 67.27 66.66 66.66 66.66 63.00 66.66 66.66
X1 X2
XTAL OSC PLL1 Spread Spectrum
REF0
CPU DIVDER
2
CPUCLKT (1:0) CPUCLKC0
SDRAM DIVDER
Stop
13
SDRAM (12:0)
SDATA SCLK FS (3:0) PD# PCI_STOP# MODE
Control Logic Config. Reg.
PCI DIVDER Stop
6
PCICLK (5:0) PCICLK_F
AGP DIVDER
Stop
2
AGP (1:0) RESET#
Power Groups
94235 Rev A 01/17/02 Third party brands and names are the property of their respective owners.
ICS94235
Pin Descriptions
PIN NUMBER 1 PIN NAME RESET# TYPE OUT DESCRIPTION Real time system reset signal for frequency value or watchdog timmer timeout. This signal is active low. Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. Crystal input,nominally 14.318M Hz. Crystal output, nominally 14.318M Hz. Ground pins Power supply pins, nominal 3.3V Analog power supply pin, nominal 3.3V Frequency select pin. 14.318 M Hz reference clock. Frequency select pin. AGP outputs defined as 2X PCI. These may not be stopped. AGP outputs defined as 2X PCI. These may not be stopped. Free running PCICLK not stoped by PCI_STOP# Frequency select pin. PCI clock outputs. PCI clock output. Function select pin, 1=Desktop M ode, 0=M obile M ode. Analog power supply pin, nominal 3.3V Frequency select pin. 48M Hz output clock Clock input of I C input, 5V tolerant input Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low SDRAM clock output. SDRAM clock outputs. Data pin for I C circuitry 5V tolerant "True" clocks of differential pair CPU outputs. These open drain outputs need an external 1.5V pull-up. "Complementory" clocks of differential pair CPU outputs. This open drain output need an external 1.5V pull-up.
2 2
2 4 5 3, 11, 16, 23, 29, 34, 41, 48 8, 17, 28, 35, 40 6 7 9 10 12 20, 19, 15, 14, 13 18 21 22 24 27 25, 26, 30, 31, 32, 33, 36, 37, 38, 39, 42, 43 44 45, 47 46
PD# X1 X2
1
IN IN OUT PWR PWR PWR IN OUT IN OUT OUT OUT IN OUT OUT IN PWR IN OUT IN
1
GND VDD AVDD FS0 REF0
2, 3
FS1 AGP0 AGP1 PCICLK_F FS2 PCICLK (5:4) (2:0) PCICLK3 M ODE AVDD48 FS3 48M Hz SCLK PCI_STOP# SDRAM 10 SDRAM (12:11, 9:0 ) SDATA CPUCLKT (1:0) CPUCLKC0
2, 3 1, 3 1, 3
2, 3
IN OUT OUT I/O OUT OUT
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ICS94235
General Description
Mode Pin - Power Management Input Control
MODE, Pin 18 (Latched Input) 0 1 Pin 27 PCI_STOP# (Input) SDRAM10 (Output)
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ICS94235
General I2C serial interface information for the ICS94235 How to Write: How to Read:
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3 (H ) ICS (Slave /Receive r)
ACK
ACK
A CK Byte Count Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK If 7H has been written to B8 ACK Byte 7
Byte 18 ACK Byte 19 ACK Byte 20 ACK Stop Bit
If 12H has been written to B8 ACK If 13H has been written to B8 ACK If 14H has been written to B8 ACK Stop Bit Byte18 Byte 19 Byte 20
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ICS94235
Brief I2C registers description for ICS94235 Programmable System Frequency Generator
Register Name Functionality & Frequency Select Register Output Control Registers Vendor ID & Revision ID Registers Byte 0 Description Output frequency, hardware / I C frequency select, spread spectrum & output enable control register. Active / inactive output control registers/latch inputs read back. Byte 11 bit[7:4] is ICS vendor id - 1001. Other bits in this register designate device revision ID of this part. Writing to this register will configure byte count and how many byte will be read back. Do not write 00H to this byte. Writing to this register will configure the number of seconds for the watchdog timer to reset. Watchdog enable, watchdog status and programmable 'safe' frequency' can be configured in this register. This bit select whether the output frequency is control by hardware/byte 0 configurations or byte 11&12 programming. These registers control the dividers ratio into the phase detector and thus control the VCO output frequency. These registers control the spread percentage amount. Increment or decrement the group skew amount as compared to the initial skew. These registers will control the output rise and fall time.
2
PWD Default See individual byte description See individual byte description See individual byte description
1-6
7
Byte Count Read Back Register Watchdog Timer Count Register
8
08 H
9
10 H
Watchdog Control Registers 10 Bit [6:0]
000,0000
VCO Control Selection Bit
10 Bit [7]
0
VCO Frequency Control Registers Spread Spectrum Control Registers Group Skews Control Registers Output Rise/Fall Time Select Registers
11-12
Depended on hardware/byte 0 configuration Depended on hardware/byte 0 configuration See individual byte description See individual byte description
13-14
15-16 17-20
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ICS94235
Serial Configuration Command Bitmap
Bit Description FS3 FS2 FS1 FS0 CPUCLK SDRAM PCICLK Bit2 Bit7 Bit6 Bit5 Bit4 ( M Hz ) ( M Hz ) (MHz) 0 0 0 0 0 66.66 66.66 33.33 0 0 0 0 1 66.66 100.00 33.33 0 0 0 1 0 100.00 6 6 . 66 33.33 0 0 0 1 1 100.00 100.00 33.33 0 0 1 0 0 100.00 133.33 33.33 0 0 1 0 1 120.00 120.00 30.00 0 0 1 1 0 133.33 100.00 33.33 0 0 1 1 1 133.33 133.33 33.33 0 1 0 0 0 90.00 90.00 30.00 0 1 0 0 1 100.90 100.90 33.63 0 1 0 1 0 100.00 6 6 . 66 33.33 0 1 0 1 1 100.00 100.00 33.33 0 1 1 0 0 100.00 133.33 33.33 0 0 1 0 1 126.00 126.00 31.50 0 1 1 1 0 133.33 100.00 33.33 0 1 1 1 1 133.33 133.33 33.33 1 0 0 0 0 102.00 102.00 34.00 1 0 0 0 1 102.00 136.00 34.00 1 0 0 1 0 136.00 102.00 34.00 1 0 0 1 1 136.00 136.00 34.00 1 0 1 0 0 103.00 103.00 34.33 1 0 1 0 1 103.00 137.33 34.33 1 0 1 1 0 137.33 103.00 34.33 1 0 1 1 1 137.33 137.33 34.33 1 1 0 0 0 105.00 105.00 35.00 1 1 0 0 1 105.00 140.00 35.00 1 1 0 1 0 140.00 140.00 35.00 1 1 0 1 1 107.00 107.00 35.66 1 1 1 0 0 107.00 1 4 2 .6 6 35.66 1 1 1 0 1 133.90 133.90 33.40 1 1 1 1 0 110.00 110.00 36.66 1 1 1 1 1 146.66 146.66 36.66 0 - Frequency is selected by hardware select, Latched Inputs 1 - Frequency is selected by Bit 2, 7:4 0 - Normal 1 - Spread Spectrum Enabled 0 - Running 1- Tristate all outputs AGP (MHz) 66.66 66.66 66.66 66.66 66.66 60.00 66.66 66.66 60.00 67.27 66.66 66.66 66.66 63.00 66.66 66.66 67.99 6 7 .9 9 6 7 .9 9 6 7 .9 9 68.66 68.66 68.66 68.66 6 9 .9 9 6 9 .9 9 6 9 .9 9 7 1 .3 3 71.33 66.95 7 3 .3 3 73.33 Spread Precentage +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread +/- 0.25% Center Spread 0 to -0.5% Down Spread 0 to -0.5% Down Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread +/- 0.25% Center Spread PWD
Bit 2, Bit 7:4
00000 Note1
Bit 3 Bit 1 Bit 0
0 0 0
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ICS94235
BI T
Bi t 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bi t 1 Bit 0
PI N#
10 9 22 43 7 47, 46 45
P WD
X 1 1 1 1 1 1 1 FS3# AGP1 AGP0
DE S CRI P T IO N
BI T Bit 7 Bit 6 Bi t 5 Bit 4 Bi t 3 Bit 2 Bit 1 Bit 0
PIN # 20 19 18 15 14 13 12
PW D X 1 1 1 1 1 1 1
DE S CR I P TI O N MODE# PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 PCICLK_F
48MHz SDRAM0
REF0 - 1X or 2X d ef a u l t = 1 = 1 X
CPUCLKT0, CPUCLKC0 CPUCLKT1
BI T Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PI N # 31 30 27 26 25
PW D X X X 1 1 1 1 1 FS0# FS1# FS2#
D ESCRI PTI O N
BIT Bit 7 Bi t 6 Bit 5 Bi t 4 Bit 3 Bi t 2 Bit 1 Bi t 0
PIN # 39 38 37 36 33 32
PW D 0 1 1 1 1 1 1 1
DE S CR I P TI ON Reserved Reserved S DRAM2 S DRAM3 S DRAM4 S DRAM5 S DRAM6 S DRAM7
SDRAM8 SDRAM9 SDRAM10 SDRAM11 SDRAM12
BI T
Bit 7 Bit 6 Bi t 5 Bit 4 Bi t 3 Bit 2 Bit 1 Bit 0
P IN # P W D
42 1 1 1 1 1 1 1 1
DE SCRI PTI ON
Reserved Reserved Reserved Reserved Reserved Reserved Reserved SDRAM1
BI T B i t7 B it 6 B it5 B it 4 B it3 B it 2 B i t1 B it 0
PI N# -
P WD 0 0 0 0 0 1 1 1
DE S C RI P T IO N Res er ved (Note) Res er ved (Note) Res er ved (Note) Res er ved (Note) Res er ved (Note) Res er ved (Note) Res er ved (Note) Res er ved (Note)
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ICS94235
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 0 0 1 X X X X X
Description Vendor ID Vendor ID Vendor ID Revision ID Revision ID Revision ID Revision ID Revision ID
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 0 0 0 0 1 0 0 0
Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 0 0 0 1 0 0 0 0
Description The decimal representation of these 8 bits correspond to how many 290ms the watchdog timer will wait before it goes to alarm mode and reset the frequency to the safe setting. Default at power up is 16X 290ms = 4.64 seconds.
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 0 0 0 1 0 0 0 0
Description 0=Hw/B0 freq / 1=B11 & 12 freq WD Enable 0=disable / 1=enable WD Status 0=normal / 1=alarm WD Safe Frequency, Byte 0 bit 2 WD Safe Frequency, FS3 WD Safe Frequency, FS2 WD Safe Frequency, FS1 WD Safe Frequency, FS0
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PW D X X X X X X X X
Description VCO Divider Bit0 REF Divider Bit6 REF Divider Bit5 REF Divider Bit4 REF Divider Bit3 REF Divider Bit2 REF Divider Bit1 REF Divider Bit0
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description VCO Divider Bit8 VCO Divider Bit7 VCO Divider Bit6 VCO Divider Bit5 VCO Divider Bit4 VCO Divider Bit3 VCO Divider Bit2 VCO Divider Bit1
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ICS94235
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description Spread Spectrum Bit7 Spread Spectrum Bit6 Spread Spectrum Bit5 Spread Spectrum Bit4 Spread Spectrum Bit3 Spread Spectrum Bit2 Spread Spectrum Bit1 Spread Spectrum Bit0
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description Reserved Reserved Reserved Spread Spectrum Bit12 Spread Spectrum Bit11 Spread Spectrum Bit10 Spread Spectrum Bi 9 Spread Spectrum Bit8
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 0 0 0 0 0 0 0 0
Description CPUCLKT/C0 Skew Control CPUCLKT1 SDRAM0 Skew Control SDRAM (12:1) Skew Control
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD Description 0 1 PCICLK (5:0, F) Skew Control 0 0 0 1 AGP (1:0) Skew Control 0 0
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 1 0 1 0 1 0 1 0
Description CPUCLKT/C0 Slew Rate Control CPUCLKT1 Slew Rate Control PCICLK_F Slew Rate Control PCICLK (5:0) Slew Rate Control
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 1 0 1 0 1 0 1 0
Description SDRAM0 Skew Control SDRAM (12:1) Skew Control AGP (1:0) Slew Rate Control 48MHz Slew Rate Control
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ICS94235
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
VCO Frequency ...................... 150MHz to 500MHz VCO Divider Range ................ 8 to 519 REF Divider Range ................. 2 to 129 Phase Detector Stability .......... 0.3536 to 1.4142
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ICS94235
Absolute Maximum Ratings
Electrical Characteristics - Input/Supply/Common Ouput Parameters.
TA = 0 - 70 C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Input High Voltage VIH Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current VIL IIH IIL1 IIL2 IDD3.3OP66 IDD3.3OP100 IDD3.3OP133 Power Down Input frequency Input Capacitance1 PD Fi CIN CINX Clk Stabilization1 TSTAB tAGP-PCI Skew1 tCPU-SDRAM tCPU-PCI
1Guaranteed by design, not 100% tested in production.
MIN 2 VSS-0.3
TYP
MAX VDD+0.3 0.8 5
UNITS V V uA uA uA
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; Select @ 66MHz CL = 0 pF; Select @ 66MHz CL = 0 pF; Select @ 133MHz VDD = 3.3 V; Logic Inputs X1 & X2 pins From VDD = 3.3 V to 1% target Freq. 300 VT = 50% 200 2.67 27 12 14.318 -5 -200
180
mA
600 16 5 45 3 750 350 3
uA MHz pF pF ms
ps ns
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ICS94235
Electrical Characteristics - CPUCLK (Open Drain)
TA = 0 - 70 C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated). PARAMETER SYMBOL CONDITIONS Output Impedance Output High Voltage Output Low Voltage Output Low Current Rise Time1 Fall Time1 Differential Voltage- AC1 Differential Voltage-DC1 Differential Crossover Voltage1 Duty Cycle1 Skew1 Jitter, Cycle-to-cycle1 Jitter, Absolute1 ZO VOH2B VOL2B IOL2B tr2B tf 2B VDIF VDIF VX dt2B tsk2B tjcyc-cyc2B tjabs2B VO = VX Termination to Vpull-up(external) Termination to Vpull-up(external) VOL = 0.3V VOL = 0.3V, VOH = 1.2 V VOH = 1.2 V, VOL = 0.3 V
Note 2
MIN
TYP
MAX
UNITS Ohms
1
1.2 0.4
V V mA ns ns V V mV % ps ps ps
18 0.9 0.913 0.4 0.2 550 45 53 0.9 Vpullup(external) 0.6 Vpullup(external) 0.6 1100 55 250 201 -250 250 250
Note 2
Note 3
VT = 50% VT = 50% VT = VX VT = 50%
Notes: 1 - Guaranteed by design, not 100% tested in production. - VDIF specifies the minimum input differential voltages (VTR-VCP) required for switching, where VTR is the TRUE input level and VCP is the "complement" input level. 3 - Vpullup(external) = 1.5V, Min = Vpullup(external)/2-150mV; Max = (Vpullup(external)/2)+150mV.
2
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ICS94235
Electrical Characteristics - PCICLK
TA = 0 - 70 C VDD = 3.3V +/-5%; C = 30pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Output High Voltage VOH1 IOH = -11 mA Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time1 Duty Cycle1 Skew1 VOL1 IOH1 IOL1 tr 1 tf1 dt1 Tsk1 IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5V VT = 1.5V 45 19 1.63 1.63 51.9 170 2 2 55 500 MIN 2.6 TYP MAX 0.4 -16 UNITS V V mA mA ns ns % ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK_F
TA = 0 - 70 C; VDD = 3.3V +/-5%; CL = 20 pF (unless otherwise stated). PARAMETER SYMBOL CONDITIONS Output High Voltage VOH1 IOH = -11 mA Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time1 Duty Cycle1 Skew1(window)
1Guaranteed
MIN 2.6
TYP
MAX 0.4 -12
UNITS V V mA mA ns ns % ps
VOL1 IOH1 IOL1 tr1 tf1 dt1 Tsk1
IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH =2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 50% VT = 50% 45 12 1.63 1.63 49.7 170
2 2 55 500
by design, not 100% tested in production.
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ICS94235
Electrical Characteristics - 48MHz, REF0
TA = 0 - 70 C; VDD = 3.3V +/-5%, VDDL = 2.5 V +/-5%; CL = 20pF (otherwise stated). PARAMETER SYMBOL CONDITIONS MIN TYP Output High Voltage VOH5 IOH = -16 mA 2.4 Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time1 Duty Cycle1 Jitter, One Sigma1 Jitter, Absolute1 VOL5 IOH5 IOL5 tr 5 tf 5 dt5 tj1s5 tjabs5 IOL = 9 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V 45 -1 16 1.23 1.21 53 595 2 2 55 0.5 1 MAX 0.4 -22 UNITS V V mA mA ns ns % ns ns
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM (12:0)
TA = 0 - 70 C; VDD = 3.3 V +/-5%, CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Output High Voltage VOH3 IOH = -11 mA Output Low Voltage VOL3 IOL = 11 mA Output High Current Output Low Current Rise Time1 Fall Time1 Duty Cycle1 Skew1(window) IOH3 IOL3 Tr3 Tf3 Dt3 Tsk1 VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 50% VT = 50% 45 12 0.88 0.8 51.2 205 2.2 2.2 55 250 MIN 2 TYP MAX 0.4 -12 UNITS V V mA mA ns ns % ps
1Guarenteed by design, not 100% tested in production.
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ICS94235
Shared Pin Operation Input/Output Pins
Programming Header Via to Gnd Device Pad 2K
Via to VDD
8.2K Clock trace to load Series Term. Res.
Fig. 1
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ICS94235
PD# Timing Diagram
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ICS94235
PCI_STOP# Timing Diagram
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ICS94235
c
SYMBOL
In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX 2.413 0.203 0.203 2.794 0.406 0.343 .095 .008 .008 .110 .016 .0135
L
A A1 b c D E
E1 INDEX AREA
E
0.127 0.254 SEE VARIATIONS 10.033 7.391 0.381 10.668 7.595 0.635
.005 .010 SEE VARIATIONS .395 .291 .015 .420 .299 .025
12 h x 45 D
E1 e h L N
0.635 BASIC 0.508 1.016 SEE VARIATIONS 0 8
0.025 BASIC .020 .040 SEE VARIATIONS 0 8
A A1
-Cb SEATING PLANE
VARIATIONS N 48 D mm. MIN 15.748 MAX 16.002 MIN .620
JEDEC MO-118 DOC# 10-0034
D (inch) MAX .630
6/1/00 REV B
Ordering Information
ICS94235YFT ICS XXXX y F - T
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ICS94235
SYMBOL
In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX 0.05 0.80 0.17 1.20 0.15 1.05 0.27 .002 .032 .007 .047 .006 .041 .011
A A1 A2 b c D E E1 e L N aaa VARIATIONS N 48
0.09 0.20 SEE VARIATIONS 8.10 BASIC 6.00 6.20
.0035 .008 SEE VARIATIONS 0.319 .236 .244 0.020 BASIC .018 .30 SEE VARIATIONS 0 8 .004
0.50 BASIC 0.45 0.75 SEE VARIATIONS 0 8 0.10
D mm. MIN 12.40 MAX 12.60 MIN .488
D (inch) MAX .496
7/6/00 Rev B
MO-153 JEDEC Doc.# 10-0039
Ordering Information
ICS94235yGT ICS XXXX y G - T
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