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0.5C Accurate Digital Temperature Sensor and Quad Voltage Output 12-/10-/8-Bit DACs ADT7316/ADT7317/ADT7318
FEATURES
ADT7316--four 12-Bit DACs ADT7317--four 10-Bit DACs ADT7318--four 8-Bit DACs Buffered voltage output Guaranteed monotonic by design over all codes 10-bit temperature-to-digital converter Temperature range: -40C to +120C Temperature sensor accuracy of 0.5C Supply range: 2.7 V to 5.5 V DAC output range: 0 V to 2 VREF Power-down current 1 A Internal 2.28 VREF option Double-buffered input logic Buffered/unbuffered reference input option Power-on reset to 0 V Simultaneous update of outputs (LDAC function) On-chip rail-to-rail output buffer amplifier I2C(R), SMBus, SPI(R), QSPITM, MICROWIRETM, and DSP compatible 4-wire serial interface SMBus packet error checking (PEC) compatible 16-lead QSOP package
APPLICATIONS
Portable battery-powered instruments Personal computers Telecommunications systems Electronic test equipment Domestic appliances Process control
PIN CONFIGURATION
VOUT-B 1 VOUT-A 2 VREF-AB 3 CS 4 GND 5
16 VOUT-C
ADT7316/ ADT7317/ ADT7318
15 VOUT-D 14 VREF-CD 13 SCL/SCLK
TOP VIEW 12 SDA/DIN (Not to Scale) VDD 6 11 DOUT/ADD D+ 7 D- 8
10 INT/INT 9
LDAC
Figure 1.
GENERAL DESCRIPTION
The ADT7316/ADT7317/ADT73181 combine a 10-bit temperature-to-digital converter and a quad 12-/10-/8-bit DAC, respectively, in a 16-lead QSOP package. This includes a band gap temperature sensor and a 10-bit ADC to monitor and digitize the temperature reading to a resolution of 0.25C. The ADT7316/ADT7317/ADT7318 operate from a single 2.7 V to 5.5 V supply. The output voltage of the DAC ranges from 0 V to 2 VREF, with an output voltage settling time of typ 7 ms. The ADT7316/ADT7317/ADT7318 provide two serial interface options, a 4-wire serial interface that is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards, and a 2-wire SMBus/I2C interface. They feature a standby mode that is controlled via the serial interface. The reference for the four DACs is derived either internally or from two reference pins (one per DAC pair). The outputs of all DACs may be updated simultaneously using the software LDAC function or external LDAC pin. The ADT7316/ADT7317/ ADT7318 incorporate a power-on-reset circuit that ensures the DAC output powers up to 0 V and remains there until a valid write takes place. The ADT7316/ADT7317/ADT7318's wide supply voltage range, low supply current, and SPI/I2C compatible interface make them ideal for a variety of applications, including personal computers, office equipment, and domestic appliances.
1
Protected by the following U.S. patent numbers: 5,764,174; 5,867,012; 6,097,239; 6,169,442. Other patents pending.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
02661-A-006
ADT7316/ADT7317/ADT7318 TABLE OF CONTENTS
Specifications..................................................................................... 3 Functional Block Diagram .............................................................. 7 DAC AC Characteristics.................................................................. 8 Absolute Maximum Ratings............................................................ 9 ESD Caution.................................................................................. 9 Pin Configuration and Function Descriptions........................... 10 Terminology .................................................................................... 11 Typical Performance Characteristics ........................................... 13 Theory of Operation ...................................................................... 18 Power-Up Calibration................................................................ 18 Conversion Speed....................................................................... 18 Functional Description--Voltage Output ................................... 19 Digital-to-Analog Converters................................................... 19 Digital-to-Analog Section ......................................................... 19 Resistor String ............................................................................. 19 DAC External Reference Inputs ............................................... 19 Output Amplifier........................................................................ 20 Thermal Voltage Output............................................................ 20 Functional Description--Measurement...................................... 22 Temperature Sensor ................................................................... 22 VDD Monitoring .......................................................................... 22 On-Chip Reference .................................................................... 23 Round Robin Measurement...................................................... 23 Single-Channel Measurement .................................................. 23 Temperature Measurement Method ........................................ 23 Temperature Value Format ....................................................... 24 Interrupts..................................................................................... 25 Registers........................................................................................... 26 Serial Interface ................................................................................ 34 Serial Interface Selection ........................................................... 34 I2C Serial Interface ..................................................................... 34 SPI Serial Interface ..................................................................... 35 Layout Considerations................................................................... 39 Outline Dimensions ....................................................................... 40 Ordering Guide .......................................................................... 40
REVISION HISTORY
6/04--Data Sheet Changed from Rev. 0 to Rev. A Updated Format...................................................................... Universal Internal VREF Value Change ................................................... Universal Change to Equation in Thermal Voltage Output Section ..............21 Changes to Outline Dimensions........................................................40 8/03--Initial Version: Rev.0
Rev. A | Page 2 of 40
ADT7316/ADT7317/ADT7318 SPECIFICATIONS
Table 1. Temperature ranges are as follows: A Version: -40C to +120C. VDD = 2.7 V to 5.5 V, GND = 0 V, REFIN = 2.25 V, unless otherwise noted.
Parameter1 DAC DC PERFORMANCE2,3 ADT7318 Resolution Relative Accuracy Differential Nonlinearity ADT7317 Resolution Relative Accuracy Differential Nonlinearity ADT7316 Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error Lower Dead Band Upper Dead Band Offset Error Drift Gain Error Drift DC Power Supply Rejection Ratio DC Crosstalk THERMAL CHARACTERISTICS INTERNAL TEMPERATURE SENSOR Accuracy at VDD = 3.3 V 10% Min Typ Max Unit Conditions/Comments
8 0.15 0.02 10 0.5 0.05 12 2 0.02 0.4 0.4 20 60 -12 -5 -60 200
1 0.25
Bits LSB LSB Bits LSB LSB Bits LSB LSB % of FSR % of FSR mV mV ppm of FSR/C ppm of FSR/C dB V
Guaranteed monotonic over all codes.
4 0.5
Guaranteed monotonic over all codes.
16 0.9 2 2 65 100
Guaranteed monotonic over all codes.
Lower dead band exists only if offset error is negative. See Figure 2. Upper dead band exists if VREF = VDD and offset plus gain error is positive. See Figure 3.
VDD = 10%. See Figure 6. Internal reference used. Averaging on. TA = 85C. TA = 0C to +85C. TA = -40C to +120C. TA = 0C to +85C. TA = -40C to +120C. Equivalent to 0.25C. Drift over 10 years if part is operated at 55C. External Transistor = 2N3906. TA = 85C. TA = 0C to +85C. TA = -40C to +120C. TA = 0C to +85C. TA = -40C to +120C. Equivalent to 0.25C. High level. Low level.
Accuracy at VDD = 5 V 5% Resolution Long Term Drift EXTERNAL TEMPERATURE SENSOR Accuracy at VDD = 3.3 V 10%
0.5 2 2 3 0.25
1.5 3 5 3 5 10
C C C C C Bits C C C C C C Bits A A
Accuracy at VDD = 5 V 5% Resolution Output Source Current Thermal Voltage Output 8-Bit DAC Output Resolution Scale Factor
2 3 180 11
1.5 3 5 3 5 10
1 8.79 17.58
C mV/C mV/C
0 V to VREF Output. TA = -40C to +120C. 0 V to 2 VREF Output. TA = -40C to +120C.
1 2
See Terminology. DC specifications tested with the outputs unloaded. 3 Linearity is tested using a reduced code range: ADT7316 (code 115 to 4095); ADT7317 (code 28 to 1023); ADT7318 (code 8 to 255). Rev. A | Page 3 of 40
ADT7316/ADT7317/ADT7318
Parameter1 10-Bit DAC Output Resolution Scale Factor CONVERSION TIMES Slow ADC VDD Internal Temperature External Temperature Fast ADC VDD Internal Temperature External Temperature ROUND ROBIN UPDATE RATE4 Slow ADC at 25C Averaging On Averaging Off Fast ADC at 25C Averaging On Averaging Off DAC EXTERNAL REFERENCE INPUT5 VREF Input Range VREF Input Range VREF Input Impedance Min 0.25 2.2 4.39 Typ Max Unit C mV/C mV/C Conditions/Comments
0 V to VREF Output. TA = -40C to +120C. 0 V to 2 VREF Output. TA= -40C to +120C. Single Channel Mode. Averaging (16 samples) on. Averaging off. Averaging (16 samples) on. Averaging off. Averaging (16 samples) on Averaging off. Averaging (16 samples) on. Averaging off. Averaging (16 samples) on. Averaging off. Averaging (16 samples) on. Averaging off. Time to complete one measurement cycle through all channels.
11.4 712 11.4 712 24.22 1.51 712 44.5 2.14 134 14.25 890
ms s ms s ms ms s s ms s ms s
59.95 6.52 19.59 2.89 1 0.25 37 74 VDD VDD 45 90 >10 -90 -75 2.28 80 0.001 0.5 25 16 2.5 5 VDD to 0.001
ms ms ms ms V V k k M dB dB V ppm/C V mA mA s s This is a measure of the minimum and maximum drive capability of the output amplifier. VDD = 5 V. VDD = 3 V. Coming out of power-down mode. VDD = 5 V. Coming out of power-down mode. VDD = 3.3 V. Buffered reference mode. Unbuffered reference mode. Unbuffered reference mode. 0 V to 2 VREF output range. Unbuffered reference mode. 0 V to VREF output range. Buffered reference mode and power-down mode. Frequency = 10 kHz. Frequency = 10 kHz.
Reference Feedthrough Channel-to-Channel Isolation ON-CHIP REFERENCE Reference Voltage5 Temperature Coefficient5 OUTPUT CHARACTERISTICS5 Output Voltage6 DC Output Impedance Short Circuit Current Power-Up Time
4 5
Round robin is the continuous sequential measurement of the following three channels: VDD, internal temperature, and external temperature. Guaranteed by design and characterization, but not production tested. 6 In order for the amplifier output to reach its minimum voltage, the offset error must be negative. In order for the amplifier output to reach its maximum voltage, VREF = VDD, offset plus gain error must be positive. Rev. A | Page 4 of 40
ADT7316/ADT7317/ADT7318
Parameter1 DIGITAL INPUTS5 Input Current Input Low Voltage, VIL Input High Voltage, VIH Pin Capacitance SCL, SDA Glitch Rejection LDAC Pulse Width DIGITAL OUTPUT Output High Voltage, VOH Output Low Voltage, VOL Output High Current, IOH Output Capacitance, COUT INT/INT Output Saturation Voltage I2C TIMING CHARACTERISTICS7,8 Serial Clock Period, t1 Data In Setup Time to SCL High, t2 Data Out Stable after SCL Low, t3 SDA Low Setup Time to SCL Low (Start Condition), t4 SDA High Hold Time after SCL High (Stop Condition), t5 SDA and SCL Fall Time, t6 SPI TIMING CHARACTERISTICS9,10 CS to SCLK Setup Time, t1 SCLK High Pulse Width, t2 SCLK Low Pulse, t3 Data Access Time after SCLK Falling Edge, t411 Data Setup Time Prior to SCLK Rising Edge, t5 Data Hold Time after SCLK Rising Edge, t6 CSto SCLK Hold Time, t7 CSto DOUT High Impedance, t8 POWER REQUIREMENTS VDD VDD Settling Time IDD (Normal Mode)12 IDD(Power Down Mode) Power Dissipation Min Typ Max 1 0.8 1.89 3 20 2.4 0.4 1 50 0.8 2.5 50 0 50 50 90 0 50 50 35 20 0 0 40 2.7 5.5 50 3 3 10 10 10 33 10 50 Unit A V V pF ns ns V V mA pF V s ns ns ns ns ns ns ns ns ns ns ns ns ns V ms mA mA A A mW W Conditions/Comments VIN = 0 V to VDD.
All digital inputs. Input filtering suppresses noise spikes of less than 50 ns. Edge triggered input. ISOURCE = ISINK = 200 A. IOL = 3 mA. VOH = 5 V. IOUT = 4 mA. Fast-mode I2C. See Figure 4. See Figure 4. See Figure 4. See Figure 4. See Figure 4. See Figure 7. See Figure 7. See Figure 7. See Figure 7. See Figure 7. See Figure 7. See Figure 7. See Figure 7.
2.2
VDD settles to within 10% of its final voltage level. VDD = 3.3 V, VIH = VDD and VIL = GND. VDD = 5 V, VIH = VDD and VIL = GND. VDD = 3.3 V, VIH = VDD and VIL = GND. VDD = 5 V, VIH = VDD and VIL = GND. VDD = 3.3 V. Using Normal Mode. VDD = 3.3 V. Using Shutdown Mode.
The SDA and SCL timing is measured with the input filters turned on so as to meet the fast-mode I2C specification. Switching off the input filters improves the transfer rate but has a negative effect on the EMC behavior of the part. 8 Guaranteed by design. Not tested in production. 9 Guaranteed by design and characterization, but not production tested. 10 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. 11 Measured with the load circuit of Figure 5. 12 IDD specification is valid for all DAC codes. Interface inactive. All DACs active. Load currents excluded.
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Rev. A | Page 5 of 40
ADT7316/ADT7317/ADT7318
GAIN ERROR + OFFSET ERROR
t1
SCL
t4
OUTPUT VOLTAGE
t2
t5
SDA DATA IN
t3
SDA DATA OUT
02661-A-002
t6
NEGATIVE OFFSET ERROR DAC CODE ACTUAL IDEAL
Figure 4. I2C Bus Timing Diagram
LOWER DEADBAND CODES AMPLIFIER FOOTROOM
TO OUTPUT PIN
200A
IOL
1.6V CL 50pF 200A IOH
02661-A-004
02661-A-007
NEGATIVE OFFSET ERROR
Figure 5. Load Circuit for Access Time and Bus Relinquish Time
Figure 2. DAC Transfer Function with Negative Offset
GAIN ERROR + OFFSET ERROR UPPER DEADBAND CODES
VDD 4.7k
02661-A-005
02661-A-003
OUTPUT VOLTAGE
TO DAC OUTPUT 4.7k 200pF
ACTUAL IDEAL
02661-A-008
Figure 6. Load Circuit for DAC Outputs
POSITIVE OFFSET ERROR DAC CODE FULL SCALE
Figure 3. DAC Transfer Function with Positive Offset (VREF = VDD)
CS
t1
SCLK
t2
t7
t3
DIN D7 D6 D5 D4 D3
t5
D2
t6
D1 D0 X X X X X X X
t8
X
t4
DOUT X X X X X X X X D7 D6 D5 D4 D3 D2 D1 D0
Figure 7. SPI Bus Timing Diagram
Rev. A | Page 6 of 40
ADT7316/ADT7317/ADT7318 FUNCTIONAL BLOCK DIAGRAM
ON-CHIP TEMPERATURE SENSOR D+ D- INTERNAL TEMPERATURE VALUE REGISTER ADDRESS POINTER REGISTER THIGH LIMIT REGISTERS DAC A REGISTERS STRING DAC A 2 VOUT-A
DIGITAL MUX
DIGITAL MUX
7 8
ANALOG MUX
A-TO-D CONVERTER
VDD VALUE REGISTER
LIMIT COMPARATOR
TLOW LIMIT REGISTERS VDD LIMIT REGISTERS CONTROL CONFIG. 1 REGISTER CONTROL CONFIG. 2 REGISTER CONTROL CONFIG. 3 REGISTER
DAC B REGISTERS
STRING DAC B
1
VOUT-B
VDD SENSOR
EXTERNAL TEMPERATURE VALUE REGISTER
DAC C REGISTERS
STRING DAC C
16 VOUT-C
DAC D REGISTERS
STRING DAC D
15 VOUT-D
ADT7316/ ADT7317/ ADT7318
STATUS REGISTERS
DAC CONFIGURATION REGISTER LDAC CONFIGURATION REGISTER INTERRUPT MASK REGISTERS
GAIN SELECT LOGIC
POWERDOWN LOGIC
10 INT/INT
SMBus/SPI INTERFACE
6 VDD 5 GND 4 13 12 11 9 LDAC 3 VREF-AB
INTERNAL REFERENCE 14 VREF-CD
CS SCL/SCLK
SDA/DIN DOUT/ADD
Figure 8.
Rev. A | Page 7 of 40
02661-A-001
ADT7316/ADT7317/ADT7318 DAC AC CHARACTERISTICS
Table 2. Guaranteed by design and characterization, but not production tested. VDD = 2.7 V to 5.5 V; RL = 4.7 k to GND; CL = 200 pF to GND; 4.7 k to VDD. All specifications TMIN to TMAX, unless otherwise noted.
Parameter1 Output Voltage Settling Time ADT7318 ADT7317 ADT7316 Slew Rate Major-Code Change Glitch Energy Digital Feedthrough Digital Crosstalk Analog Crosstalk DAC-to-DAC Crosstalk Multiplying Bandwidth Total Harmonic Distortion Min Typ (@ 25C) 6 7 8 0.7 12 0.5 1 0.5 3 200 -70 Max 8 9 10 Unit s s s V/s nV-s nV-s nV-s nV-s kHz dB Conditions and Comments VREF = VDD = +5 V 1/4 scale to 3/4 scale change (0x40 to 0xC0). 1/4 scale to 3/4 scale change (0x100 to 0x300). 1/4 scale to 3/4 scale change (0x400 to 0xC00). 1 LSB change around major carry.
VREF = 2 V 0.1 V p-p. VREF = 2.5 V 0.1 V p-p. Frequency = 10 kHz.
1
See Terminology section.
Rev. A | Page 8 of 40
ADT7316/ADT7317/ADT7318 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter VDD to GND Digital Input Voltage to GND Digital Output Voltage to GND Reference Input Voltage to GND Operating Temperature Range Storage Temperature Range Junction Temperature 16-Lead QSOP Package Power Dissipation1 Thermal Impedance2 JA Junction-to-Ambient JC Junction-to-Case IR Reflow Soldering Peak Temperature Time at Peak Temperature Ramp-Up Rate Ramp-Down Rate Rating -0.3 V to +7 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -40C to +120C -65C to +150C 150C (TJ max - TA)/JA 105.44C/W 38.8C/W 220C (0/5C) 10 sec to 20 sec 2C/sec to 3C/sec -6C/sec
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 4. I2C Address Selection
ADD Pin Low Float High I2C Address 1001 000 1001 010 1001 011
1 2
Values relate to package being used on a 4-layer board. Junction-to-case resistance is applicable to components featuring a preferential flow direction, e.g., components mounted on a heat sink. Junction-to-ambient resistance is more useful for air-cooled PCB-mounted components.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 9 of 40
ADT7316/ADT7317/ADT7318 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VOUT-B 1 VOUT-A 2 VREF-AB 3 CS 4 GND 5
16
VOUT-C VOUT-D VREF-CD SCL/SCLK
ADT7316/ ADT7317/ ADT7318
15 14 13
TOP VIEW 12 SDA/DIN (Not to Scale) VDD 6 11 DOUT/ADD D+ 7 D- 8
10 9
INT/INT LDAC
Figure 9. Pin Configuration QSOP
Table 5. ADT7316/ADT7317/ADT7318 Pin Function Descriptions
Pin No. 1 2 3 Mnemonic VOUT-B VOUT-A VREF-AB Description Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. Reference Input Pin for DACs A and B. It may be configured as a buffered or unbuffered input to both DACs A and B. It has an input range from 0.25 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode. DACs A and B default on power-up to this pin. SPI Active Low Control Input. This is the frame synchronization signal for the input data. When CS goes low, it enables the input register and data is transferred in on the rising edges and out on the falling edges of the subsequent serial clocks. It is recommended that this pin be tied high to VDD when operating the serial interface in I2C mode. Ground Reference Point for All Circuitry on the Part. Analog and digital ground. Positive Supply Voltage, 2.7 V to 5.5 V. The supply should be decoupled to ground. Positive connection to external temperature sensor. Negative connection to external temperature sensor. Active low control input that transfers the contents of the input registers to their respective DAC registers. A falling edge on this pin forces any or all DAC registers to be updated if the input registers have new data. A minimum pulse width of 20 ns must be applied to the LDAC pin to ensure proper loading of a DAC register. This allows simultaneous update of all DAC outputs. Bit C3 of Control Configuration 3 register enables LDAC pin. Default is with LDAC pin controlling the loading of DAC registers. Over Limit Interrupt. The output polarity of this pin can be set to give an active low or active high interrupt when temperature or VDD limits are exceeded. Default is active low. Open-drain output--needs a pull-up resistor. SPI, Serial Data Output. Logic output. Data is clocked out of any register at this pin. Data is clocked out on the falling edge of SCLK. Open-drain output--needs a pull-up resistor. ADD, I2C Serial Bus Address Selection Pin. Logic input. A low on this pin gives the address 1001 000, leaving it floating gives the address 1001 010 and setting it high gives the address 1001 011. The I2C address set up by the ADD pin is not latched by the device until after this address has been sent twice. On the eighth SCL cycle of the second valid communication, the serial bus address is latched in. Any subsequent changes on this pin will have no affect on the I2C serial bus address. SDA, I2C Serial Data Input. I2C serial data that is loaded into the device's registers is provided on this input. Open-drain configuration--needs a pull-up resistor. DIN, SPI Serial Data Input. Serial data to be loaded into the device's registers is provided on this input. Data is clocked into a register on the rising edge of SCLK. Open-drain configuration--needs a pull-up resistor. Serial Clock Input. This is the clock input for the serial port. The serial clock is used to clock data out of any register of the ADT7316/ADT7317/ADT7318 and also to clock data into any register that can be written to. Open-drain configuration--needs a pull-up resistor. Reference Input Pin for DACs C and D. It may be configured as a buffered or unbuffered input to both DACs C and D. It has an input range from 0.25 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode. DACs C and D default on power-up, to this pin. Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
4
CS
5 6 7 8 9
GND VDD D+ D- LDAC
10 11
INT/INT DOUT/ADD
12
SDA/DIN
13
SCL/SCLK
14
VREF -CD
15 16
VOUT -D VOUT -C
Rev. A | Page 10 of 40
02661-A-006
ADT7316/ADT7317/ADT7318 TERMINOLOGY
Relative Accuracy Relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. Typical INL versus code plots can be seen in Figure 10, Figure 11, and Figure 12. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 0.9 LSB maximum ensures monotonicity. Typical DAC DNL versus code plots can be seen in Figure 13, Figure 14, and Figure 15. Offset Error This is a measure of the offset error of the DAC and the output amplifier. (See Figure 2 and Figure 3.) It can be negative or positive. It is expressed as a percentage of the full-scale range. Gain Error This is a measure of the span error of the DAC. It is the deviation in slope of the actual DAC transfer characteristic from the ideal expressed as a percentage of the full-scale range. Offset Error Drift This is a measure of the change in offset error with changes in temperature. It is expressed in ppm of full-scale range/C. Gain Error Drift This is a measure of the change in gain error with changes in temperature. It is expressed in ppm of full-scale range/C. Long Term Temperature Drift This is a measure of the change in temperature error with the passage of time. It is expressed in degrees Celsius. The concept of long term stability has been used for many years to describe by what amount an IC's parameter would shift during its lifetime. This is a concept that has been typically applied to both voltage references and monolithic temperature sensors. Unfortunately, integrated circuits cannot be evaluated at room temperature (25C) for 10 years or so to determine this shift. As a result, manufacturers very typically perform accelerated lifetime testing of integrated circuits by operating ICs at elevated temperatures (between 125C and 150C) over a shorter period of time (typically between 500 and 1000 hours). As a result of this operation, the lifetime of an integrated circuit is significantly accelerated due to the increase in rates of reaction within the semiconductor material. DC Power Supply Rejection Ratio (PSRR) This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. It is measured in decibels. VREF is held at 2 V and VDD is varied 10%. DC Crosstalk This is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC while monitoring another DAC. It is expressed in V. Reference Feedthrough This is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated (i.e., LDAC is high). It is expressed in decibels. Channel-to-Channel Isolation This is the ratio of the amplitude of the signal at the output of one DAC to a sine wave on the reference input of another DAC. It is measured in decibels. Major-Code Transition Glitch Energy Major-code transition glitch energy is the energy of the impulse injected into the analog output when the code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s and is measured when the digital code is changed by 1 LSB at the major carry transition (011...11 to 100...00 or 100...00 to 011...11). Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of a DAC from the digital input pins of the device but is measured when the DAC is not being written to. It is specified in nV-s and is measured with a full-scale change on the digital input pins, i.e., from all 0s to all 1s or vice versa. Digital Crosstalk This is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is measured in standalone mode and is expressed in nV-s. Analog Crosstalk This is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa) while keeping LDAC high. Pulse LDAC low and monitor the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nV-s.
Rev. A | Page 11 of 40
ADT7316/ADT7317/ADT7318
DAC-to-DAC Crosstalk This is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) with LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nV-s. Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. Total Harmonic Distortion This is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measure of the harmonics present on the DAC output. It is measured in decibels. Round Robin This term is used to describe the ADT7316/ADT7317/ ADT7318 cycling through the available measurement channels in sequence, taking a measurement on each channel. DAC Output Settling Time This is the time required, following a prescribed data change, for the output of a DAC to reach and remain within 0.5 LSB of the final value. A typical prescribed change is from 1/4 scale to 3/4 scale.
Rev. A | Page 12 of 40
ADT7316/ADT7317/ADT7318 TYPICAL PERFORMANCE CHARACTERISTICS
0.20 0.15 0.10
0.04 0.10 0.08 0.06
0.05 0 -0.05 -0.10
DNL ERROR (LSB)
02661-A-009
INL ERROR (LSB)
0.02 0 -0.02 -0.04 -0.06
-0.15 -0.20
-0.08 -0.10 0 50 100 150 DAC CODE 200 250
0
50
100
150 DAC CODE
200
250
Figure 10. ADT7318 Typical INL Plot
Figure 13. ADT7318 Typical DNL Plot
0.6
0.3
0.4
0.2
DNL ERROR (LSB)
INL ERROR (LSB)
0.2
0.1
0
0
-0.2
-0.1
02661-A-010
-0.6
-0.3
0
200
400 600 DAC CODE
800
1000
0
200
400 600 DAC CODE
800
1000
Figure 11. ADT7317 Typical INL Plot
Figure 14. ADT7317 Typical DNL Plot
2.5 2.0 1.5
DNL ERROR (LSB)
1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6
02661-A-011
INL ERROR (LSB)
1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 0 500 1000 1500 2000 2500 DAC CODE 3000 3500 4000
-0.8 -1.0 0 500 1000 1500 2000 2500 DAC CODE 3000 3500 4000
Figure 12. ADT7316 Typical INL Plot
Figure 15. ADT7316 Typical DNL Plot
Rev. A | Page 13 of 40
02661-A-014
02661-A-013
-0.4
-0.2
02661-A-012
ADT7316/ADT7317/ADT7318
0.30 0.25 0.20
ERROR (LSB)
ERROR (LSB)
10 OFFSET ERROR 5
INL WCP
0.15 0.10 0.05 0 DNL WCN
02661-A-015
0 VREF = 2.25V -5
DNL WCP
-10
-0.05 -0.10 1.0
INL WCN 1.5 2.0 2.5 3.0 VREF (V) 3.5 4.0 4.5
-20 2.7 3.3 3.6 4.0 VDD (V) 4.5 5.0 5.5
5.0
Figure 16. ADT7318 INL Error and DNL Error vs. VREF
Figure 19. Offset Error and Gain Error vs. VDD
0.14 0.12 0.10 INL WCP
2.505 2.500 SOURCE CURRENT 2.495 INL WCN
0.08
ERROR (LSB)
DAC OUTPUT (V)
0.06 0.04 DNL WCP 0.02 0
2.490 2.485 SINK CURRENT 2.480 2.475
-0.02 -0.04 -0.06 -40 -10
02661-A-016
2.470 2.465 0
20 50 TEMPERATURE (C)
80
110
1
2
3 CURRENT (mA)
4
5
6
Figure 17. ADT7318 INL Error and DNL Error vs. Temperature
Figure 20. VOUT Source and Sink Current Capability
0 -0.2 OFFSET ERROR -0.4 -0.6
ERROR (LSB)
1.98 DAC OUTPUT UNLOADED 1.96
1.94
-0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -40 -20 0 20 40 60 TEMPERATURE (C) 80 100
02661-A-017
ICC (mA)
1.92
1.90
DAC OUTPUT LOADED
1.86
120
0
500
1000
1500
2000 2500 DAC CODE
3000
3500
4000
Figure 18. Offset Error and Gain Error vs. Temperature
Figure 21. Supply Current vs. DAC Code
Rev. A | Page 14 of 40
02661-A-020
GAIN ERROR
1.88
02661-A-019
DNL WCN
VDD = 5V VREF = 5V DAC OUTPUT LOADED TO MIDSCALE
02661-A-018
-15
GAIN ERROR
ADT7316/ADT7317/ADT7318
2.00 ADC OFF, DAC OUTPUTS AT 0V 1.95
1.8 1.6 1.4
ICC (mA)
1.90
DAC OUTPUT (V)
1.2 1.0 0.8 0.6 0.4
1.85
1.80
02661-A-021
0.2 0 0 2 4 TIME (s) 6 8 10
1.75 2.7
3.1
3.5
3.9 4.3 VCC (V)
4.7
5.1
5.5
Figure 22. Supply Current vs. Supply Voltage @25C
Figure 25. Exiting Power-Down to Midscale
7
0.4700 0.4695
6
0.4690
5
DAC OUTPUT (V)
0.4685 0.4680 0.4675 0.4670 0.4665 0.4660
02661-A-022
ICC (A)
4 3
2
02661-A-024
1 0 2.7
0.4655 0.4650 0 2 4 TIME (s) 6 8 10
3.1
3.5
3.9 4.3 VCC (V)
4.7
5.1
5.5
Figure 23. Power-Down Current vs. Supply Voltage @ 25C
Figure 26. ADT7316 Major-Code Transition Glitch Energy--0....11 to 100...00
4.0 3.5 3.0
0.4730 0.4725 0.4720
DAC OUTPUT (V)
DAC OUTPUT (V)
2.5 2.0 1.5 1.0
02661-A-023
0.4715 0.4710 0.4705 0.4700 0.4695 0.4690 0.4685 0 2 4 6 TIME (s) 8 10
02661-A-026
0.5 0
0
2
4 TIME (s)
6
8
10
Figure 24. Half-Scale Settling (1/4 to 3/4 Scale Code Change)
Figure 27. ADT7316 Major-Code Transition Glitch Energy--100...00 to 011...11
Rev. A | Page 15 of 40
02661-A-025
ADT7316/ADT7317/ADT7318
0 VDD = 5V TA = 25C -2 1.5 EXTERNAL TEMPERATURE @ 5V
TEMPERATURE ERROR (C)
1.0
FULL-SCALE ERROR (mV)
INTERNAL TEMPERATURE @ 3.3V
-4
0.5
-6
0
-8
02661-A-027
EXTERNAL TEMPERATURE @ 3.3V INTERNAL TEMPERATURE @ 5V -1.0 -30 0 40 TEMPERATURE (C) 85 120
-12
1
2
3 VREF (V)
4
5
Figure 28. Full-Scale Error vs. VREF
Figure 31. Temperature Error @ 3.3 V and 5 V
2.329 VDD = 5V VREF = 5V DAC OUTPUT LOADED TO MIDSCALE
15 10
TEMPERATURE ERROR (C)
2.328
VDD = 3.3V TEMPERATURE = 25C D+ TO GND
2.327 DAC OUTPUT (V)
5 0 -5
2.326 2.325 2.324
02661-A-028
D+ TO VCC -10 -15 -20 -25 0 10 20 30 40 50 60 70 80 PCB TRACK RESISTANCE (M) 90
02661-A-031
2.323
2.322
0
1
2
3 TIME (s)
4
5
100
Figure 29. DAC-to-DAC Crosstalk
Figure 32. External Temperature Error vs. PCB Track Resistance
0
-10
100mV RIPPLE ON VCC VREF = 2.25V VDD = 3.3V TEMPERATURE = 25C
TEMPERATURE ERROR (C)
0 VDD = 3.3V -10
AC PSRR (dB)
-20
-20
-30
-30
-40
-40
02661-A-029
-50
-60
1
10 FREQUENCY (kHz)
100
-60
0
5
10
15
20 25 30 35 CAPACITANCE (nF)
40
45
50
Figure 30. PSRR vs. Supply Ripple Frequency
Figure 33. External Temperature Error vs. Capacitance Between D+ and D-
Rev. A | Page 16 of 40
02661-A-032
-50
02661-A-030
-10
-0.5
ADT7316/ADT7317/ADT7318
10 8
TEMPERATURE ERROR (C)
140
VDD = 3.3V COMMON-MODE VOLTAGE = 100mV
EXTERNAL TEMPERATURE 120
6
TEMPERATURE (C)
100 INTERNAL TEMPERATURE 80
4 2 0 -2
02661-A-033
60
40
TEMPERATURE OF ENVIRONMENT CHANGED HERE
-4 -6
1
100
200 300 400 NOISE FREQUENCY (Hz)
500
600
0 0 10 20 30 TIME (s) 40 50
60
Figure 34. External Temperature Error vs. Common-Mode Noise Frequency
Figure 37. Temperature Sensor Response to Thermal Shock
70 60
TEMPERATURE ERROR (C)
0
VDD = 3.3V DIFFERENTIAL-MODE VOLTAGE = 100mV
-5
50 40 30 20 10
-20
ATTENUATION (dB)
-10
-15
0 -10
02661-A-034
-25 1 10 100 1k 10k FREQUENCY (Hz) 100k 1M
1
100
200 300 400 NOISE FREQUENCY (MHz)
500
600
10M
Figure 35. External Temperature Error vs. Differential-Mode Noise Frequency
Figure 38. Multiplying Bandwidth (Small-Signal Frequency Response)
0.6 VDD = 3.3V 0.4
TEMPERATURE ERROR (C)
0.2
0
-0.2 250mV
02661-A-035
-0.4
-0.6
1
100
200 300 400 NOISE FREQUENCY (Hz)
500
600
Figure 36. Internal Temperature Error vs. Power Supply Noise Frequency
Rev. A | Page 17 of 40
02661-A-037
02661-A-036
20
ADT7316/ADT7317/ADT7318 THEORY OF OPERATION
Directly after the power-up calibration routine, the ADT7316/ ADT7317/ADT7318 go into idle mode. In this mode, the device is not performing any measurements and is fully powered up. All four DAC outputs are at 0 V. To begin monitoring, write to Control Configuration 1 register (Address = 18h), and set Bit C0 = 1. The ADT7316/ADT7317/ ADT7318 go into their power-up default measurement mode, which is round robin. The device proceeds to take measurements on the VDD channel, the internal temperature sensor channel, and the external temperature sensor channel. Once it finishes taking measurements on the external temperature sensor channel, the device immediately loops back to start taking measurements on the VDD channel and repeats the same cycle as before. This loop continues until the monitoring is stopped by resetting Bit C0 of Control Configuration 1 register to 0. It is also possible to continue monitoring as well as switching to single-channel mode by writing to Control Configuration 2 register (Address = 19h) and setting Bit C4 = 1. Further explanation of the single-channel and round robin measurement modes are given in later sections. All measurement channels have averaging enabled on power-up. Averaging forces the device to take an average of 16 readings before giving a final measured result. To disable averaging and consequently decrease the conversion time by a factor of 16, set C5 = 1 in Control Configuration 2 register. Controlling the DAC outputs can be done by writing to the DAC's MSB and LSB registers (Addresses 10h to 17h). The power-up default setting is to have a low going pulse on the LDAC pin controlling the updating of the DAC outputs from the DAC registers. Alternatively, users can configure the updating of the DAC outputs to be controlled by means other than the LDAC pin by setting C3 = 1 of the Control Configuration 3 register (Address = 1Ah). The DAC Configuration register (Address = 1Bh), and the LDAC Configuration register (Address = 1Ch) can now be used to control the DAC updating. These two registers also control the output range of the DACs, enabling or disabling the external reference buffer, and selecting between the internal or external reference. DAC A and DAC B outputs can be configured to give a voltage output proportional to the temperature of the internal and external temperature sensors, respectively. The dual-serial interface defaults to the I2C protocol on powerup. To select and lock in the SPI protocol, follow the selection process as described in the Serial Interface Selection section. The I2C protocol cannot be locked in, while the SPI protocol, when selected, is automatically locked in. The interface can only be switched back to be I2C when the device is powered off and on. When using I2C, the CS pin should be tied to either VDD or GND. There are a number of different operating modes on the ADT7316/ADT7317/ADT7318 devices, and all of them can be controlled by the configuration registers. These features consist of enabling and disabling interrupts, polarity of the INT/INT pin, enabling and disabling the averaging on the measurement channels, SMBus timeout, and software reset.
POWER-UP CALIBRATION
It is recommended that no communication to the part is initiated until approximately 5 ms after VDD has settled to within 10% of its final value. It is generally accepted that most systems take a maximum of 50 ms to power-up. Power-up time is directly related to the amount of decoupling on the voltage supply line. During this 5 ms after VDD has settled, the part is performing a calibration routine, and any communication to the device will interrupt this routine and could cause erroneous temperature measurements. If it is not possible to have VDD at its nominal value by the time 50 ms has elapsed, or that communication to the device has started prior to VDD settling, then it is recommended that a measurement be taken on the VDD channel before a temperature measurement is taken. The VDD measurement is used to calibrate out any temperature measurement error due to different supply voltage values.
CONVERSION SPEED
The internal oscillator circuit used by the ADC has the capability to output two different clock frequencies. This means that the ADC is capable of running at two different speeds when performing a conversion on a measurement channel. Thus the time taken to perform a conversion on a channel can be reduced by setting C0 of Control Configuration 3 register (Address 1Ah). This increases the ADC clock speed from 1.4 kHz to 22 kHz. At the higher clock speed, the analog filters on the D+ and D- input pins (external temperature sensor) are switched off. This is why the power-up default setting is to have the ADC working at the slow speed. The typical times for fast and slow ADC speeds are given in the specification pages. The ADT7316/ADT7317/ADT7318 power up with averaging on. This means every channel is measured 16 times and internally averaged to reduce noise. The conversion time can also be sped up by turning the averaging off by setting Bit C5 of Control Configuration 2 register (Address = 19h) to a 1.
Rev. A | Page 18 of 40
ADT7316/ADT7317/ADT7318 FUNCTIONAL DESCRIPTION--VOLTAGE OUTPUT
DIGITAL-TO-ANALOG CONVERTERS
The ADT7316/ADT7317/ADT7318 have four resistor-string DACs fabricated on a CMOS process, with resolutions of 12, 10, and 8 bits, respectively. They contain four output buffer amplifiers, and are written to via an I2C serial interface or an SPI serial interface. See the Serial Interface Selection section for more information. The ADT7316/ADT7317/ADT7318 operate from a single supply of 2.7 V to 5.5 V, and the output buffer amplifiers provide rail-to-rail output swing with a slew rate of 0.7 V/s. DACs A and B share a common external reference input, namely VREF-AB. DACs C and D share a common external reference input, namely VREF-CD. Each reference input may be buffered to draw virtually no current from the reference source or unbuffered to give a reference input range from GND to VDD. The devices have a power-down mode in which all DACs may be turned off completely with a high impedance output. Each DAC output will not be updated until it receives the LDAC command. Therefore, while the DAC registers would have been written to with a new value, this value will not be represented by a voltage output until the DACs have received the LDAC command. Reading back from any DAC register prior to issuing an LDAC command will result in the digital value that corresponds to the DAC output voltage. Therefore, the digital value written to the DAC register cannot be read back until after the LDAC command has been initiated. This LDAC command can be given by either pulling the LDAC pin low (falling edge loads DACs), setting up Bits D4 and D5 of DAC Configuration register (Address = 1Bh), or using the LDAC register (Address = 1Ch). When using the LDAC pin to control DAC register loading, the low going pulse width should be 20 ns minimum. The LDAC pin has to go high and low again before the DAC registers can be reloaded.
VREF-AB
DIGITAL-TO-ANALOG SECTION
The architecture of a DAC channel consists of a resistor string DAC followed by an output buffer amplifier. The voltage at the VREF pin or the on-chip reference of 2.28 V provides the reference voltage for the corresponding DAC. Figure 39 shows a block diagram of the DAC architecture. Since the input coding to the DAC is straight binary, the ideal output voltage is given by
VOUT = V REF x D 2N
where: D = the decimal equivalent of the binary code that is loaded to the DAC register: 0-255 for ADT7318 (8 bits) 0-1023 for ADT7317 (10 bits) 0-4095 for ADT7316 (12 bits) N = the DAC resolution
RESISTOR STRING
The resistor string section is shown in Figure 40. It is simply a string of resistors, each of value 603 approximately. The digital code loaded to the DAC register determines at what node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic.
R
R TO OUTPUT AMPLIFIER
R
R
02661-A-039
R
BUFFER SELECT SIGNAL
REFERENCE BUFFER
Figure 40. Resistor String
INT VREF
GAIN MODE (GAIN = 1 OR 2)
DAC EXTERNAL REFERENCE INPUTS
There is a reference pin for each pair of DACs. The reference inputs are buffered, but can also be individually configured as unbuffered. The advantage with the buffered input is the high impedance it presents to the voltage source driving it. However, if the unbuffered mode is used, the user can have a reference voltage as low as 0.25 V and as high as VDD, since there is no restriction due to headroom and footroom of the reference amplifier.
INPUT REGISTER
DAC REGISTER
RESISTOR STRING
VOUT-A
02661-A-038
OUTPUT BUFFER AMPLIFIER
Figure 39. Single DAC Channel Architecture
Rev. A | Page 19 of 40
ADT7316/ADT7317/ADT7318
If there is a buffered reference in the circuit, there is no need to use the on-chip buffers. In unbuffered mode, the input impedance is still large at typically 90 k per reference input for 0 V to VREF output mode and 45 k for 0 V to 2 VREF output mode. The buffered/unbuffered option is controlled by the DAC Configuration register (Address 1Bh, see Registers section). The LDAC Configuration register controls the option to select between internal and external voltage references. The default setting is for external reference selected.
VREF-AB
VDD I OPTIONAL CAPACITOR, UP TO 3nF MAX. CAN BE ADDED TO IMPROVE HIGH FREQUENCY NOISE REJECTION IN NOISY ENVIRONMENTS D+ REMOTE SENSING TRANSISTOR (2N3906) C1 D- LOW-PASS FILTER fC = 65kHz BIAS DIODE VOUT+ TO ADC VOUT-
02661-A-041
NxI
IBIAS
Figure 42. Signal Conditioning for External Diode Temperature Sensors
2.25V INTERNAL VREF
STRING DAC A
02661-A-040
STRING DAC B
The default output resolution for the ADT7316 and ADT7317 is 8 bits. To increase this to 10 bits, set C1 = 1 of Control Configuration 3 register. The default output range is 0 V to VREF-AB, and this can be increased to 0 V to 2 VREF-AB. The user can select the internal VREF (VREF = 2.28 V) by setting D4 = 1 in the LDAC Configuration register (Address 1Ch). Increasing the output voltage span to 2 VREF can be done by setting D0 = 1 for DAC A (internal temperature sensor), and D1 = 1 for DAC B (external temperature sensor) in DAC Configuration register (Address 1Bh). The output voltage is capable of tracking a maximum temperature range of -128C to +127C, but the default setting is -40C to +127C. If the output voltage range is 0 V to VREF-AB (VREF-AB = 2.25 V), then this corresponds to 0 V representing -40C, and 1.48 V representing +127C. This of course will give an upper dead band between 1.48 V and VREF-AB. The internal and external analog temperature offset registers can be used to vary this upper dead band and consequently the temperature that 0 V corresponds to. Table 6 and Table 7 give examples of how this is done using a DAC output voltage span of VREF and 2 VREF, respectively. Simply write in the temperature value, in twos complement format, at which 0 V is to start. For example, if using the DAC A output with 0 V to start at -40C, program D8h into the internal analog temperature offset register (Address 21h). This is an 8-bit register and thus only has a temperature offset resolution of 1C for all device models. Use the following formulas to determine the value to program into the offset registers. Negative temperatures:
Figure 41. DAC Reference Buffer Circuit
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating output voltages to within 1 mV of either rail. Its actual range depends on the value of VREF, gain and offset error. If a gain of 1 is selected (Bits 0-3 of DAC Configuration register = 0), the output range is 0.001 V to VREF. If a gain of 2 is selected (Bits 0-3 of DAC Configuration register = 1), the output range is 0.001 V to 2VREF. Because of clamping, however, the maximum output is limited to VDD - 0.001 V. The output amplifier is capable of driving a load of 4.7 k to VDD or 4.7 k to GND in parallel with 200 pF to GND (see Figure 6). The source and sink capabilities of the output amplifier can be seen in the plot in Figure 20. The slew rate is 0.7 V/s with a half-scale settling time to 0.5 LSB (at 8 bits) of 6 s.
THERMAL VOLTAGE OUTPUT
The ADT7316/ADT7317/ADT7318 are capable of outputting voltages that are proportional to temperature. DAC A output can be configured to represent the temperature of the internal sensor while DAC B output can be configured to represent the external temperature sensor. Bits C5 and C6 of Control Configuration 3 register select the temperature proportional to output voltage. Each time a temperature measurement is taken the DAC output is updated. The output resolution for the ADT7318 is 8 bits with the 1C change corresponding to the one LSB change. The output resolution for the ADT7316 and ADT7317 is capable of 10 bits with a 0.25C change corresponding to the 1 LSB change
Offset Register Code (d ) = (0 V Temp )+ 128
where: D7 of Offset Register Code is set to 1 for negative temperatures. Example: Offset Register Code (d ) = ( -40 ) + 128 = 88d = 58h Since a negative temperature has been input into the equation, DB7 (MSB) of the Offset Register Code is set to a `1'. Therefore, 58h becomes D8h. 58h + DB7 (1) = D8h
Rev. A | Page 20 of 40
ADT7316/ADT7317/ADT7318
Positive temperatures: Table 7. Thermal Voltage Output (0 V to 2 VREF-AB)
O/P Voltage (V) 0 0.25 0.5 0.75 1 1.12 1.47 1.5 2 2.25 2.5 2.75 3 3.25 3.5 3.75 4 4.25 4.5 Default (C) -40 -26 +12 +3 +17 +23 +43 +45 +73 +88 +102 +116 UDB1 UDB1 UDB1 UDB1 UDB1 UDB1 UDB1 Max (C) -128 -114 -100 -85 -71 -65 -45 -43 -15 0 +14 +28 +42 +56 +70 +85 +99 +113 +127 Sample (C) 0 +14 +28 +43 +57 +63 +83 +85 +113 +127 UDB1 UDB1 UDB1 UDB1 UDB1 UDB1 UDB1 UDB1 UDB1
Offset Register Code (d ) = 0 V Temp Example: Offset Register Code (d ) = 10d = 0 Ah The following equation is used to work out the various temperatures for the corresponding 8-bit DAC output: 8 - Bit Temp = (DAC O / P / 1 LSB ) + (0 V Temp ) For example, if the output is 1.5 V, VREF-AB = 2.25 V, 8-bit DAC has an LSB size = 2.25 V/256 = 8.79 x 10-3, and 0 V temp is at -128C, then the resultant temperature is
(1.5 / 8.79 x 10 ) + (- 128) = + 43 o C
-3
The following equation is used to work out the various temperatures for the corresponding 10-bit DAC output 10 - Bit Temp = ((DAC O / P / 1 LSB ) x 0.25) + (0 V Temp ) For example, if the output is 0.4991 V, VREF-AB = 2.25 V, 10-bit DAC has an LSB size = 2.25 V/1024 = 2.197 x 10-3, and 0 V temp is at -40C, then the resultant temperature works out to be
((0.4991 / 2.197 / 10 -3 ) x 0.25) + (- 40) + 16.75 o C
Table 6. Thermal Voltage Output (0 V to VREF-AB)
O/P Voltage (V) 0 0.5 1 1.12 1.47 1.5 2 2.25 Default (C) -40 +17 +73 +87 +127 UDB1 UDB1 UDB1 Max (C) -128 -71 -15 -1 +39 +42 +99 +127 Sample (C) 0 +56 +113 +127 UDB1 UDB1 UDB1 UDB1
Figure 43 shows DAC output versus temperature for a VREF-AB= 2.25 V.
2.25 2.10 1.95 1.80 1.65 1.50 1.35 1.20 1.05 0.90 0.75 0.60 0.45 0.30 0.15 0 -128-110 -90 -70 -50 -30 -10 10 30 50 TEMPERATURE (C) 70
02661-A-042
0V = -128C
DAC OUTPUT (V)
0V = -40C
0V = 0C
90 110 127
Figure 43. 10-DAC Output vs. Temperature, VREF-AB = 2.25 V
1
Upper dead band has been reached. DAC output is not capable of increasing (see Figure 3).
Rev. A | Page 21 of 21
ADT7316/ADT7317/ADT7318 FUNCTIONAL DESCRIPTION--MEASUREMENT
TEMPERATURE SENSOR
The ADT7316/ADT7317/ADT7318 contain an ADC with special input signal conditioning to enable operation with external and on-chip diode temperature sensors. When the ADT7316/ADT7317/ADT7318 are operating in single-channel mode, the ADC continually processes the measurement taken on one channel only. This channel is preselected by Bits C0 and C1 in Control Configuration 2 register (Address 19h). When in round robin mode, the analog input multiplexer sequentially selects the VDD input channel, the on-chip temperature sensor to measure its internal temperature, and the external temperature sensor. These signals are digitized by the ADC and the results stored in the various value registers. The measured results are compared with the internal and external, THIGH and TLOW, limits. These temperature limits are stored in on-chip registers. If the temperature limits are not masked out, any out-of-limit comparisons generate flags that are stored in the Interrupt Status 1 register. One or more out-oflimit results will cause the INT/INT output to pull either high or low depending on the output polarity setting. Theoretically, the temperature measuring circuit can measure temperatures from -128C to +127C with a resolution of 0.25C. Temperatures outside TA, however, are outside the guaranteed operating temperature range of the device. Temperature measurement from -128C to +127C is possible using an external sensor. Temperature measurement is initiated by three methods. The first method is applicable when the part is in single-channel measurement mode. The temperature is measured 16 times and internally averaged to reduce noise. In single-channel mode, the part is continuously monitoring the selected channel, i.e., as soon as one measurement is taken then another one is started on the same channel. The total time to measure a temperature channel with the ADC operating at slow speed is typically 11.4 ms (712 s x 16) for the internal temperature sensor, and 24.22 ms (1.51 ms x 16) for the external temperature sensor. The new temperature value is stored in two 8-bit registers and ready for reading by the I2C or SPI interface. The user has the option of disabling the averaging by setting a bit (Bit 5) in the Control Configuration 2 register (Address 19h). The ADT7316/ ADT7317/ADT7318 default on power-up, with the averaging enabled. The second method is applicable when the part is in round robin measurement mode. The part measures both the internal and external temperature sensors as it cycles through all possible measurement channels. The two temperature channels are measured each time the part runs a round robin sequence. In round robin mode, the part is continuously measuring all channels. Temperature measurement is also initiated after every read or write to the part when the part is in either single-channel measurement mode or round robin measurement mode. Once serial communication has started, any conversion in progress is stopped and the ADC reset. Conversion will start again immediately after the serial communication has finished. The temperature measurement proceeds normally as described above.
VDD MONITORING
The ADT7316/ADT7317/ADT7318 also have the capability of monitoring their own power supplies. The parts measure the voltage on their VDD pin to a resolution of 10 bits. The resultant value is stored in two 8-bit registers, the 2 LSBs stored in Register Address 03h and the 8 MSBs are stored in Register Address 06h. This allows the user to have the option of just doing a one byte read if 10-bit resolution is not important. The measured result is compared with VHIGH and VLOW limits. If the VDD interrupt is not masked out, any out-of-limit comparison generates a flag in Interrupt Status 2 register and one or more out-of-limit results will cause the INT/INT output to pull either high or low depending on the output polarity setting. Measuring the voltage on the VDD pin is regarded as monitoring a channel. Therefore, along with the internal and external temperature sensors, the VDD voltage makes up the third and final monitoring channel. The user can select the VDD channel for single-channel measurement by setting Bit C4 = 1 and setting Bits C0 to C2 to all 0s in Control Configuration 2 register. When measuring the VDD value, the reference for the ADC is sourced from the internal reference. Table 8 shows the data format. As the maximum VDD voltage measurable is 7 V, internal scaling is performed on the VDD voltage to match the 2.28 V internal reference value. Below is an example of how the transfer function works. VDD = 5 V ADC Reference = 2.28 V 1 LSB = ADC Reference/210 = 2.28/1024 = 2.226 mV Scale Factor = Full-Scale VCC/ADC Reference = 7/2.28 = 3.07 Conversion Result = VDD/(Scale Factor x LSB Size) = 5/(3.07 x 2.226 mV ) = 2DBh
Rev. A | Page 22 of 40
ADT7316/ADT7317/ADT7318
Table 8. VDD Data Format, VREF = 2.28 V
VDD Value (V) 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 Digital Output Binary 01 0110 1110 01 1011 0111 10 0000 0000 10 0100 1001 10 1001 0010 10 1101 1100 11 0010 0101 11 0110 1110 11 1011 0111 11 1111 1111
I NxI IBIAS VDD
Hex 16E 1B7 200 249 292 2DC 325 36E 3B7 3FF
VOUT+ TO ADC INTERNAL SENSE TRANSISTOR BIAS DIODE VOUT-
02661-A-043
Figure 44. Top Level Structure of Internal Temperature Sensors
SINGLE-CHANNEL MEASUREMENT
Setting C4 of Control Configuration 2 register enables the single-channel mode and allows the ADT7316/ADT7317/ ADT7318 to focus on one channel only. A channel is selected by writing to Bits C0:C1 in Control Configuration 2 register. For example, to select the VDD channel for monitoring, write to the Control Configuration 2 register and set C4 to 1 (if not done so already), then write all 0s to Bits C0 to C1. All subsequent conversions will be done on the VDD channel only. To change the channel selection to the internal temperature channel, write to the Control Configuration 2 register and set C0 = 1. When measuring in single-channel mode, conversions on the channel selected occur directly after each other. Any communication to the ADT7316/ADT7317/ADT7318 stops the conversions, but they are restarted once the read or write operation is completed.
ON-CHIP REFERENCE
The ADT7316/ADT7317/ADT7318 has an on-chip 1.2 V band gap reference that is gained up by a switched capacitor amplifier to give an output of 2.28 V. The amplifier is powered up for the duration of the device monitoring phase and is powered down once monitoring is disabled. This saves on current consumption. The internal reference is used as the reference for the ADC. The ADC is used for measuring VDD and the internal and external temperature sensors. The internal reference is always used when measuring VDD, and the internal and external temperature sensors. The external reference is the default power-up reference for the DACs.
ROUND ROBIN MEASUREMENT
On power-up, the ADT7316/ADT7317/ADT7318 go into round robin mode, but monitoring is disabled. Setting Bit C0 of Configuration Register 1 to a 1 enables conversions. It sequences through the three channels of VDD, internal temperature sensor, and external temperature sensor and takes a measurement from each. Once the conversion is completed on the external temperature sensor, the device loops around for another measurement cycle on all three channels. This method of taking a measurement on all three channels in one cycle is called round robin. Setting Bit 4 of Control Configuration 2 (Address 19h) disables the round robin mode and in turn sets up the single-channel mode. The single-channel mode is where only one channel, e.g., internal temperature sensor, is measured in each conversion cycle. The time taken to monitor all channels will normally not be of interest, since the most recently measured value can be read at any time. For applications where the round robin time is important, typical times at 25C are given in the specification pages.
TEMPERATURE MEASUREMENT METHOD
Internal Temperature Measurement
The ADT7316/ADT7317/ADT7318 contain an on-chip band gap temperature sensor whose output is digitized by the on-chip ADC. The temperature data is stored in the internal temperature value register. As both positive and negative temperatures can be measured, the temperature data is stored in twos comple-ment format, as shown in Table 9. The thermal characteristics of the measurement sensor could change, and therefore an offset is added to the measured value to enable the transfer function to match the thermal characteristics. This offset is added before the temperature data is stored. The offset value used is stored in the internal temperature offset register.
External Temperature Measurement
The ADT7316/ADT7317/ADT7318 can measure the temperature of one external diode sensor or diode-connected transistor. The forward voltage of a diode or diode-connected transistor, operated at a constant current, exhibits a negative temperature coefficient of about -2 mV/C. Unfortunately, the absolute value of VBE varies from device to device, and individual calibration is required to null this out, so the technique is unsuitable for mass production.
Rev. A | Page 23 of 40
ADT7316/ADT7317/ADT7318
The technique used in the ADT7316/ADT7317/ADT7318 is to measure the change in VBE when the device is operated at two different currents. This is given by V BE = KT/ q x In(N ) where: K is Boltzmann's constant. q is the charge on the carrier. T is the absolute temperature in Kelvin. N is the ratio of the two currents. Figure 42 shows the input signal conditioning used to measure the output of an external temperature sensor. This figure shows the external sensor as a discrete substrate transistor. If a PNP transistor is used, the base is connected to the D- input and the emitter to the D+ input. If an NPN transistor is used, the emitter is connected to the D- input and the base to the D+ input. We recommend that a 2N3906 be used as the external transistor. To prevent ground noise interfering with the measurement, the more negative terminal of the sensor is not referenced to ground, but is biased above ground by an internal diode at the D- input. As the sensor is operating in a noisy environment, C1 is provided as a noise filter. See the section on layout considerations for more information on C1. To measure VBE, the sensor is switched between operating currents of I and N x I. The resulting waveform is passed through a low-pass filter to remove noise, then to a chopper stabilized amplifier that performs the functions of amplification and rectification of the waveform to produce a dc voltage proportional to VBE. This voltage is measured by the ADC to give a temperature output in 10-bit twos complement format. To further reduce the effects of noise, digital filtering is performed by averaging the results of 16 measurement cycles.
TEMPERATURE VALUE FORMAT
One LSB of the ADC corresponds to 0.25C. The ADC can theoretically measure a temperature span of 255C. The internal temperature sensor is guaranteed to a low value limit of -40C. It is possible to measure the full temperature span using the external temperature sensor. The temperature data format is shown in Table 9. The result of the internal or external temperature measurements is stored in the temperature value registers and is compared with limits programmed into the internal or external high and low registers.
Table 9. Temperature Data Format (Internal and External Temperature)
Temperature -40C -25C -10C -0.25C 0C 0.25C 10C 25C 50C 75C 100C 105C 125C Digital Output DB9..........DB0 11 0110 0000 11 1001 1100 11 1101 1000 11 1111 1111 00 0000 0000 00 0000 0001 00 0010 1000 00 0110 0100 00 1100 1000 01 0010 1100 01 1001 0000 01 1010 0100 01 1111 0100
Temperature Conversion Formula: Positive Temperature = ADC Code/4 Negative Temperature = (ADC Code* - 512)/4 *DB9 is removed from the ADC code.
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ADT7316/ADT7317/ADT7318
S/W RESET
INTERRUPT STATUS REGISTER 1 (TEMP AND EXT. DIODE CHECK)
INTERNAL TEMP
STATUS BITS
EXTERNAL TEMP
WATCHDOG LIMIT COMPARISONS
INTERRUPT STATUS REGISTER 2 (VDD)
INTERRUPT MASK REGISTERS
VDD
INT/INT (LATCHED OUTPUT)
DIODE FAULT
STATUS BIT
READ RESET
CONTROL CONFIGURATION REGISTER 1
Figure 45. ADT7316/ADT7317/ADT7318 Interrupt Structure
INTERRUPTS
The measured results from the internal temperature sensor, external temperature sensor, and the VDD pin are compared with the THIGH/VHIGH (greater than comparison) and TLOW/VLOW (less than or equal to comparison) limits. An interrupt occurs if the measurement exceeds or equals the limit registers. These limits are stored in on-chip registers. Note that the limit registers are 8 bits long, while the conversion results are 10 bits long. If the limits are not masked out, then any out-of-limit comparisons generate flags that are stored in Interrupt Status 1 register (Address = 00h) and Interrupt Status 2 register (Address = 01h). One or more out-of-limit results will cause the INT/INT output to pull either high or low depending on the output polarity setting. It is good design practice to mask out interrupts for channels that are of no concern to the application. Figure 45 shows the interrupt structure for the ADT7316/ ADT7317/ ADT7318. It gives a block diagram representation of how the various measurement channels affect the INT/INT pin.
Rev. A | Page 25 of 40
02661-A-044
INT/INT ENABLE BIT
ADT7316/ADT7317/ADT7318 REGISTERS
The ADT7316/ADT7317/ADT7318 contain registers that are used to store the results of external and internal temperature measurements, VDD value measurements, high and low temperature and supply voltage limits. They also set output DAC voltage levels, configure multipurpose pins, and generally control the device. A description of these registers follows. The register map is divided into registers of 8 bits. Each register has its own individual address, but some consist of data that is linked with other registers. These registers hold the 10-bit conversion results of measurements taken on the temperature and VDD channels. For example, the 8 MSBs of the VDD measurement are stored in Register Address 06h, while the 2 LSBs are stored in Register Address 03h. The link involved between these types of registers is that when the LSB register is read first then the MSB registers associated with that LSB register are locked out to prevent any updates. To unlock these MSB registers, the user has only to read any one of them, which will have the effect of unlocking all previously locked out MSB registers. So for the example given above, if Register 03h was read first, then MSB Registers 06h and 07h would be locked out to prevent any updates to them. If Register 06h was read, then this register and Register 07h would be subsequently unlocked.
FIRST READ COMMAND LSB REGISTER OUTPUT DATA
Table 10. List of ADT7316/ADT7317/ADT7318 Registers
RD/WR Address
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h-0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h-4Ch 4Dh 4Eh 4Fh 50h-7Eh 7F 80-FF
Name
Interrupt Status 1 Interrupt Status 2 Reserved Internal Temp and VDD LSBs External Temp LSBs Reserved VDD MSBs Internal Temp MSBs External Temp MSBs Reserved DAC A LSBs (ADT7316/ADT7317 only) DAC A MSBs DAC B LSBs (ADT7316/ADT7317 only) DAC B MSBs DAC C LSBs (ADT7316/ADT7317 only) DAC C MSBs DAC D LSBs (ADT7316/ADT7317 only) DAC D MSBs Control Configuration 1 Control Configuration 2 Control Configuration 3 DAC Configuration LDAC Configuration Interrupt Mask 1 Interrupt Mask 2 Internal Temp Offset External Temp Offset Internal Analog Temp Offset External Analog Temp Offset VDD VHIGH Limit VDD VLOW Limit Internal THIGH Limit Internal TLOW Limit External THIGH Limit External TLOW Limit Reserved Device ID Manufacturer's ID Silicon Revision Reserved SPI Lock Status Reserved
Power-On Default
00h 00h 00h 00h 00h 00h xxh 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h D8h D8h C7h 62h 64h C9h FFh 00h 01h/09h/05h 41h 04h 00h 00h 00h
LOCK ASSOCIATED MSB REGISTERS
Figure 46. Phase 1 of 10-Bit Read
SECOND READ COMMAND
MSB REGISTER
OUTPUT DATA
UNLOCK ASSOCIATED MSB REGISTERS
Figure 47. Phase 2 of 10-Bit Read
If an MSB register is read first, its corresponding LSB register is not locked out, leaving the user with the option of just reading back 8 bits (MSB) of a 10-bit conversion result. Reading an MSB register first does not lock out other MSB registers, and likewise, reading an LSB register first does not lock out other LSB registers.
04661-A-047
04661-A-046
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ADT7316/ADT7317/ADT7318
Interrupt Status 1 Register (Read-Only) [Add. = 00h] This 8-bit read-only register reflects the status of some of the interrupts that can cause the INT/INT pin to go active. This register is reset by a read operation, provided that any out-oflimit event has been corrected. It is also reset by a software reset. Table 11. Interrupt Status 1 Register
D7 N/A D6 N/A D5 N/A D4 0* D3 0* D2 0* D1 0* D0 0*
Table 15. Internal Temperature/VDD LSBs
D7 N/A N/A D6 N/A N/A D5 N/A N/A D4 N/A N/A D3 V1 0* D2 LSB 0* D1 T1 0* D0 LSB 0*
*Default settings at power-up. Table 16.
Bit D0 D1 D2 D3 Function LSB of Internal Temperature Value. B1 of Internal Temperature Value. LSB of VDD Value. B1 of VDD Value.
*Default settings at power-up. Table 12.
Bit D0 Function 1 when internal temperature value exceeds THIGH limit. Any internal temperature reading greater than the limit set will cause an out-of-limit event. 1 when internal temperature value exceeds TLOW limit. Any internal temperature reading less than or equal to the limit set will cause an out-of-limit event. 1 when external temperature value exceeds THIGH limit. The default value for this limit register is -1C, so any external temperature reading greater than the limit set will cause an out-of-limit event. 1 when external temperature value exceeds TLOW limit. The default value for this limit register is 0C, so any external temperature reading less than or equal to the limit set will cause an out-of-limit event. 1 indicates a fault (open or short) for the external temperature sensor.
D1
External Temperature Value Register LSBs (Read-Only) [Add. = 04h] This 8-bit read-only register stores the 2 LSBs of the 10-bit temperature reading from the external temperature sensor. Table 17. External Temperature LSBs
D7 N/A N/A D6 N/A N/A D5 N/A N/A D4 N/A N/A D3 N/A N/A D2 N/A N/A D1 T1 0* D0 LSB 0*
D2
D3
*Default settings at power-up. Table 18.
Bit D0 D1 Function LSB of External Temperature Value. B1 of External Temperature Value.
D4
Interrupt Status 2 Register (Read-Only) [Add. = 01h] This 8-bit read-only register reflects the status of the VDD interrupt that can cause the INT/INT pin to go active. This register is reset by a read operation provided that any out-oflimit event has been corrected. It is also reset by a software reset. Table 13. Interrupt Status 2 Register
D7 N/A D6 N/A D5 N/A D4 0* D3 N/A D2 N/A D1 N/A D0 N/A
VDD Value Register MSBs (Read-Only) [Add. = 06h] This 8-bit read-only register stores the supply voltage value. The 8 MSBs of the 10-bit value are stored in this register. Table 19. VDD Value MSBs
D7 V9 X* D6 V8 X* D5 V7 x* D4 V6 x* D3 V5 x* D2 V4 x* D1 V3 x* D0 V2 x*
*Loaded with VDD value after power-up.
*Default settings at power-up. Table 14.
Bit D4 Function 1 when VDD value is greater than corresponding VHIGH limit. 1 when VDD is less than or equal to corresponding VLOW limit.
Internal Temperature Value Register MSBs (Read-Only) [Add. = 07h] This 8-bit read-only register stores the internal temperature value from the internal temperature sensor in twos complement format. The 8 MSBs of the 10-bit value are stored in this register. Table 20. Internal Temperature Value MSBs
D7 T9 0* D6 T8 0* D5 T7 0* D4 T6 0* D3 T5 0* D2 T4 0* D1 T3 0* D0 T2 0*
Internal Temperature Value/VDD Value Register LSBs (ReadOnly) [Add. = 03h] This 8-bit read-only register stores the 2 LSBs of the 10-bit temperature reading from the internal temperature sensor and the 2 LSBs of the 10-bit supply voltage reading.
*Default settings at power-up.
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ADT7316/ADT7317/ADT7318
External Temperature Value Register MSBs (Read-Only) [Add. = 08h] This 8-bit read-only register stores the external temperature value from the external temperature sensor in twos complement format. The 8 MSBs of the 10-bit value are stored in this register. Table 21. External Temperature Value MSBs
D7 T9 0* D6 T8 0* D5 T7 0* D4 T6 0* D3 T5 0* D2 T4 0* D1 T3 0* D0 T2 0*
Table 25. DAC B (ADT7316) LSBs
D7 B3 0* D6 B2 0* D5 B1 0* D4 LSB 0* D3 N/A N/A D2 N/A N/A D1 N/A N/A D0 N/A N/A
*Default settings at power-up.
Table 26. DAC B (ADT7317) LSBs
D7 B1 0* D6 LSB 0* D5 N/A N/A D4 N/A N/A D3 N/A N/A D2 N/A N/A D1 N/A N/A D0 N/A N/A
*Default settings at power-up.
DAC A Register LSBs (Read/Write) [Add. = 10h] This 8-bit read/write register contains the 4/2 LSBs of the ADT7316/ADT7317 DAC A word, respectively. The value in this register is combined with the value in the DAC A Register MSBs and converted to an analog voltage on the VOUT-A pin. On power-up, the voltage output on the VOUT-A pin is 0 V. Table 22. DAC A (ADT7316) LSBs
D7 B3 0* D6 B2 0* D5 B1 0* D4 LSB 0* D3 N/A N/A D2 N/A N/A D1 N/A N/A D0 N/A N/A
*Default settings at power-up.
DAC B Register MSBs (Read/Write) [Add. = 13h] This 8-bit read/write register contains the 8 MSBs of the DAC B word. The value in this register is combined with the value in the DAC B register LSBs and converted to an analog voltage on the VOUT-B pin. On power-up, the voltage output on the VOUT-B pin is 0 V. Table 27. DAC B MSBs
D7 MSB 0* D6 B8 0* D5 B7 0* D4 B6 0* D3 B5 0* D2 B4 0* D1 B3 0* D0 B2 0*
*Default settings at power-up.
Table 23. DAC A (ADT7317) LSBs
D7 B1 0* D6 LSB 0* D5 N/A N/A D4 N/A N/A D3 N/A N/A D2 N/A N/A D1 N/A N/A D0 N/A N/A
*Default settings at power-up.
DAC C Register LSBs (Read/Write) [Add. = 14h] This 8-bit read/write register contains the 4/2 LSBs of the ADT7316/ADT7317 DAC C word, respectively. The value in this register is combined with the value in the DAC C register MSBs and converted to an analog voltage on the VOUT-C pin. On power-up, the voltage output on the VOUT-C pin is 0 V. Table 28. DAC C (ADT7316) LSBs
D7 B3 0* D6 B2 0* D5 B1 0* D4 LSB 0* D3 N/A N/A D2 N/A N/A D1 N/A N/A D0 N/A N/A
*Default settings at power-up.
DAC A Register MSBs (Read/Write) [Add. = 11h] This 8-bit read/write register contains the 8 MSBs of the DAC A word. The value in this register is combined with the value in the DAC A Register LSBs and converted to an analog voltage on the VOUT-A pin. On power-up, the voltage output on the VOUT-A pin is 0 V. Table 24. DAC A MSBs
D7 MSB 0* D6 B8 0* D5 B7 0* D4 B6 0* D3 B5 0* D2 B4 0* D1 B3 0* D0 B2 0*
*Default settings at power-up.
Table 29. DAC C (ADT7317) LSBs
D7 B1 0* D6 LSB 0* D5 N/A N/A D4 N/A N/A D3 N/A N/A D2 N/A N/A D1 N/A N/A D0 N/A N/A
*Default settings at power-up.
*Default settings at power-up.
DAC C Register MSBs (Read/Write) [Add. = 15h] This 8-bit read/write register contains the 8 MSBs of the DAC C word. The value in this register is combined with the value in the DAC C register LSBs and converted to an analog voltage on the VOUT-C pin. On power-up, the voltage output on the VOUT-C pin is 0 V.
DAC B Register LSBs (Read/Write) [Add. = 12h] This 8-bit read/write register contains the 4/2 LSBs of the ADT7316/ADT7317 DAC B word, respectively. The value in this register is combined with the value in the DAC B register MSBs and converted to an analog voltage on the VOUT-B pin. On power-up, the voltage output on the VOUT-B pin is 0 V.
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ADT7316/ADT7317/ADT7318
Table 30. DAC C MSBs
D7 MSB 0* D6 B8 0* D5 B7 0* D4 B6 0* D3 B5 0* D2 B4 0* D1 B3 0* D0 B2 0*
Table 35.
Bit C0 Function This bit enables/disables conversions in round robin and single-channel mode. ADT7316/ADT7317/ADT7318 power up in round robin mode but monitoring is not initiated until this bit is set. Default = 0. 0 = Stop Monitoring. 1 = Start Monitoring. Reserved. Only write 0s. 0 = Enable INT/INT Output. 1 = Disable INT/INT Output. Configures INT/INT output polarity. 0 = Active Low. 1 =Active High. Power-down Bit. Setting this bit to 1 puts the ADT7316/ ADT7317/ADT7318 into standby mode. In this mode, both ADC and DACs are fully powered down, but serial interface is still operational. To power up the part again, write a 0 to this bit.
*Default settings at power-up.
DAC D Register LSBs (Read/Write) [Add. = 16h] This 8-bit read/write register contains the 4/2 LSBs of the ADT7316/ADT7317 DAC D word, respectively. The value in this register is combined with the value in the DAC D register MSBs and converted to an analog voltage on the VOUT-D pin. On power-up, the voltage output on the VOUT-D pin is 0 V. Table 31. DAC D (ADT7316) LSBs
D7 B3 0* D6 B2 0* D5 B1 0* D4 LSB 0* D3 N/A N/A D2 N/A N/A D1 N/A N/A D0 N/A N/A
C1:4 C5 C6 PD
*Default settings at power-up.
Table 32. DAC D (ADT7317) LSBs
D7 B1 0* D6 LSB 0* D5 N/A N/A D4 N/A N/A D3 N/A N/A D2 N/A N/A D1 N/A N/A D0 N/A N/A
Control Configuration 2 Register (Read/Write) [Add. = 19h] This configuration register is an 8-bit read/write register that is used to set up some of the operating modes of the ADT7316/ ADT7317/ADT7318. Table 36. Control Configuration 2
D7 C7 0* D6 C6 0* D5 C5 0* D4 C4 0* D3 C3 0* D2 C2 0* D1 C1 0* D0 C0 0*
*Default settings at power-up.
DAC D Register MSBs (Read/Write) [Add. = 17h] This 8-bit read/write register contains the 8 MSBs of the DAC D word. The value in this register is combined with the value in the DAC D register LSBs and converted to an analog voltage on the VOUT-D pin. On power-up, the voltage output on the VOUT-D pin is 0 V. Table 33. DAC D MSBs
D7 MSB 0* D6 B8 0* D5 B7 0* D4 B6 0* D3 B5 0* D2 B4 0* D1 B3 0* D0 B2 0*
*Default settings at power-up.
Table 37.
Bit C1:0 Function In single-channel mode, these bits select between VDD, the internal temperature sensor, and the external temperature sensor for conversion. Default is VDD. 00 = VDD. 01 = Internal Temperature Sensor. 10 = External Temperature Sensor. 11 = Reserved. Reserved. Selects between single-channel and round robin conversion cycle. Default is round robin. 0 = Round Robin. 1 = Single Channel. Default condition is to average every measurement on all channels 16 times. This bit disables this averaging. Channels affected are temperature and VDD. 0 = Enable Averaging. 1 = Disable Averaging. SMBus timeout on the serial clock puts a 25 ms limit on the pulse width of the clock. Ensures that a fault on the master SCL does not lock up the SDA line. SMBus timeout. 0 = Disable. 1 = Enable SMBus Timeout. Software Reset. Setting this bit to a 1 causes a software reset. All registers and DAC outputs will reset to their default settings.
C2:C3 C4
*Default settings at power-up.
Control Configuration 1 Register (Read/Write) [Add. = 18h] This configuration register is an 8-bit read/write register that is used to setup some of the operating modes of the ADT7316/ ADT7317/ADT7318. Table 34. Control Configuration 1
D7 PD 0* D6 C6 0* D5 C5 0* D4 C4 0* D3 C3 0* D2 C2 0* D1 C1 0* D0 C0 0* C7 C5
C6
*Default settings at power-up.
Rev. A | Page 29 of 40
ADT7316/ADT7317/ADT7318
Control Configuration 3 Register (Read/Write) [Add. = 1Ah] This configuration register is an 8-bit read/write register that is used to set up some of the operating modes of the ADT7316/ ADT7317/ADT7318. Table 38. Control Configuration 3
D7 C7 0* D6 C6 0* D5 C5 0* D4 C4 0* D3 C3 0* D2 C2 0* D1 C1 0* D0 C0 0*
Table 41.
Bit D0 Function Selects the output range of DAC A. 0 = 0 V to VREF. 1 = 0 V to 2 VREF. Selects the output range of DAC B. 0 = 0 V to VREF. 1 = 0 V to 2 VREF. Selects the output range of DAC C. 0 = 0 V to VREF. 1 = 0 V to 2 VREF. Selects the output range of DAC D. 0 = 0 V to VREF. 1 = 0 V to 2 VREF. 00 MSB write to any DAC register will generate LDAC command, which updates that DAC only. 01 MSB write to DAC B or DAC D register will generate LDAC command, which updates DACs A, B or DACs C, D, respectively. 10 MSB write to DAC D register will generate LDAC command, which updates all 4 DACs. 11 LDAC command generated from LDAC register. Setting this bit allows the external VREF to bypass the reference buffer when supplying DACs A and B. Setting this bit allows the external VREF to bypass the reference buffer when supplying DACs C and D.
D1
D2
*Default settings at power-up.
Table 39.
Bit C0 Function Selects between fast and normal ADC conversion speeds for all three monitoring channels. 0 = ADC clock at 1.4 kHz. 1 = ADC clock at 22.5 kHz. D+ and D- analog filters are disabled. On the ADT7316 and ADT7317, this bit selects between 8bits and 10-bits DAC output resolution on the thermal voltage output feature. Default = 8 bits. This bit has no effect on the ADT7318 output since this part has only an 8bit DAC. In the ADT7318 case, write 0 to this bit. 0 = 8 Bits Resolution. 1 = 10 Bits Resolution. Reserved. Only write 0. 0 = LDAC pin controls updating of DAC outputs. 1 = DAC configuration register and LDAC configuration register control the updating of the DAC outputs. Reserved. Only write 0. Setting this bit selects DAC A voltage output to be proportional to the internal temperature measurement. Setting this bit selects DAC B voltage output to be proportional to the external temperature measurement. Reserved. Only write 0. D3 D5:D4
C1
D6 D7
C2 C3
C4 C5 C6 C7
LDAC Configuration Register (Write-Only) [Add. = 1Ch] This configuration register is an 8-bit write register that is used to control the updating of the quad DAC outputs if the LDAC pin is disabled and Bits D4 and D5 of DAC Configuration register are both set to 1. It also selects either the internal or external VREF for all four DACs. Bits D0-D3 in this register are self clearing, i.e., reading back from this register will always give 0s for these bits. Table 42. LDAC Configuration
D7 D7 0* D6 D6 0* D5 D5 0* D4 D4 0* D3 D3 0* D2 D2 0* D1 D1 0* D0 D0 0*
DAC Configuration Register (Read/Write) [Add. = 1Bh] This configuration register is an 8-bit read/write register that is used to control the output ranges of all four DACs and to control the loading of the DAC registers if the LDAC pin is disabled (Bit C3 = 1, Control Configuration 3 Register). Table 40. DAC Configuration
D7 D7 0* D6 D6 0* D5 D5 0* D4 D4 0* D3 D3 0* D2 D2 0* D1 D1 0* D0 D0 0*
*Default settings at power-up. Table 43.
Bit D0 D1 D2 D3 D4 Function Writing a 1 to this bit will generate the LDAC command to update the DAC A output only. Writing a 1 to this bit will generate the LDAC command to update the DAC B output only. Writing a 1 to this bit will generate the LDAC command to update the DAC C output only. Writing a 1 to this bit will generate the LDAC command to update the DAC D output only. Selects either internal VREF or external VREF-AB for DACs A and B. 0 = External VREF. 1 = Internal VREF. Selects either internal VREF or external VREF-CD for DACs C and D. 0 = External VREF. 1 = Internal VREF. Reserved. Only write 0s.
*Default settings at power-up.
D5
D6:D7
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ADT7316/ADT7317/ADT7318
Interrupt Mask 1 Register (Read/Write) [Add. = 1Dh] This mask register is an 8-bit read/write register that can be used to mask out any interrupts that can cause the INT/INT pin to go active. Table 44. Interrupt Mask 1
D7 D7 0* D6 D6 0* D5 D5 0* D4 D4 0* D3 D3 0* D2 D2 0* D1 D1 0* D0 D0 0*
Table 48. Internal Temperature Offset
D7 D7 0* D6 D6 0* D5 D5 0* D4 D4 0* D3 D3 0* D2 D2 0* D1 D1 0 D0 D0 0*
*Default settings at power-up. External Temperature Offset Register (Read/Write) [Add. = 20h] This register contains the offset value for the external temperature channel. A twos complement number can be written to this register which is then added to the measured result before it is stored or compared to limits. In this way, onepoint calibration can be done whereby the whole transfer function of the channel can be moved up or down. From a software point of view, this may be a very simple method to vary the characteristics of the measurement channel if the thermal characteristics change. As it is an 8-bit register, the temperature resolution is 1C. Table 49. External Temperature Offset
D7 D7 0* D6 D6 0* D5 D5 0* D4 D4 0* D3 D3 0* D2 D2 0* D1 D1 0* D0 D0 0*
*Default settings at power-up. Table 45.
Bit D0 D1 D2 D3 D4 D5:D7 Function 0 = Enable internal THIGH interrupt. 1 = Disable internal THIGH interrupt. 0 = Enable internal TLOW interrupt. 1 = Disable internal TLOW interrupt. 0 = Enable external THIGH interrupt. 1 = Disable external THIGH interrupt. 0 = Enable external TLOW interrupt. 1 = Disable external TLOW interrupt. 0 = Enable external temperature fault interrupt. 1 = Disable external temperature fault interrupt. Reserved. Only write 0s.
Interrupt Mask 2 Register (Read/Write) [Add. = 1Eh] This mask register is an 8-bit read/write register that can be used to mask out any interrupts that can cause the INT/INT pin to go active. Table 46. Interrupt Mask 2
D7 D7 0* D6 D6 0* D5 D5 0* D4 D4 0* D3 D3 0* D2 D2 0* D1 D1 0* D0 D0 0*
*Default settings at power-up. Internal Analog Temperature Offset Register (Read/Write) [Add. = 21h] This register contains the offset value for the internal thermal voltage output. A twos complement number can be written to this register which is then added to the measured result before it is converted by DAC A. Varying the value in this register has the affect of varying the temperature span. For example, the output voltage can represent a temperature span of -128C to +127C or even 0C to 127C. In essence, this register changes the position of 0 V on the temperature scale. Anything other than -128C to +127C will produce an upper dead band on the DAC A output. As it is an 8-bit register, the temperature resolution is 1C. The default value is -40C. Table 50. Internal Analog Temperature Offset
D7 D7 1* D6 D6 1* D5 D5 0* D4 D4 1* D3 D3 1* D2 D2 0* D1 D1 0* D0 D0 0*
*Default settings at power-up. Table 47.
Bit D0:D3 D4 D5:D7 Function Reserved. Only write 0s. 0 = Enable VDD interrupts. 1 = Disable VDD interrupts. Reserved. Only write 0s.
Internal Temperature Offset Register (Read/Write) [Add. = 1Fh] This register contains the offset value for the internal temperature channel. A twos complement number can be written to this register which is then added to the measured result before it is stored or compared to limits. In this way, a one-point calibration can be done whereby the whole transfer function of the channel can be moved up or down. From a software point of view, this may be a very simple method to vary the characteristics of the measurement channel if the thermal characteristics change. As it is an 8-bit register, the temperature resolution is 1C.
*Default settings at power-up. External Analog Temperature Offset Register (Read/Write) [Add. = 22h] This register contains the offset value for the external thermal voltage output. A twos complement number can be written to this register which is then added to the measured result before it is converted by DAC B. Varying the value in this register has the affect of varying the temperature span. For example, the output
Rev. A | Page 31 of 31
ADT7316/ADT7317/ADT7318
voltage can represent a temperature span of -128C to +127C or even 0C to 127C. In essence, this register changes the position of 0 V on the temperature scale. Anything other than -128C to +127C will produce an upper dead band on the DAC B output. As it is an 8-bit register, the temperature resolution is 1C. The default value is -40C.
Table 51. External Analog Temperature
D7 D7 1* D6 D6 1* D5 D5 0* D4 D4 1* D3 D3 1* D2 D2 0* D1 D1 0* D0 D0 0*
Internal TLOW Limit Register (Read/Write) [Add. 26h] This limit register is an 8-bit read/write register which stores the twos complement of the internal temperature lower limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen, the measured internal temperature value has to be more negative than or equal to the value in this register. As it is an 8-bit register, the temperature resolution is 1C. The default value is -55C. Table 55. Internal TLOW Limit
D7 D7 1* D6 D6 1* D5 D5 0* D4 D4 0* D3 D3 1* D2 D2 0* D1 D1 0* D0 D0 1*
*Default settings at power-up.
VDD VHIGH Limit Register (Read/Write) [Add. = 23h] This limit register is an 8-bit read/write register which stores the VDD upper limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen, the measured VDD value has to be greater than the value in this register. The default value is 5.46 V. Table 52. VDD VHIGH Limit
D7 D7 1* D6 D6 1* D5 D5 0* D4 D4 0* D3 D3 0* D2 D2 1* D1 D1 1* D0 D0 1*
*Default settings at power-up.
External THIGH Limit Register (Read/Write) [Add. = 27h] This limit register is an 8-bit read/write register which stores the twos complement of the external temperature upper limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen, the measured external temperature value has to be greater than the value in this register. As it is an 8-bit register, the temperature resolution is 1C. The default value is -1C. Table 56. External THIGH Limit
D7 D7 1* D6 D6 1* D5 D5 1* D4 D4 1* D3 D3 1* D2 D2 1* D1 D1 1* D0 D0 1*
*Default settings at power-up.
VDD VLOW Limit Register (Read/Write) [Add. = 24h] This limit register is an 8-bit read/write register which stores the VDD lower limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen, the measured VDD value has to be less than or equal to the value in this register. The default value is 2.7 V Table 53. VDD VLOW Limit
D7 D7 0* D6 D6 1* D5 D5 1* D4 D4 0* D3 D3 0* D2 D2 0* D1 D1 1* D0 D0 0*
*Default settings at power-up.
External TLOW Limit Register (Read/Write) [Add. = 28h]
*Default settings at power-up.
Internal THIGH Limit Register (Read/Write) [Add. = 25h] This limit register is an 8-bit read/write register which stores the twos complement of the internal temperature upper limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen, the measured internal temperature value has to be greater than the value in this register. As it is an 8-bit register the temperature resolution is 1C. Default value is +100C. Table 54. Internal THIGH Limit
D7 D7 0* D6 D6 1* D5 D5 1* D4 D4 0* D3 D3 0* D2 D2 1* D1 D1 0* D0 D0 0*
This limit register is an 8-bit read/write register which stores the twos complement of the external temperature lower limit that will cause an interrupt and activate the INT/INT output (if enabled). For this to happen, the measured external temperature value has to be more negative than or equal to the value in this register. As it is an 8-bit register, the temperature resolution is 1C. The default value is 0C.
Table 57. External TLOW Limit
D7 D7 0* D6 D6 0* D5 D5 0* D4 D4 0* D3 D3 0* D2 D2 0* D1 D1 0* D0 D0 0*
*Default settings at power-up.
Device ID Register (Read-Only) [Add. = 4Dh] This 8-bit read-only register indicates which part the device is in the model range. ADT7316 = 01h, ADT7317 = 09h, and ADT7318 = 05h. Manufacturer's ID Register (Read-Only) [Add. = 4Eh] This register contains the manufacturers identification number. ADI's ID is 41h.
*Default settings at power-up.
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ADT7316/ADT7317/ADT7318
Silicon Revision Register (Read-Only) [Add. = 4Fh] This register is divided into the 4 LSBs representing the stepping and the 4 MSBs representing the version. The stepping contains the manufacturer's code for minor revisions or steppings to the silicon. The version is the ADT7316/ADT7317/ ADT7318 version number. SPI Lock Status Register (Read-Only) [Add. = 7Fh] Bit D0 (LSB) of this read-only register indicates whether the SPI interface is locked or not. Writing to this register will cause the device to malfunction. The default value is 00h.
ADT7316/ ADT7317/ ADT7318
CS SDA SCL ADD
02661-A-049
VDD 10k
VDD 10k
I2C ADDRESS = 1001 000
Figure 48. Typical I2C Interface Connection
0 = I2C Interface. 1 = SPI Interface Selected and Locked.
ADT7316/ ADT7317/ ADT7318
CS VDD 820 DIN SCLK DOUT 820 820
LOCK AND SELECT SPI
SPI FRAMING EDGE
Figure 49. Typical SPI Interface Connection
CS (START HIGH)
A
B
C
SPI LOCKED ON THIRD RISING EDGE
SPI FRAMING EDGE
A CS (START LOW)
B
C
02661-A-048
SPI LOCKED ON THIRD RISING EDGE
SPI FRAMING EDGE
Figure 50. Serial Interface--Selecting and Locking SPI Protocol
1 SCL
9
1
9
SDA START BY MASTER
1
0
0
1
A2
A1
A0
R/W
P7
P6
P5
P4
P3
P2
P1
P0
02661-A-051
ACK. BY ADT7316/ADT7317/ADT7318 FRAME 1 SERIAL BUS ADDRESS BYTE
ACK. BY ADT7316/ADT7317/ADT7318 FRAME 2 ADDRESS POINTER REGISTER BYTE
STOP BY MASTER
Figure 51. I2C--Writing to the Address Pointer Register to Select a Register for a Subsequent Read Operation
Rev. A | Page 33 of 40
02661-A-050
ADT7316/ADT7317/ADT7318 SERIAL INTERFACE
There are two serial interfaces that can be used on this part, I2C and SPI. The device will power up with the serial interface in I2C mode, but it is not locked into this mode. To stay in I2C mode, it is recommended that the user ties the CS line to either VCC or GND. It is not possible to lock the I2C mode, but it is possible to select and lock the SPI mode. To select and lock the interface into the SPI mode, a number of pulses must be sent down the CS (Pin 4) line. The following section describes how this is done. Once the SPI communication protocol has been locked in, it cannot be unlocked while the device is still powered up. Bit D0 of SPI Lock Status register (Address = 7Fh) is set to 1 when a successful SPI interface lock has been accomplished. To reset the serial interface, the user must power down the part and power up again. A software reset does not reset the serial interface. set Bit 6 of Control Configuration 2 register. The power-up default is with the SMBus timeout disabled. The ADT7316/ADT7317/ADT7318 support SMBus packet error checking (PEC) and its use is optional. It is triggered by supplying the extra clocks for the PEC byte. The PEC is calculated using CRC-8. The frame clock sequence (FCS) conforms to CRC-8 by the polynomial: C(x) = x8 + x2 + x1 + 1 Consult SMBus specification (www.smbus.org) for more information. The serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line SDA while the serial clock line SCL remains high. This indicates that an address/data stream will follow. All slave peripherals connected to the serial bus respond to the start condition and shift in the next 8 bits, consisting of a 7-bit address (MSB first) plus a R/W bit, which determines the direction of the data transfer, i.e., whether data will be written to or read from the slave device. The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit. All other devices on the bus now remain idle, while the selected device waits for data to be read from or written to it. If the R/W bit is a 0, the master will write to the slave device. If the R/W bit is a 1, the master will read from the slave device. Data is sent over the serial bus in sequences of 9 clock pulses, 8 bits of data followed by an Acknowledge Bit from the receiver of data. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-to-high transition when the clock is high may be interpreted as a stop signal. When all data bytes have been read or written, stop conditions are established. In write mode, the master will pull the data line high during the 10th clock pulse to assert a stop condition. In read mode, the master device will pull the data line high during the low period before the 9th clock pulse. This is known as No Acknowledge. The master will then take the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a stop condition.
SERIAL INTERFACE SELECTION
The CS line controls the selection between I2C and SPI. Figure 49 shows the selection process necessary to lock the SPI interface mode. If the user wants to communicate to the ADT7316/ADT7317/ ADT7318 using the SPI protocol, send three pulses down the CS line as shown in Figure 49. On the third rising edge (marked as C in Figure 49), the part selects and locks the SPI interface. The user is now limited to communicating to the device using the SPI protocol. As per most SPI standards, the CS line must be low during every SPI communication to the ADT7316/ADT7317/ ADT7318 and high all other times. Typical examples of how to connect up the dual interface as I2C or SPI is shown in Figure 48 and Figure 49. The following sections describe in detail how to use the I2C and SPI protocols associated with the ADT7316/ADT7317/ ADT7318. 2.
3.
I2C SERIAL INTERFACE
Like all I2C compatible devices, the ADT7316/ADT7317/ ADT7318 have a 7-bit serial address. The 4 MSBs of this address for the ADT7316/ADT7317/ADT7318 are set to 1001. The 3 LSBs are set by Pin 11, ADD. The ADD pin can be configured three ways to give three different address options: low, floating, and high. Setting the ADD pin low gives a serial bus address of 1001 000, leaving it floating gives the address 1001 010, and setting it high gives the address 1001 011. The recommended pullup resistor value is 10 k. There is a programmable SMBus timeout. When this is enabled the SMBus will timeout after 25 ms of no activity. To enable it,
Any number of bytes of data may be transferred over the serial bus in one operation but it is not possible to mix read and write in one operation because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation.
Rev. A | Page 34 of 40
ADT7316/ADT7317/ADT7318
The I2C address set up by the ADD pin is not latched by the device until after this address has been sent twice. On the eighth SCL cycle of the second valid communication, the serial bus address is latched in. This is the SCL cycle directly after the device has seen its own I2C serial bus address. Any subsequent changes on this pin will have no effect on the I2C serial bus address.
Writing to the ADT7316/ADT7317/ADT7318 Reading Data from the ADT7316/ADT7317/ADT7318
Reading data from the ADT7316/7317/7318 is done in a one byte operation. Reading back the contents of a register is shown in Figure 56. The register address previously had been set up by a single byte write operation to the address pointer register. To read from another register, write to the address pointer register again to set up the relevant register address. Therefore, block reads are not possible, i.e., no I2C auto-increment.
Depending on the register being written to, there are two different writes for the ADT7316/ADT7317/ADT7318. It is not possible to do a block write to this part, i.e., no I2C autoincrement.
Writing to the Address Pointer Register for a Subsequent Read
SPI SERIAL INTERFACE
The SPI serial interface of the ADT7316/ADT7317/ADT7318 consists of four wires, CS, SCLK, DIN, and DOUT. The CS is used to select the device when more than one device is connected to the serial clock and data lines. The CS is also used to distinguish between any two separate serial communications (see Figure 58). The SCLK is used to clock data in and out of the part. The DIN line is used to write to the registers and the DOUT line is used to read data back from the registers. The recommended pull-up resistor value is between 500 to 820 The part operates in a slave mode and requires an externally applied serial clock to the SCLK input. The serial interface is designed to allow the part to be interfaced to systems that provide a serial clock that is synchronized to the serial data. There are two types of serial operations, a read and a write. Command words are used to distinguish between a read and a write operation. These command words are given in Table 58. Address auto-increment is possible in SPI mode.
Table 58. SPI Command Words
Write 90h (1001 0000) Read 91h (1001 0001)
In order to read data from a particular register, the address pointer register must contain the address of that register. If it does not, the correct address must be written to the address pointer register by performing a single-byte write operation, as shown in Figure 51. The write operation consists of the serial bus address followed by the address pointer byte. No data is written to any of the data registers. A read operation is then performed to read the register.
Writing Data to a Register
All registers are 8-bit registers so only one byte of data can be written to each register. Writing a single byte of data to one of these read/write registers consists of the serial bus address, the data register address written to the address pointer register, followed by the data byte written to the selected data register. This is illustrated in Figure 52. To write to a different register, another start or repeated start is required. If more than one byte of data is sent in one communication operation, the addressed register will be repeatedly loaded until the last data byte has been sent.
1 SCL
9
1
9
SDA START BY MASTER
1
0
0
1
A2
A1
A0
R/W
P7
P6
P5
P4
P3
P2
P1
P0
ACK. BY ADT7316/ADT7317/ADT7318 FRAME 1 SERIAL BUS ADDRESS BYTE 1 SCL (CONTINUED)
ACK. BY ADT7316/ADT7317/ADT7318 FRAME 2 ADDRESS POINTER REGISTER BYTE 9
SDA (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
02661-A-052
ACK. BY STOP BY ADT7316/ADT7317/ADT7318 MASTER FRAME 3 DATA BYTE
Figure 52. I2C--Writing to the Address Pointer Register Followed by a Single Byte of Data to the Selected Register
Rev. A | Page 35 of 40
ADT7316/ADT7317/ADT7318
Write Operation
Figure 53 and Figure 54 show the timing diagrams for a write operation to the ADT7316/ADT7317/ADT7318. Data is clocked into the registers on the rising edge of SCLK. When the CS line is high, the DIN and DOUT lines are in three-state mode. Only when the CS goes from a high to a low does the part accept any data on the DIN line. In SPI mode, the address pointer register is capable of auto-increment to the next register in the register map without having to load the address pointer register each time. In Figure 54, the register address portion of the diagram gives the first register that will be written to. Subsequent data bytes will be written into sequential writable registers. Therefore, after each data byte has been written into a
1 9 1
register, the address pointer register auto-increments its value to the next available register. The address pointer register will auto-increment from 00h to 3Fh and will loop back to start all over again at 00h when it reaches 3Fh.
Read Operation
Figure 55 and Figure 57 show the timing diagrams necessary to accomplish correct read operations. To read back from a register, first write to the address pointer register with the address of the register to read from. This operation is shown in Figure 53. Figure 55 shows the procedure for reading back a single byte of data. The read command is first sent to the part during the first eight clock cycles, during the following eight clock cycles the data contained in the register
9
SCL
SDA START BY MASTER
1
0
0
1
A2
A1
A0
R/W
D7
D6
D5
D4
D3
D2
D1
D0 NO ACK. BY MASTER STOP BY MASTER
FRAME 1 SERIAL BUS ADDRESS BYTE
FRAME 2 SINGLE DATA BYTE FROM ADT7316/ADT7317/ADT7318
Figure 53. I2C -- Reading a Single Byte of Data From a Selected Register
CS
1
SCLK
8
1
8
DIN
D7
START
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
WRITE COMMAND
REGISTER ADDRESS
CS (CONTINUED)
1
SCLK (CONTINUED)
8
DIN (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
STOP
DATA BYTE
Figure 54. SPI--Writing to the Address Pointer Register Followed by a Single Byte of Data to the Selected Register
CS
1
8
1
8
SCLK
DIN
D7
START
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
STOP
02661-A-055
WRITE COMMAND
REGISTER ADDRESS
Figure 55. SPI--Writing to the Address Pointer Register to Select a Register for a Subsequent Read Operation
Rev. A | Page 36 of 40
02661-A-054
02661-A-053
ACK. BY ADT7316/ADT7317/ADT7318
ADT7316/ADT7317/ADT7318
CS
1
SCLK
8
1
8
DIN
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
DOUT
X
START
X
X
X
X
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0
02661-A-056
STOP
READ COMMAND DATA BYTE 1
Figure 56. SPI --Reading a Single Byte of Data From a Selected Register
CS
1 8 1 8
SCLK
DIN
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
DOUT
X
X
X
X
X
X
X
X
D7
D6
D5
D4
D3
D2
D1
D0
START
READ COMMAND DATA BYTE 1
CS (CONTINUED)
1
8
SCLK (CONTINUED)
DIN (CONTINUED)
X
X
X
X
X
X
X
X
DOUT (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
STOP
DATA BYTE 2
Figure 57. SPI--Reading Two Bytes of Data from Two Sequential Registers
CS
SPI
READ OPERATION
WRITE OPERATION
Figure 58. SPI--Correct Use of CS During SPI Communication
selected by the address pointer register is outputted onto the DOUT line. Data is outputted onto the DOUT line on the falling edge of SCLK. Figure 57 shows the procedure when reading data from two sequential registers. Multiple data reads are possible in SPI interface mode as the address pointer register is auto-incremental. The address pointer register will auto-increment from 00h to 3Fh and will loop back to start all over again at 00h when it reaches 3Fh.
SMBUS/SPI INT/INT
The ADT7316/ADT7317/ADT7318 INT/INT output is an interrupt line that signals an over-limit/under-limit event on any of the measurement channels if the interrupt on that event has not been disabled. The ADT7316/ADT7317/ADT7318 are a slave-only device and use the SMBus/SPI INT/INT as their only means to signal other devices that an event has occurred.
Rev. A | Page 37 of 40
02661-A-058
02661-A-057
ADT7316/ADT7317/ADT7318
The INT/INT pin has an open-drain configuration that allows the outputs of several devices to be wired-AND together when the INT/INT pin is active low. Use C6 of the Control Configuration 1 Register to set the active polarity of the INT/INT output. The power-up default is active low. The INT/INT output can be disabled or enabled by setting C5 of Control Configuration 1 register to a 1 or 0, respectively. The INT/INT output becomes active when either the internal temperature value, the external temperature value, or the VDD value exceeds the values in their corresponding THIGH/VHIGH or TLOW/VLOW registers. The INT/INT output goes inactive again when a conversion result indicates that all measurement channels are within their trip limits, and when the status register associated with the out-of-limit event is read. The two interrupt status registers show which event caused the INT/INT pin to go active. The INT/INT output requires an external pull-up resistor. This can be connected to a voltage different from VDD provided that the maximum voltage rating of the INT/INT output pin is not exceeded. The value of the pull-up resistor depends on the application but should be large enough to avoid excessive sink currents at the INT/INT output, which can heat the chip and affect the temperature reading.
SMBUS Alert Response
1. 2.
SMBALERT pulled low. Master initiates a read operation and sends the alert response address (ARA = 0001 100). This is a general call address that must not be used as a specific device address. The devices whose INT/INT output is low responds to the alert response address and the master reads its device address. Since the device address is seven bits long, an LSB of 1 is added. The address of the device is now known and it can be interrogated in the usual way. If more than one devices INT/INT output is low, the one with the lowest device address will have priority, in accordance with normal SMBus specifications. Once the ADT7316/ADT7317/ADT7318 has responded to the alert response address, it will reset its INT/INT output, provided that the condition that caused the out-of-limit event no longer exists and the status register associated with the out-of-limit event is read. If the SMBALERT line remains low, the master will send the ARA again. It will continue to do this until all devices whose SMBALERT outputs were low have responded.
MASTER RECEIVES SMBALERT START ALERT RESPONSE ADDRESS MASTER SENDS ARA AND READ COMMAND DEVICE ACK MASTER ACK MASTER NACK
02661-A-060
3.
4.
5.
RD ACK
DEVICE ACK ADDRESS
PEC
NO ACK
STOP
The INT/INT pin behaves the same way as an SMBus alert pin when the SMBus/I2C interface is selected. It is an open-drain output and requires a pull-up to VDD. Several INT/INT outputs can be wire-AND together so that the common line will go low if one or more of the INT/INT outputs goes low. The polarity of the INT/INT pin must be set for active low for a number of outputs to be wire-AND together. The INT/INT output can operate as an SMBALERT function. Slave devices on the SMBus can normally not signal to the master that they want to talk, but the SMBALERT function allows them to do so. SMBALERT is used in conjunction with the SMBus general call address. One or more INT/INT outputs can be connected to a common SMBALERT line connected to the master. When SMBALERT line is pulled low by one of the devices, the following procedure occurs (see Figure 59).
DEVICE SENDS DEVICE SENDS ITS ADDRESS ITS PEC DATA
Figure 60. INT/INT Responds to SMBALERT ARA with Packet Error Checking (PEC)
START
ALERT RESPONSE ADDRESS MASTER SENDS ARA AND READ COMMAND
RD ACK DEVICE ADDRESS
NO STOP ACK
DEVICE SENDS ITS ADDRESS
Figure 59. INT/INT Responds to SMBALERT ARA
Rev. A | Page 38 of 40
02661-A-059
MASTER RECEIVES SMBALERT
ADT7316/ADT7317/ADT7318 LAYOUT CONSIDERATIONS
Digital boards can be electrically noisy environments, and care must be taken to protect the analog inputs from noise, particularly when measuring the very small voltages from a remote diode sensor. The following precautions should be taken: 1. Place the ADT7316/ADT7317/ADT7318 as close as possible to the remote sensing diode. Provided that the worst noise sources, such as clock generators, data/address buses and CRTs, are avoided, this distance can be 4 inches to 8 inches. Route the D+ and D- tracks close together, in parallel, with grounded guard tracks on each side. Provide a ground plane under the tracks if possible. Use wide tracks to minimize inductance and reduce noise pickup. A 10 mil track minimum width and spacing is recommended.
10 MIL 10 MIL D+ 10 MIL 10 MIL D- 10 MIL 10 MIL GND 10 MIL
02661-A-045
4.
2.
Try to minimize the number of copper/solder joints, which can cause thermocouple effects. Where copper/solder joints are used, make sure that they are in both the D+ and D- path and at the same temperature. Thermocouple effects should not be a major problem as 1C corresponds to about 240 V, and thermocouple voltages are about 3 V/C of the temperature difference. Unless there are two thermocouples with a big temperature differential between them, thermocouple voltages should be much less than 200 mV. Place 0.1 F bypass and 2200 pF input filter capacitors close to the ADT7316/ADT7317/ADT7318. If the distance to the remote sensor is more than 8 inches, the use of the twisted pair cable is recommended. This will work up to about 6 feet to 12 feet. For really long distances (up to 100 feet), use shielded twisted pair, such as Belden #8451 microphone cable. Connect the twisted pair to D+ and D- and the shield to GND close to the ADT7316/ADT7317/ADT7318. Leave the remote end of the shield unconnected to avoid ground loops.
5. 6.
3.
7.
GND
Figure 61. Arrangement of Signal Tracks
Because the measurement technique uses switched current sources, excessive cable and/or filter capacitance can affect the measurement. When using long cables, the filter capacitor may be reduced or removed. Cable resistance can also introduce errors. Series resistance of 1 introduces about 0.5C error.
Rev. A | Page 39 of 40
ADT7316/ADT7317/ADT7318 OUTLINE DIMENSIONS
0.193 BSC
16
9
0.154 BSC
1 8
0.236 BSC
PIN 1 0.065 0.049 0.069 0.053
0.010 0.025 0.004 BSC COPLANARITY 0.004
0.012 0.008
SEATING PLANE
0.010 0.006
8 0
0.050 0.016
COMPLIANT TO JEDEC STANDARDS MO-137AB
Figure 62. 16-Lead Shrink Small Outline Package [QSOP] (RQ-16) Dimensions shown in inches and millimeters
ORDERING GUIDE
Model1 ADT7318ARQ ADT7318ARQ-REEL ADT7318ARQ-REEL7 ADT7317ARQ ADT7317ARQ-REEL ADT7317ARQ-REEL7 ADT7316ARQ ADT7316ARQ-REEL ADT7316ARQ-REEL7 Temperature Range -40C to +120C -40C to +120C -40C to +120C -40C to +120C -40C to +120C -40C to +120C -40C to +120C -40C to +120C -40C to +120C DAC Resolution 8-Bits 8-Bits 8-Bits 10-Bits 10-Bits 10-Bits 12-Bits 12-Bits 12-Bits Package Description 16-Lead QSOP 16-Lead QSOP 16-Lead QSOP 16-Lead QSOP 16-Lead QSOP 16-Lead QSOP 16-Lead QSOP 16-Lead QSOP 16-Lead QSOP Minimum Quantities/Reel N/A 2500 1000 N/A 2500 1000 N/A 2500 1000
1
Devices that have date codes before 0414 have an internal reference of 2.25 V. Devices manufactured after this data code have the internal reference at 2.28 V.
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02661-0-6/04(A)
Rev. A | Page 40 of 40
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