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PD- 93922B SMPS MOSFET IRFPS43N50K HEXFET(R) Power MOSFET Applications l Switch Mode Power Supply (SMPS) l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits Benefits l Low Gate Charge Qg results in Simple Drive Requirement l Improved Gate, Avalanche and Dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche Voltage and Current l Low RDS(on) Absolute Maximum Ratings Parameter ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS TJ TSTG Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage dv/dtPeak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case ) VDSS 500V RDS(on) typ. 0.078 ID 47A Super-247TM Max. 47 29 190 540 4.3 30 9.0 -55 to + 150 300 Units A W W/C V V/ns C Avalanche Characteristics Symbol EAS IAR EAR Parameter Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Typ. --- --- --- Max. 910 47 54 Units mJ A mJ Thermal Resistance Symbol RJC RCS RJA Parameter Junction-to-Case Case-to-Sink, Flat, Greased Surface Junction-to-Ambient Typ. --- 0.24 --- Max. 0.23 --- 40 Units C/W www.irf.com 1 04/03/01 IRFPS43N50K Static @ TJ = 25C (unless otherwise specified) Symbol V(BR)DSS V(BR)DSS/TJ RDS(on) VGS(th) IDSS IGSS Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Min. Typ. Max. Units Conditions 500 --- --- V VGS = 0V, ID = 250A --- 0.60 --- V/C Reference to 25C, ID = 1mA --- 0.078 0.090 VGS = 10V, ID = 28A 3.0 --- 5.0 V VDS = V GS, ID = 250A --- --- 50 A VDS = 500V, VGS = 0V --- --- 250 A VDS = 400V, VGS = 0V, TJ = 125C --- --- 100 VGS = 30V nA --- --- -100 VGS = -30V Dynamic @ TJ = 25C (unless otherwise specified) Symbol gfs Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Coss Coss Coss eff. Parameter Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Output Capacitance Effective Output Capacitance Min. 23 --- --- --- --- --- --- --- --- --- --- --- --- --- Typ. --- --- --- --- 25 140 55 74 8310 960 120 10170 240 440 Max. Units Conditions --- S VDS = 50V, ID = 28A 350 ID = 47A 85 nC VDS = 400V 180 VGS = 10V, See Fig. 6 and 13 --- VDD = 250V --- ID = 47A ns --- RG = 1.0 --- VGS = 10V,See Fig. 10 --- VGS = 0V --- VDS = 25V --- pF = 1.0MHz, See Fig. 5 --- VGS = 0V, VDS = 1.0V, = 1.0MHz --- VGS = 0V, VDS = 400V, = 1.0MHz --- VGS = 0V, VDS = 0V to 400V Diode Characteristics Symbol IS ISM VSD trr Q rr IRRM ton Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Reverse RecoveryCurrent Forward Turn-On Time Min. Typ. Max. Units --- --- --- --- 47 A 190 --- --- 1.5 V --- 620 940 ns --- 14 21 C --- 38 --- A Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) Conditions MOSFET symbol showing the G integral reverse p-n junction diode. TJ = 25C, IS = 47A, VGS = 0V TJ = 25C, IF = 47A di/dt = 100A/s D S Notes: Repetitive rating; pulse width limited by max. junction temperature. (See Fig. 11) Pulse width 400s; duty cycle 2%. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS . Starting TJ = 25C, L = 0.82mH, RG = 25, IAS = 47A (See Figure 12a). ISD 47A, di/dt 230A/s, VDD V(BR)DSS, TJ 150C. 2 www.irf.com IRFPS43N50K 1000 I D , Drain-to-Source Current (A) 100 I D , Drain-to-Source Current (A) VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP 1000 100 VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP 10 10 1 4.5V 1 0.1 4.5V 20s PULSE WIDTH TJ = 25 C 1 10 100 0.01 0.1 0.1 0.1 20s PULSE WIDTH TJ = 150 C 1 10 100 VDS , Drain-to-Source Voltage (V) VDS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 1000 3.5 RDS(on) , Drain-to-Source On Resistance (Normalized) ID = 48A I D , Drain-to-Source Current (A) 3.0 2.5 100 TJ = 150 C 2.0 1.5 10 TJ = 25 C 1 1.0 0.5 0.1 4 5 6 7 8 V DS = 50V 20s PULSE WIDTH 9 10 11 12 0.0 -60 -40 -20 VGS = 10V 0 20 40 60 80 100 120 140 160 VGS , Gate-to-Source Voltage (V) TJ , Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature www.irf.com 3 IRFPS43N50K 1000000 VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd Coss = Cds + Cgd 10000 20 ID = 48A V DS= 400V V DS= 250V V DS= 100V 100000 VGS , Gate-to-Source Voltage (V) C, Capacitance(pF) 15 Ciss 10 1000 Coss 100 Crss 5 10 1 10 100 1000 0 0 50 100 150 200 250 300 350 VDS, Drain-to-Source Voltage (V) QG , Total Gate Charge (nC) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 1000 1000 ISD , Reverse Drain Current (A) OPERATION IN THIS AREA LIMITED BY RDS(on) TJ = 150 C 10 ID , Drain Current (A) 100 100 10us 100us TJ = 25 C 1 10 1ms 0.1 0.2 V GS = 0 V 0.7 1.2 1.7 2.2 1 TC = 25 C TJ = 150 C Single Pulse 10 100 10ms 1000 VSD ,Source-to-Drain Voltage (V) VDS , Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4 www.irf.com IRFPS43N50K 50 VDS VGS RD 40 D.U.T. + ID , Drain Current (A) RG -VDD 30 10V Pulse Width 1 s Duty Factor 0.1 % 20 Fig 10a. Switching Time Test Circuit 10 VDS 90% 0 25 50 75 100 125 150 TC , Case Temperature ( C) 10% VGS Fig 9. Maximum Drain Current Vs. Case Temperature td(on) tr t d(off) tf Fig 10b. Switching Time Waveforms 1 Thermal Response (Z thJC ) 0.1 D = 0.50 0.20 0.10 0.05 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE) 0.01 0.001 0.00001 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T = P DM x ZthJC + TC J 0.0001 0.001 0.01 0.1 PDM t1 t2 1 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 IRFPS43N50K 2000 EAS , Single Pulse Avalanche Energy (mJ) 1500 TOP BOTTOM ID 22A 30A 47A VDS L 1 5V D R IV E R 1000 RG D .U .T IA S + - VD D A 500 20V tp 0 .0 1 Fig 12c. Unclamped Inductive Test Circuit 0 25 50 75 100 125 150 Starting TJ , Junction Temperature ( C) Fig 12a. Maximum Avalanche Energy Vs. Drain Current tp V (B R )D SS IAS Fig 12d. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50K 12V .2F .3F QG VGS D.U.T. + V - DS QGS VG QGD VGS 3mA IG ID Current Sampling Resistors Charge Fig 13a. Gate Charge Test Circuit Fig 13b. Basic Gate Charge Waveform 6 www.irf.com IRFPS43N50K Peak Diode Recovery dv/dt Test Circuit D.U.T + + Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer - + RG * * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test + VDD Driver Gate Drive P.W. Period D= P.W. Period VGS=10V * D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt VDD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% ISD * VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFET(R) Power MOSFETs www.irf.com 7 IRFPS43N50K SUPER -247AC Package Outline Dimensions are shown in millimeters (inches) 0.13 [.005] 16.10 [.632] 15.10 [.595] 5.50 [.216] 4.50 [.178] 2.15 [.084] 1.45 [.058] 0.25 [.010] BA 2X R 3.00 [.118] 2.00 [.079] A 13.90 [.547] 13.30 [.524] 1.30 [.051] 0.70 [.028] 20.80 [.818] 19.80 [.780] 4 16.10 [.633] 15.50 [.611] 4 C 1 2 3 B O 1.60 [.063] MAX. E E 14.80 [.582] 13.80 [.544] 4.25 [.167] 3.85 [.152] 5.45 [.215] 2X 3X 1.60 [.062] 1.45 [.058] BA 3X 1.30 [.051] 1.10 [.044] 0.25 [.010] S ECT ION E-E NOT ES : 1. DIMENS IONING AND T OLE RANCING PER AS ME Y14.5M-1994. 2. DIMENS IONS ARE S HOWN IN MILLIMET ERS [INCHES ] 3. CONT ROLLING DIMENS ION: MILLIMET ER 4. OUT LINE CONF ORMS T O JEDEC OUT LINE T O-274AA 2.35 [.092] 1.65 [.065] LE AD AS S IGNMENT S MOS FET 1 - GATE 2 - DRAIN 3 - S OURCE 4 - DRAIN IGBT 1 - GATE 2 - COLLECT OR 3 - EMIT T ER 4 - COLLECT OR Data and specifications subject to change without notice. This product has been designed and qualified for the industrial market. Qualification Standards can be found on IR's Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.04/01 8 www.irf.com |
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