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CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V
Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs
Features
* High-speed, low-power, first-in, first-out (FIFO) memories * 64 x 9 (CY7C4421V) * 256 x 9 (CY7C4201V) * 512 x 9 (CY7C4211V) * 1K x 9 (CY7C4221V) * 2K x 9 (CY7C4231V) * 4K x 9 (CY7C4241V) * 8K x 9 (CY7C4251V) * High-speed 66-MHz operation (15-ns read/write cycle time) * Low power (ICC = 20 mA) * 3.3V operation for low power consumption and easy integration into low-voltage systems * 5V-tolerant inputs VIH max= 5V * Fully asynchronous and simultaneous read and write operation * Empty, Full, and Programmable Almost Empty and Almost Full status flags * TTL compatible * Output Enable (OE) pin * Independent read and write enable pins * Center power and ground pins for reduced noise * Width expansion capability * Space saving 32-pin 7 mm x 7 mm TQFP * 32-pin PLCC
Functional Description
The CY7C42X1V are high-speed, low-power, FIFO memories with clocked read and write interfaces. All are nine bits wide. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering. These FIFOs have 9-bit input and output ports that are controlled by separate clock and enable signals. The input port is controlled by a Free-Running Clock (WCLK) and two Write Enable pins (WEN1, WEN2/LD). When WEN1 is LOW and WEN2/LD is HIGH, data is written into the FIFO on the rising edge of the WCLK signal. While WEN1, WEN2/LD is held active, data is continually written into the FIFO on each WCLK cycle. The output port is controlled in a similar manner by a Free-Running Read Clock (RCLK) and two Read Enable Pins (REN1, REN2). In addition, the CY7C42X1V has an Output Enable Pin (OE). The Read (RCLK) and Write (WCLK) clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 66 MHz are achievable. Depth expansion is possible using one enable input for system control, while the other enable is controlled by expansion logic to direct the flow of data.
Logic Block Diagram
D0 - 8
Pin Configuration
PLCC Top View
4 3 2 1 32 3130 29 5 28 6 27 7 26 8 9 25 10 24 11 23 22 12 21 13 141516 171819 20 EF FF Q0 Q1 Q2 Q3 Q4 D2 D3 D4 D5 D6 D7 D8 D1 D0 PAF PAE GND REN1 RCLK REN2 OE EF PAE PAF FF
INPUT REGISTER
WCLK WEN1 WEN2/LD FLAG PROGRAM REGISTER WRITE CONTROL FLAG LOGIC Dual Port RAM Array 64 x 9 WRITE POINTER 8Kx 9 READ POINTER
RS WEN1 WCLK WEN2/LD V CC Q8 Q7 Q6 Q5
TQFP Top View
D4 D5 D6 D7 D8 RS 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 OE EF FF Q0 Q1 Q2 Q3 Q4 D2 D3 1 2 3 4 5 6 7 8
32 31 30 29 28 27 26 25 RS RESET LOGIC D1 D0 PAF PAE GND REN1 RCLK REN2 WEN1 WCLK WEN2/LD VCC Q8 Q7 Q6 Q5
THREE-ST ATE OUTPUTREGISTER OE Q0 - 8
READ CONTROL
RCLK REN1 REN2
Cypress Semiconductor Corporation Document #: 38-06010 Rev. *A
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised August 22, 2003
CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V
Selection Guide
CY7C42X1V-15 Maximum Frequency Maximum Access Time Minimum Cycle Time Minimum Data or Enable Set-up Minimum Data or Enable Hold Maximum Flag Delay Active Power Supply Current CY7C4421V Density 64 x 9 Commercial CY7C4201V 256 x 9 CY7C4211V 512 x 9 66.7 11 15 4 1 10 20 CY7C4221V 1K x 9 CY7C42X1V-25 40 15 25 6 1 15 20 CY7C4231V 2K x 9 CY7C42X1V-35 28.6 20 35 7 2 20 20 CY7C4241V 4K x 9 Unit MHz ns ns ns ns ns mA CY7C4251V 8K x 9
Pin Definitions
Signal Name D0-8 Q0-8 WEN1 Description Data Inputs Data Outputs Write Enable 1 I/O I O I Data Inputs for 9-bit bus. Data Outputs for 9-bit bus. The only write enable when device is configured to have programmable flags. Data is written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is HIGH. If the FIFO is configured to have two write enables, data is written on a LOW-to-HIGH transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH. If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this pin operates as a control to write or read the programmable flag offsets. WEN1 must be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW to write or read the programmable flag offsets. Enables the device for Read operation. The rising edge clocks data into the FIFO when WEN1 is LOW and WEN2/LD is HIGH and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable flag-offset register. The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and the FIFO is not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable flag offset register. When EF is LOW, the FIFO is empty. EF is synchronized to RCLK. When FF is LOW, the FIFO is full. FF is synchronized to WCLK. When PAE is LOW, the FIFO is almost empty based on the almost empty offset value programmed into the FIFO. When PAF is LOW, the FIFO is almost full based on the almost full offset value programmed into the FIFO. Resets device to empty condition. A reset is required before an initial read or write operation after power-up. When OE is LOW, the FIFO's data outputs drive the bus to which they are connected. If OE is HIGH, the FIFO's outputs are in High Z (high-impedance) state. When entering or exiting the Empty and Almost Empty states, the flags are updated exclusively by the RCLK. The flags denoting Almost Full and Full states are updated exclusively by WCLK. The synchronous flag architecture guarantees that the flags maintain their status for at least one cycle All configurations are fabricated using an advanced 0.65m P-Well CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings. Description
WEN2/LD Dual Mode Pin
Write Enable 2 Load
I I
REN1, REN2 WCLK
Read Enable Inputs Write Clock
I I
RCLK
Read Clock
I
EF FF PAE PAF RS OE
Empty Flag Full Flag Programmable Almost Empty Programmable Almost Full Reset Output Enable
O O O O I I
Functional Description (continued)
The CY7C42X1V provides four status pins: Empty, Full, Almost Empty, Almost Full. The Almost Empty/Almost Full flags are programmable to single word granularity. The programmable flags default to Empty-7 and Full-7. The flags are synchronous, i.e., they change state relative to either the Read Clock (RCLK) or the Write Clock (WCLK).
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CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V
Architecture
The CY7C42X1V consists of an array of 64 to 8K words of nine bits each (implemented by a dual-port array of SRAM cells), a read pointer, a write pointer, control signals (RCLK, WCLK, REN1, REN2, WEN1, WEN2, RS), and flags (EF, PAE, PAF, FF.) Write Enable 2/Load (WEN2/LD). This is a dual-purpose pin. The FIFO is configured at Reset to have programmable flags or to have two write enables, which allows for depth expansion. If Write Enable 2/Load (WEN2/LD) is set active HIGH at Reset (RS=LOW), this pin operates as a second write enable pin. If the FIFO is configured to have two write enables, when Write Enable (WEN1) is LOW and Write Enable 2/Load (WEN2/LD) is HIGH, data can be loaded into the input register and RAM array on the LOW-to-HIGH transition of every write clock (WCLK.) Data is stored in the RAM array sequentially and independently of any on-going read operation.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS) cycle. This causes the FIFO to enter the Empty condition signified by EF being LOW. All data outputs (Q0-8) go LOW tRSF after the rising edge of RS. In order for the FIFO to reset to its default state, a falling edge must occur on RS and the user must not read or write while RS is LOW. All flags are guaranteed to be valid tRSF after RS is taken LOW.
Programming
When WEN2/LD is held LOW during Reset, this pin is the load (LD) enable for flag offset programming. In this configuration, WEN2/LD can be used to access the four 8-bit offset registers contained in the CY7C42X1V for writing or reading data to these registers. When the device is configured for programmable flags and both WEN2/LD and WEN1 are LOW, the first LOW-to-HIGH transition of WCLK writes data from the data inputs to the empty offset Least Significant Bit (LSB) register. The second, third, and fourth LOW-to-HIGH transitions of WCLK store data in the empty offset Most Significant Bit (MSB) register, full offset LSB register, and full offset MSB register, respectively, when WEN2/LD and WEN1 are LOW. The fifth LOW-to-HIGH transition of WCLK while WEN2/LD and WEN1 are LOW writes data to the empty LSB register again. Figure 1 shows the register sizes and default values for the various device types. It is not necessary to write to all the offset registers at one time. A subset of the offset registers can be written; then by bringing the WEN2/LD input HIGH, the FIFO is returned to normal read and write operation. The next time WEN2/LD is brought LOW, a write operation stores data in the next offset register in sequence. The contents of the offset registers can be read to the data outputs when WEN2/LD is LOW and both REN1 and REN2 are LOW. LOW-to-HIGH transitions of RCLK read register contents to the data outputs. Writes and reads should not be performed simultaneously on the offset registers.
FIFO Operation
When the WEN1 signal is active LOW and WEN2 is active HIGH, data present on the D0-8 pins is written into the FIFO on each rising edge of the WCLK signal. Similarly, when the REN1 and REN2 signals are active LOW, data in the FIFO memory will be presented on the Q0-8 outputs. New data will be presented on each rising edge of RCLK while REN1 and REN2 are active. REN1 and REN2 must set up tENS before RCLK for it to be a valid read function. WEN1 and WEN2 must occur tENS before WCLK for it to be a valid write function. An Output Enable (OE) pin is provided to three-state the Q0-8 outputs when OE is asserted. When OE is enabled (LOW), data in the output register will be available to the Q0-8 outputs after tOE. The FIFO contains overflow circuitry to disallow additional writes when the FIFO is full, and underflow circuitry to disallow additional reads when the FIFO is empty. An empty FIFO maintains the data of the last valid read on its Q0-8 outputs even after additional reads occur. Write Enable 1 (WEN1). If the FIFO is configured for programmable flags, Write Enable 1 (WEN1) is the only write enable control pin. In this configuration, when Write Enable 1 (WEN1) is LOW, data can be loaded into the input register and RAM array on the LOW-to-HIGH transition of every write clock (WCLK). Data is stored is the RAM array sequentially and independently of any on-going read operation.
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CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V
64 x 9 8 6 0 8 256 x 9 7
Empty Offset (LSB) Reg. Default Value = 007h
512 x 9 0 8 7
Empty Offset (LSB) Reg. Default Value = 007h
1K x 9 0 8 7
Empty Offset (LSB) Reg. Default Value = 007h
0
Empty Offset (LSB) Reg. Default Value = 007h
8
0
8
0
8
0
(MSB) 0
8
1
(MSB) 00
0
8
6
Full Offset (LSB) Reg Default Value = 007h
0
8
7
Full Offset (LSB) Reg Default Value = 007h
0
8
7
Full Offset (LSB) Reg Default Value = 007h
0
8
7
Full Offset (LSB) Reg Default Value = 007h
0
8
0
8
0
8
0
(MSB) 0
8
1
(MSB) 00
0
2K x 9 8 7
Empty Offset (LSB) Reg. Default Value = 007h
4K x 9 0 8 7
Empty Offset (LSB) Reg. Default Value = 007h
8K x 9 0 8 7
Empty Offset (LSB) Reg. Default Value = 007h
0
8
2
(MSB) 000
0
8
3
(MSB) 0000
0
8
4
(MSB) 00000
0
8
7
Full Offset (LSB) Reg Default Value = 007h
0
8
7
Full Offset (LSB) Reg Default Value = 007h
0
8
7
Full Offset (LSB) Reg Default Value = 007h
0
8
2
(MSB) 000
0
8
3
(MSB) 0000
0
8
4
(MSB) 00000
0
Figure 1. Offset Register Location and Default Values Programmable Flag (PAE, PAF) Operation Whether the flag offset registers are programmed as described in Table 1 or the default values are used, the programmable Almost Empty Flag (PAE) and programmable Almost Full Flag (PAF) states are determined by their corresponding offset registers and the difference between the read and write pointers. Table 1. Writing the Offset Registers LD 0 WEN 0 WCLK[1] Selection Empty Offset (LSB) Empty Offset (MSB) Full Offset (LSB) Full Offset (MSB) No Operation Write Into FIFO No Operation The number formed by the empty offset least significant bit register and empty offset most significant register is referred to as n and determines the operation of PAE. PAE is synchronized to the LOW-to-HIGH transition of RCLK by one flip-flop and is LOW when the FIFO contains n or fewer unread words. PAE is set HIGH by the LOW-to-HIGH transition of RCLK when the FIFO contains (n+1) or greater unread words. The number formed by the full offset least significant bit register and full offset most significant bit register is referred to as m and determines the operation of PAF. PAE is synchronized to the LOW-to-HIGH transition of WCLK by one flip-flop and is set LOW when the number of unread words in the FIFO is greater than or equal to CY7C4421V (64 - m), CY7C4201V (256 - m), CY7C4211V (512 - m), CY7C4221V (1K - m), CY7C4231V (2K - m), CY7C4241V (4K - m), and CY7C4251V (8K - m). PAF is set HIGH by the LOW-to-HIGH transition of WCLK when the number of available memory locations is greater than m.
0 1 1
1 0 1
Note: 1. The same selection sequence applies to reading from the registers. REN1 and REN2 are enabled and a read is performed on the LOW-to-HIGH transition of RCLK.
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CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V
Table 2. Status Flags Number of Words in FIFO CY7C4421V 0 1 to n[2] (n+1) to 32 33 to (64-(m+1)) (64-m) 64
[3] to 63
CY7C4201V 0 1 to n[2] (n+1) to 128 129 to (256-(m+1)) (256-m)[3] to 255 256 0 1 to n[2]
CY7C4211V
FF H H H H H L
PAF H H H H L L
PAE L L H H H H
EF L H H H H H
(n+1) to 256 257 to (512-(m+1)) (512-m)[3] to 511 512
Number of Words in FIFO CY7C4221V 0 1 to n[2] (n+1) to 512 513 to (1024 -(m+1)) (1024-m)[3] to 1023 1024 0 1 to n
[2]
CY7C4231V 0 1 to n
CY7C4241V 0
[2]
CY7C4251V 1 to n
[2]
FF H H H H H L
PAF H H H H L L
PAE L L H H H H
EF L H H H H H
(n+1) to 1024 1025 to (2048 -(m+1)) (2048-m)[3] to 2047 2048
(n+1) to 2048 2049 to (4096 -(m+1)) (4096-m)[3] to 4095 4096
(n+1) to 4096 4097 to (8192 -(m+1)) (8192-m)[3] to 8191 8192
Width Expansion Configuration
Word width may be increased simply by connecting the corresponding input control signals of multiple devices. A composite flag should be created for each of the end-point status flags (EF and FF). The partial status flags (PAE and PAF) can be detected from any one device. Figure 2 demonstrates a 18-bit word width by using two CY7C42X1Vs. Any word width can be attained by adding additional CY7C42X1Vs. When the CY7C42X1V is in a Width Expansion Configuration, the Read Enable (REN2) control input can be grounded (see Figure 2). In this configuration, the Write Enable 2/Load (WEN2/LD) pin is set to LOW at Reset so that the pin operates as a control to load and read the programmable flag offsets.
Flag Operation
The CY7C42X1 devices provide four flag pins to indicate the condition of the FIFO contents. Empty, Full, PAE, and PAF are synchronous. Full Flag The Full Flag (FF) will go LOW when device is full. Write operations are inhibited whenever FF is LOW regardless of the state of WEN1 and WEN2/LD. FF is synchronized to WCLK, i.e., it is exclusively updated by each rising edge of WCLK. Empty Flag The Empty Flag (EF) will go LOW when the device is empty. Read operations are inhibited whenever EF is LOW, regardless of the state of REN1 and REN2. EF is synchronized to RCLK, i.e., it is exclusively updated by each rising edge of RCLK.
Notes: 2. n = Empty Offset (n=7 default value). 3. m = Full Offset (m=7 default value).
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CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V
RESET (RS) DATA IN (D) 18
9 9
RESET (RS)
WRITE CLOCK (WCLK) WRITE ENABLE 1 (WEN1) WRITE ENABLE 2/LOAD (WEN2/LD) PROGRAMMABLE (PAF) FULL FLAG (FF) # 1 FF FULL FLAG (FF) # 2
9
CY7C42X1V CY7C42X1V
READ CLOCK (RCLK) READ ENABLE 1 (REN1) OUTPUT ENABLE (OE) PROGRAMMABLE (PAE) EMPTY FLAG (EF) #1
EF FF
EF EMPTY FLAG (EF) #2
9
DATA OUT (Q)
18
Read Enable 2 (REN2)
Read Enable 2 (REN2)
Figure 2. Block Diagram of 64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9 Low-Voltage Synchronous FIFO Memory Used in a Width-Expansion Configuration
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CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ...................................-65C to +150C Ambient Temperature with Power Applied............................................. --55C to +125C Supply Voltage to Ground Potential ............... -0.5V to +5.0V DC Voltage Applied to Outputs in High-Z State ............................................... -0.5V to +5.0V DC Input Voltage ............................................-0.5V to +5.0V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA
Operating Range
Range Commercial Ambient Temperature 0C to +70C VCC 3.3V 300 mV
Electrical Characteristics Over the Operating Range
7C42X1V-15 Parameter VOH VOL VIH VIL IIX IOZL IOZH ICC[4] ISB[5] Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output OFF, High Z Current Active Power Supply Current Average Standby Current VCC = Max. OE > VIH, VSS < VO < VCC Com'l Com'l Test Conditions VCC = Min., IOH = -2.0 mA VCC = Min., IOL = 8.0 mA 2.0 -0.5 -10 -10 Min. 2.4 0.4 5.0 0.8 +10 +10 20 6 2.0 -0.5 -10 -10 Max. 7C42X1V-25 Min. 2.4 0.4 5.0 0.8 +10 +10 20 6 2.0 -0.5 -10 -10 Max. 7C42X1V-35 Min. 2.4 0.4 5.0 0.8 +10 +10 20 6 Max. Unit V V V V A A mA mA
Capacitance[6]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 5 7 Unit pF pF
AC Test Loads and Waveforms[7, 8]
R1= 330 3.3V OUTPUT CL INCLUDING JIG AND SCOPE Equivalent to: THE VENIN EQUIVALENT Rth=200 OUTPUT R2=510 3.0V GND 3 ns
ALL INPUT PULSES
90% 10% 90% 10%
3 ns
Vth=2.0V
Notes: 4. Outputs open. Tested at Frequency = 20 MHz. 5. All inputs = VCC - 0.2V, except WCLK and RCLK, which are switching at 20 MHz. 6. Tested initially and after any design or process changes that may affect these parameters. 7. CL = 30 pF for all AC parameters except for tOHZ. 8. CL = 5 pF for tOHZ.
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CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V
Switching Characteristics Over the Operating Range
7C42X1V-15 Parameter tS tA tCLK tCLKH tCLKL tDS tDH tENS tENH tRS tRSS tRSR tRSF tOLZ tOE tOHZ tWFF tREF tPAF tPAE tSKEW1 tSKEW2 Data Access Time Clock Cycle Time Clock HIGH Time Clock LOW Time Data Set-Up Time Data Hold Time Enable Set-Up Time Enable Hold Time Reset Pulse Width[9] Reset Set-Up Time Reset Recovery Time Reset to Flag and Output Time Output Enable to Output in Low Output Enable to Output Valid Output Enable to Output in High Write Clock to Full Flag Read Clock to Empty Flag Clock to Programmable Almost-Full Flag Clock to Programmable Almost-Full Flag Skew Time between Read Clock and Write Clock for Empty Flag and Full Flag Skew Time between Read Clock and Write Clock for Almost-Empty Flag and Almost-Full Flag 6 15 Z[10] Z[10] 0 3 3 8 8 11 11 16 16 10 18 Description Clock Cycle Frequency 2 15 6 6 4 1 4 1 15 10 10 18 0 3 3 12 12 15 15 22 22 12 20 Min. Max. 66.7 11 2 25 10 10 6 2 6 2 25 15 15 25 0 3 3 15 15 20 20 25 25 7C42X1V-25 Min. Max. 40 15 2 35 14 14 7 2 7 2 35 20 20 35 7C42X1V-35 Min. Max. 28.6 20 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 9. Pulse widths less than minimum values are not allowed. 10. Values guaranteed by design, not currently tested.
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Switching Waveforms
Write Cycle Timing
tCLKH WCLK tDS D0 -D8 tENS WEN1 tENH
NO OPERATION
tCLK tCLKL
tDH
WEN2 (if applicable) FF tSKEW1 RCLK
[11]
NO OPERATION
tWFF
tWFF
REN1,REN2
Read Cycle Timing
tCLKH RCLK tENS REN1,REN2 tREF EF tA Q0 -Q8 tOLZ tOE OE tENH
tCKL tCLKL
NO OPERATION
tREF
VALID DATA
tOHZ
tSKEW1 WCLK
[12]
WEN1
WEN2
Notes: 11. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge. 12. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF may not change state until the next RCLK rising edge.
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CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V
Switching Waveforms (continued)
Reset Timing[13]
tRS RS tRSS REN1, REN2 tRSS WEN1 tRSS WEN2/LD
[15]
tRSR
tRSR
tRSR
tRSF EF,PAE tRSF FF,PAF, tRSF Q0 - Q8 OE=1 [14] OE=0
Notes: 13. The clocks (RCLK, WCLK) can be free-running during reset. 14. After reset, the outputs will be LOW if OE = 0 and three-state if OE=1. 15. Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable for the programmable flag offset registers.
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CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V
Switching Waveforms (continued)
First Data Word Latency after Reset with Simultaneous Read and Write
WCLK tDS D0 -D8 tENS WEN1 WEN2 (if applicable) tSKEW1 RCLK tREF EF tA REN1, REN2
[17]
D0 (FIRSTVALID WRITE)
D1
D2
D3
D4
tFRL
[16]
tA
Q0 -Q8 tOLZ tOE OE
D0
D1
Notes: 16. When tSKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK + tSKEW1. The Latency Timing applies only at the Empty Boundary (EF = LOW). 17. The first word is available the cycle after EF goes HIGH, always.
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CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V
Switching Waveforms (continued)
Empty Flag Timing
WCLK tDS D0 -D8 DATAWRITE1 tENH WEN1 tENS tENS WEN2 (if applicable) tFRL RCLK tSKEW1 EF REN1, REN2 LOW OE tA Q0 -Q8 DATA IN OUTPUT REGISTER DATA READ tREF tREF tSKEW1 tREF
[16]
tDS DATAWRITE2 tENH tENS tENH tENS tENH
tFRL
[16]
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Switching Waveforms (continued)
Full Flag Timing
WCLK tSKEW1 [11] D0 -D8 tWFF FF tDS tSKEW1 [11] DATA WRITE tWFF tWFF DATA WRITE NO WRITE NO WRITE NO WRITE
WEN1
WEN2 (if applicable)
RCLK tENH REN1, REN2 tENS tENS tENH
OE
LOW tA tA DATA READ NEXT DATA READ
Q0 -Q8
DATA IN OUTPUT REGISTER
Programmable Almost Empty Flag Timing
tCLKH WCLK tENS tENH WEN1 tCLKL
WEN2 (if applicable) tENS tENH PAE tSKEW2 RCLK tENS REN1, REN2
Notes: 18. tSKEW2 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the rising RCLK is less than tSKEW2, then PAE may not change state until the next RCLK. 19. PAE offset = n. 20. If a read is performed on this rising edge of the read clock, there will be Empty + (n-1) words in the FIFO when PAE goes LOW.
[18]
Note 19 N + 1 WORDS INFIFO tPAE Note 20 tPAE
tENS tENH
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CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V
Switching Waveforms (continued)
Programmable Almost Full Flag Timing
tCLKH WCLK tENS tENH WEN1 [22] tCLKL Note 21
WEN2 (if applicable) tENS tENH PAF FULL - (M+1) WORDS IN FIFO
tPAF FULL - M WORDS IN FIFO [23] tSKEW2 [24] tPAF
RCLK tENS REN1, REN2 tENS tENH
Write Programmable Registers
tCLK tCLKH WCLK tENS WEN2/LD tENS WEN1 tDS D0 -D8 PAE OFFSET LSB PAE OFFSET MSB PAF OFFSET LSB PAF OFFSET MSB tDH tENH tCLKL
Notes: 21. If a write is performed on this rising edge of the write clock, there will be Full - (m-1) words of the FIFO when PAF goes LOW. 22. PAF offset = m. 23. 64-m words for CY7C4421V, 256-m words in FIFO for CY7C4201V, 512-m words for CY7C4211V, 1024-m words for CY7C4221V, 2048-m words for CY7C4231V, 4096-m words for CY7C4241V, 8192-m words for CY7C4251V. 24. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK.
Document #: 38-06010 Rev. *A
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CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V
Switching Waveforms (continued)
Read Programmable Registers
tCLK tCLKH RCLK tENS WEN2/LD tENS REN1, REN2 tA Q0 -Q8 UNKNOWN PAE OFFSET LSB PAE OFFSET MSB PAF OFFSET LSB PAF OFFSET MSB tENH tCLKL
Ordering Information
256 x 9 Low Voltage Synchronous FIFO Speed (ns) 15 25 Speed (ns) 15 25 Ordering Code CY7C4201V-15AC CY7C4201V-25AC Ordering Code CY7C4211V-15AC CY7C4211V-15JC CY7C4211V-25AC CY7C4211V-25JC 1K x 9 Low Voltage Synchronous FIFO Speed (ns) 15 25 Speed (ns) 15 25 Ordering Code CY7C4221V-15AC CY7C4221V-15JC CY7C4221V-25AC Ordering Code CY7C4231V-15AC CY7C4231V-15JC CY7C4231V-25AC CY7C4231V-25JC 4K x 9 Low Voltage Synchronous FIFO Speed (ns) 15 25 Ordering Code CY7C4241V-15AC CY7C4241V-15JC CY7C4241V-25AC CY7C4241V-25JC Package Name A32 J65 A32 J65 Package Type 32-Lead Thin Quad Flatpack 32-Lead Plastic Leaded Chip Carrier 32-Lead Thin Quad Flatpack 32-Lead Plastic Leaded Chip Carrier Commercial Operating Range Commercial 2K x 9 Low Voltage Synchronous FIFO Package Name A32 J65 A32 J65 Package Type 32-Lead Thin Quad Flatpack 32-Lead Plastic Leaded Chip Carrier 32-Lead Thin Quad Flatpack 32-Lead Plastic Leaded Chip Carrier Commercial Operating Range Commercial Package Name A32 J65 A32 Package Type 32-Lead Thin Quad Flatpack 32-Lead Plastic Leaded Chip Carrier 32-Lead Thin Quad Flatpack Commercial Operating Range Commercial Package Name A32 A32 Package Name A32 J65 A32 J65 Package Type 32-Lead Thin Quad Flatpack 32-Lead Thin Quad Flatpack Package Type 32-Lead Thin Quad Flatpack 32-Lead Plastic Leaded Chip Carrier 32-Lead Thin Quad Flatpack 32-Lead Plastic Leaded Chip Carrier Commercial Operating Range Commercial Commercial Operating Range Commercial
512 x 9 Low Voltage Synchronous FIFO
Document #: 38-06010 Rev. *A
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CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V
Ordering Information (continued)
8K x 9 Low Voltage Synchronous FIFO Speed (ns) 15 25 Ordering Code CY7C4251V-15AC CY7C4251V-15JC CY7C4251V-25AC Package Name A32 J65 A32 Package Type 32-Lead Thin Quad Flatpack 32-Lead Plastic Leaded Chip Carrier 32-Lead Thin Quad Flatpack Commercial Operating Range Commercial
Package Diagrams
32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.0 mm A32
51-85063-*B
32-Lead Plastic Leaded Chip Carrier J65
51-85002-*B
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-06010 Rev. *A
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(c) Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V
Document History Page
Document Title: CY7C4421V/4201V/4211V/4221V/CY7C4231V/4241V/4251V Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs Document Number: 38-06010 REV. ** *A ECN NO. Issue Date 106471 127857 09/10/01 08/25/03 Orig. of Change SZV FSG Description of Change Change from Spec number: 38-00622 to 38-06010 Fixed empty flag timing diagram Fixed switching waveform diagram typo
Document #: 38-06010 Rev. *A
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