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EL2141
Data Sheet February 11, 2005 FN7048.1
150MHz Differential Twisted Pair Driver
The EL2141 is a very high bandwidth amplifier whose output is in differential form, and is thus primarily targeted for applications such as driving twisted pair lines, or any application where common mode injection is likely to occur. The input signal can be in either single-ended or differential form, but the output is always in differential form. On the EL2141, two feedback inputs provide the user with the ability to set the device gain, (stable at minimum gain of two). The output common mode level is set by the reference pin (VREF), which has a -3dB bandwidth of over 100MHz. Generally, this pin is grounded, but it can be tied to any voltage reference. The transmission of ADSL/HDSL signals requires very low distortion amplification, so this amplifier was designed with this as a primary goal. The actual signal distortion levels depend upon input and output signal amplitude, as well as the output load impedance. (See distortion data inside.) Both outputs (VOUT, VOUTB) are short circuit protected to withstand temporary overload condition.
Features
* Fully differential inputs, outputs, and feedback * Differential input range 2.3V * 150MHz 3dB bandwidth * 800V/s slew rate * -55dB distortion at 3MHz * -75dB distortion at 100kHz * 5V supplies or +6V single supply * 50mA minimum output current * Output swing (200 load) to within 1.5V of supplies (14VPKPK differential) * Low power-11mA typical supply current * Pb-free available (RoHS compliant)
Applications
* Twisted pair driver * Differential line driver * VGA over twisted pair
Ordering Information
PART NUMBER EL2141CS EL2141CS-T7 EL2141CS-T13 EL2141CSZ (See Note) EL2141CSZ-T7 (See Note) EL2141CSZT13 (See Note) PACKAGE 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC (Pb-free) 8-pin SOIC (Pb-free) 8-pin SOIC (Pb-free) TAPE & REEL 7" 13" 7" 13" PKG. DWG. # MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027
* ADSL/HDSL driver * Single ended to differential amplification * Transmission of analog signals in a noisy environment
Pinout
EL2141 (8-PIN SOIC) TOP VIEW
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1995, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
EL2141
Absolute Maximum Ratings (TA = 25C)
Supply Voltage VS+ and GND . . . . . . . . . . . . . . . . . . . . . . . . +12.6V Maximum Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60mA Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150C Recommended Operating Temperature . . . . . . . . . . . -40C to 85C VIN, VINB, VREF. . . . . . . . . . . . VEE+0.8V (MIN) to VCC-0.8V (MAX) VIN-VINB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
DC Electrical Specifications
PARAMETER VSUPPLY IS VOS IIN ZIN VDIFF AVOL VOUT(200) VOUT(100) VN VREFOS PSRR IOUT(min) ROUT
VCC = +5V, VEE = -5V, TA = 25C, VIN = 0V, RL = 200, unless otherwise specified. DESCRIPTION MIN 3.0 TYP 5.0 11 -25 -20 10 6 400 2.0 2.3 75 3.4 2.9 3.6 3.1 36 -60 60 50 -25 70 60 0.1 +60 MAX 6.3 14 40 20 UNITS V mA mV A k V dB V V nV/Hz mV dB mA
Supply Operating Range (VCC-VEE) Power Supply Current (No Load) Input Referred Offset Voltage Input Bias Current (VIN, VINB, VREF) Differential Input Impedance Differential Input Range Open Loop Voltage Gain Output Voltage Swing (200 load, VOUT to VOUTB) Output Voltage Swing (100 Load, VOUT to VOUTB) Input Referred Voltage Noise Output Offset Relative to VREF Power Supply Rejection Ratio Minimum Output Current (VOUT = VOUTB = 0V) Output Impedance
AC Electrical Specifications
PARAMETER BW(-3dB) SR Tstl GBW VREFBW(-3dB) VREFSR THDf1 dP dG NOTE:
VCC = +5V, VEE = -5V, TA = 25C, VIN = 0V, RLOAD = 200, unless otherwise specified DESCRIPTION MIN TYP 150 800 15 400 130 100 -75 0.16 0.24 MAX UNITS MHz V/s ns MHz MHz V/s dB %
-3dB Bandwidth (@ gain of 2) Differential Slewrate Settling Time to 1% Gain Bandwidth Product VREF -3dB Bandwidth VREF Slewrate Distortion at 100kHz (Note 1) Differential Phase @ 3.58MHz Differential Gain @ 3.58MHz
1. Distortion measurement quoted for VOUT-VOUTB = 12V pk-pk, RLOAD = 200, VGAIN = 8
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FN7048.1 February 11, 2005
EL2141 Pin Descriptions
EL2141 2 1 4 3 5 6 7 8 PIN NAME VIN FBP FBN VREF VOUTB VCC VEE VOUT Non-inverting Input Non-inverting Feedback Input. Resistor R1 must be Connected from this Pin to VOUT. Inverting Feedback Input. Resistor R3 must be Connected from this pin to VOUTB. Output Common-mode Control. The Common-mode Voltage of VOUT and VOUTB will Follow the Voltage on this Pin. Note that on the EL2141, this pin is also the VINB pin. Inverting Output Positive Supply Negative Supply Non-inverting Output FUNCTION
Typical Performance Curves
FIGURE 1. IS vs SUPPLY VOLTAGE
FIGURE 2. FREQUENCY RESPONSE vs RESISTOR R2 (GAIN = 2)
FIGURE 3. FREQUENCY RESPONSE vs TEMPERATURE
FIGURE 4. FREQUENCY RESPONSE vs RESISTOR R2 (GAIN = 8)
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FN7048.1 February 11, 2005
EL2141 Typical Performance Curves
(Continued)
FIGURE 5. DISTORTION vs FREQUENCY (GAIN = 6, RLOAD = 200) VIN = 2VPK-PK
FIGURE 6. OUTPUT SIGNAL AND COMMON MODE SIGNAL vs FREQUENCY
Applications Information
The amount of capacitance tolerated on any of these nodes in an actual application will also be dependent on the gain setting and the resistor values in the feedback network.
Distortion Considerations
The harmonics that these amplifiers will potentially produce are the 2nd, 3rd, 5th, and 6th. Their amplitude is application dependent. All other harmonics should be negligible by comparison. Each should be considered separately: H2 The second harmonic arises from the input stage, and the lower the applied differential signal amplitude, the lower the magnitude of the second harmonic. For practical considerations of required output signal and input noise levels, the user will end up choosing a circuit gain. Referring to Figure 1, it is best if the voltage at the negative feedback node tracks the VREF node, and the voltage at the positive feedback node tracks the VIN node respectively. This would theoretically require that R1 + R2 = R3, although the lowest distortion is found at about R3 = R1 + (0.7*R2). With this arrangement, the second harmonic should be suppressed well below the value of the third harmonic. H3 The third harmonic should be the dominant harmonic and is primarily affected by output load current which, of course, is unavoidable. However, this should encourage the user not to waste current in the gain setting resistors, and to use values that consume only a small proportion of the load current, so long as peaking does not occur. The more load current, the worse the distortion, but depending on the frequency, it may be possible to reduce the amplifier gain so that there is more internal gain left to cancel out any distortion. H5 The fifth harmonic should always be below the third, and will not become significant until heavy load currents are drawn. Generally, it should respond to the same efforts applied to reducing the third harmonic. H6 The sixth harmonic should not be a problem and is the result of poor power supply decoupling. While 100nF chip capacitors may be sufficient for some applications, it would be insufficient for driving full signal swings into a twisted pair line at 100kHz. Under these conditions, the addition of 4.7F tantalum capacitors would cure the problem.
R1 + R2 + R3 GAIN = -----------------------------------R2
Choice of Feedback Resistor
There is little to be gained from choosing resistor R2 values below 400 and, in fact, it would only result in increased power dissipation and signal distortion. Above 400, the bandwidth response will develop some peaking (for a gain of two), but substantially higher resistor R2 values may be used for higher voltage gains, such as up to 2k at a gain of eight before peaking will develop. R1 and R3 are selected as needed to set the voltage gain, and while R1 = R3 is suggested, the gain equation above holds for any values (see distortion for further suggestions).
Capacitance Considerations
As with many high bandwidth amplifiers, the EL2141 prefers not to drive highly capacitive loads. It is best if the capacitance on VOUT and VOUTB is kept below 10pF if the user does not want gain peaking to develop. In addition, on the EL2141, the two feedback nodes FBP and FBN should be laid out so as to minimize stray capacitance, else an additional pole will potentially develop in the response with possible gain peaking.
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FN7048.1 February 11, 2005
EL2141 Typical Applications Circuits
FIGURE 7. TYPICAL TWISTED PAIR APPLICATION
FIGURE 8. DIFFERENTIAL LINE DRIVER WITH EQUALIZATION R1 + R2 + R3 DCGain = ------------------------------------ ( SeeFigure9 ) R2 R1 + ( R2 R4 ) + R3 ( HF )Gain = ----------------------------------------------------- ( SeeFigure9 ) ( R2 R4 )
1 whereF O = ---------------------2C 1 R 2 1 andF P = ---------------------2C 1 R 4
FIGURE 9. DUAL SIGNAL TRANSMISSION CIRCUIT
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FN7048.1 February 11, 2005
EL2141 SOIC Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 6
FN7048.1 February 11, 2005

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