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| LF2301 DEVICES INCORPORATED Image Resampling Sequencer LF2301 DEVICES INCORPORATED Image Resampling Sequencer DESCRIPTION The LF2301 is a self-sequencing address generator designed to filter a two-dimensional image or remap and resample it from one set of Cartesian coordinates (x,y) into a new set (u,v). The LF2301 can resample digitized images or perform such manipulations as rotation, panning, zooming, and warping as well as compression in real-time. By using two LF2301s in a Image Transformation System (ITS), nearest-neighbor, bilinear interpolation, and cubic convolution algorithms, with kernel sizes up to 4 x 4 pixels, are all possible (see Figure 1). This system can also implement simple static filters with kernel sizes up to 16 x 16 pixels. DETAILS OF OPERATION Most video applications use a pair of LF2301s in tandem to construct an ITS. One LF2301 is the row coordinate generator (x to u) and the other is the column generator (y to v). External RAM is needed for storage of the interpolation coefficient lookup table, as well as for buffers of the source and destination images. An external MultiplierAccumulator is required when performing interpolation or implementing static filters. The ITS is capable of performing the general second-order coordinate transformation of the form: x(u,v) = Au 2+Bu+Cuv+Dv2+Ev+F y(u,v) = Gu2+Hu+Kuv+Lv2+Mv+N where parameters A through N of the transform are user-defined. The system steps sequentially through each pixel in the "target" image lying within a user-defined rectangle. For each "target" pixel at (u,v), the LF2301 points to a corresponding "source" pixel at (x,y). FEATURES u 40 MHz Clock Rate u High-Speed Image Manipulation u Maximum Image Size: 4096 x 4096 Pixels u Supports Following Interpolation Algorithms: * Nearest-Neighbor * Bilinear Interpolation * Cubic Convolution u Applications: * Video Special-Effects * Image Recognition * High-Speed Data Encoding/ Decoding u Replaces TRW/Raytheon/Fairchild TMC2301 u 68-pin PLCC, J-Lead LF2301 BLOCK DIAGRAM LDR WEN B3-0 P11-0 NOOP INTER INIT PARAMETER STORAGE CONTROL WALK COUNT ACC DONE END SOURCE ADDRESS GENERATOR FRACTION INTEGER INPUT IMAGE BOUNDARY COMPARATOR TARGET ADDRESS GENERATOR OETA CA7-0 X11-0 CZERO UWRI U11-0 Video Imaging Products 2-1 08/16/2000-LDS.2301-H LF2301 DEVICES INCORPORATED Image Resampling Sequencer FIGURE 1. IMAGE TRANSFORMATION SYSTEM (ITS) IMAGE DATA IN 12 SIGNAL DEFINITIONS Power Vcc and GND +5V power supply. All pins must be connected. Clock CLK -- Master Clock The rising edge of CLK strobes all enabled registers. Inputs P11-0 -- Parameter Register Data Input P11-0 is the 12-bit Parameter Register Data input port. P11-0 is latched on the rising edge of CLK. B3-0 -- Parameter Register Address Input B3-0 is the 4-bit Parameter Register Address input port. B3-0 is latched on the rising edge of CLK. Outputs X11-0 -- Source Address Output X11-0 is the 12-bit registered Source Address output port. CA7-0 -- Coefficient Address Output CA7-0 is the 8-bit registered Coefficient Address output port. U11-0 -- Target Address Output U11-0 is the 12-bit registered Target Address output port. Controls INIT -- Initialize When INIT is HIGH for a minimum of two clock cycles, the control logic is cleared and initialized for the start of a new image transformation. When INIT goes LOW, normal operation begins after two clock cycles. INIT is latched on the rising edge of CLK. WEN -- Write Enable When WEN is LOW, data latched into the device on P11-0 is loaded into the preload register addressed by the data P11-0 B3-0 INIT, LDR, WEN, NOOP, OETA 12 4 5 X11-0 LF2301 Row Address Generator (X) CA7-0 8 12 24 ACC UWRI U11-0 12 INTER END SOURCE IMAGE RAM 12 X ACC INTERPOLATION COEFFICIENT RAM LMA1009/2009 12 x 12 bit MultiplierAccumulator X,Y,P DOUT 12 8 12 Y CA7-0 LF2301 Column Address Generator (Y) 12 12 24 Y11-0 V11-0 INTER END DESTINATION IMAGE RAM 12 CLK IMAGE DATA OUT latched into the device on B3-0. When WEN is HIGH, data cannot be loaded into the preload registers and their contents will not be changed. WEN is latched on the rising edge of CLK. LDR -- Load Data Register When LDR is HIGH, data in all preload registers is latched into the Transformation Parameter Registers. When LDR is LOW, data cannot be loaded into the Transformation Parameter Registers and their contents will not be changed. LDR is latched on the rising edge of CLK. ACC -- Accumulate The registered ACC output initializes the accumulation register of the external multiplier-accumulator. At the start of each interpolation "walk," ACC goes LOW for one cycle effectively clearing the storage register by loading in only the new first product. ACC from either the row or column LF2301 may be used. UWRI -- Target Memory Write Enable The Target Memory Write Enable goes LOW for one clock cycle after the end of each interpolation "walk." When OETA is HIGH, this registered output is forced to the high-impedance state. UWRI from either the row or column LF2301 may be used. INTER -- Interconnect When two LF2301s are used to form an ITS, the END flag on each device is connected to INTER on the other device. The END flag from the row device indicates an "end of line" to the column device. The END flag from the column device indicates a "bottom of frame" to the row device, forcing a reset of the address counter. NOOP -- No Operation When NOOP is LOW, the clock is overridden holding all address generators in their current state. X11-0 and CA7-0 are forced to the high- Video Imaging Products 2-2 08/16/2000-LDS.2301-H LF2301 DEVICES INCORPORATED Image Resampling Sequencer When Mode is set to "01" or "11" END goes HIGH on the row device for K+1 clock cycles starting at (K+1) + 2 clock cycles before the last X address of a row. END goes HIGH on the column device for (K+1) x (K+1) clock cycles starting at [(K+1) x (K+1)] + 1 clock cycles before the last X address of a frame. DONE -- End of Transform In a two LF2301 system, after the last walk of the last row of an image, the registered DONE flag goes HIGH indicating the end of the transform. DONE goes HIGH one clock cycle before the last X address of a frame. If AIN is HIGH, DONE will remain HIGH for one clock cycle. If AIN is LOW, DONE will remain HIGH until a new transform begins. Transformation Control Parameters XMIN, XMAX, YMIN, YMAX XMIN, XMAX, YMIN, YMAX define the valid area in the source image from which pixels may be read. The CZERO flags will denote a valid memory read whenever the LF2301s generate an (x,y) address within this boundary. UMIN, UMAX, VMIN, VMAX UMIN, UMAX, VMIN, VMAX define the area in the destination image into which pixels will be written. (UMIN, VMIN) is the top left corner and (UMAX + 1, VMAX) is the bottom right corner. The following conditions must be met: UMAX>UMIN and VMAX>VMIN. x0, y0 x0, y0 determine what the first pixel read out of the source image will be at the beginning of an image transformation. x0, y0 will be the upper left corner of the original image in non-inverting, nonreversing applications. dx/du dx/du is the displacement along the x axis corresponding to a one-pixel movement along the u axis. 2-3 impedance state. Users may then access external memory. Normal operation resumes on the next clock cycle after NOOP goes HIGH. NOOP is latched on the rising edge of CLK. OETA -- Target Memory Output Enable When OETA is HIGH, UWRI and U11-0 are forced to the high-impedance state. When OETA is LOW, UWRI and U11-0 are enabled on the next clock cycle. OETA is latched on the rising edge of CLK. Flags CZERO -- Coefficient Zero If in a row device x<0, XMINxXMAX, or x4096, the registered CZERO flag goes HIGH . If 0x dx/dv dx/dv is the displacement along the x axis corresponding to each one-pixel movement along the v axis. dy/du dy/du is the displacement along the y axis corresponding to each one-pixel movement along the u axis. dy/dv dy/dv is the displacement along the y axis corresponding to each one-pixel movement along the v axis. d2x/du2 d2x/du2 determines the rate of change of dx/du with each step along a line in the output image. d2x/dv2 d2x/dv2 determines the rate of change of dx/dv with each step down a column in the output image. d2y/du2 d2y/du2 determines the rate of change of dy/du with each step along a line in the output image. d2y/dv2 d2y/dv2 determines the rate of change of dy/dv with each step down a column in the output image. d2x/dudv d2x/dudv determines the rate of change of dx/du while moving vertically through the output image. d2x/dudv also determines the rate of change of dx/dv while moving horizontally through the output image. d2y/dudv d2y/dudv determines the rate of change of dy/dv while moving horizontally through the output image. d2y/dudv also determines the rate of change of dy/du while moving vertically through the output image. Video Imaging Products 08/16/2000-LDS.2301-H LF2301 DEVICES INCORPORATED Image Resampling Sequencer possible is 4 x 4 pixels (Kernel = 3). For static filters, kernels of up to 16 x 16 pixels (Kernel = 15) are possible. FOV -- Field of View FOV determines the distance between pixels in a spiral walk. An FOV of 1 means each step in a spiral walk is one pixel. An FOV of 2 means each step is two pixels, and so on. FOV can be set as high as 7 (see Table 3). It is important to note when FOV is 0, the x and y addresses will not change during a spiral walk. They will remain fixed at the first pixel address of the spiral walk. ALR -- Autoload When set HIGH and upon INIT being strobed, the LDR control is automatically asserted which causes the data currently stored in the Preload Registers to be loaded into the Transformation Parameter Registers. AIN -- Autoinit A new transform automatically begins if the AIN bit is HIGH when the end of an image is reached. The DONE flag will go HIGH for one clock cycle. If AIN is LOW, UWRI and the DONE flag remain HIGH until the user strobes the INIT control to begin a new image transformation. PIPE -- Pipe Control In order to compensate for buffered source image RAM, PIPE adjusts the timing of UWRI and ACC. If the PIPE bit is HIGH, UWRI and ACC will have a one clock cycle delay added relative to the generation of the target address. TM -- Test Mode Calculations of the source image and coefficient addresses are made by an internal 28-bit accumulator. TM allows access to the sign bit and the seven bits below the four coefficient address bits in the accumulator. When TM is HIGH the sign bit and 11 bits below the source image address are fed to X11-0 (see Figure 2). When TM is LOW, the source image address is fed to X11-0. Two clock cycles are required to access both the MS and LS words of the internal accumulator. Functional Description The LF2301 is an address generator designed to be used in an image transformation system (ITS). When implementing an LF2301-based ITS, second-order image transformations can be performed like resampling, rotation, warping, panning, and rescaling, all at real-time video rates. 2D filtering operations, like pixel convolutions, can also be performed. In most applications two LF2301s are used, one to generate the row addresses and the other to generate the column TABLE 1. MODE SELECTION M1 M0 MODE 0 0 single-pass operation (CW) 0 1 1 1 pass 1 of two-pass operation 0 single-pass operation (CCW) 1 pass 2 of two-pass operation R/C -- Row/Column Select When set to 0, the LF2301 functions as a row device. When set to 1, the LF2301 functions as a column device. M1-0 -- Mode This 2-bit control word defines four modes as follows (see table 1): The 1st and 3rd modes are singlepass operations where the device walks through a (K + 1) x (K + 1) kernel for each output pixel. K is the kernel size determined by K3-0 in Parameter Register 7. In mode 00, the spiral walk is in the clockwise direction. In mode 10, the spiral walk is in the counter clockwise direction. The 2nd and 4th modes are used together to perform a two-pass operation. The first pass (mode 01) performs a (K+1) kernel in the horizontal dimension. The second pass (mode 11) performs a (K+1) kernel in the vertical dimension. The result of pass 1 is stored in the destination image memory and is used as the source image data for the second pass. A system to switch source and destination memory banks could be designed, or utilization of a second LF2301 pair in a pipelined architecture could be used. In this case, the system would require a third image buffer for the final destination image. K3-0 -- Kernel Kernel determines the length of the spiral walk when performing image transformations and the size of the filter when implementing static filters (see table 2). When performing image transformations, the longest spiral walk TABLE 2. KERNEL K3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 K2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 K1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 K0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Kernel 1x1 2x2 3x3 4x4 5x5 6x6 7x7 8x8 9x9 10 x 10 11 x 11 12 x 12 13 x 13 14 x 14 15 x 15 16 x 16 TABLE 3. FIELD OF VIEW F2 0 0 0 0 1 1 1 1 F1 0 0 1 1 0 0 1 1 F0 0 1 0 1 0 1 0 1 FOV 0 1 2 3 4 5 6 7 Video Imaging Products 2-4 08/16/2000-LDS.2301-H LF2301 DEVICES INCORPORATED Image Resampling Sequencer FIGURE 2. TEST MODE DATA ROUTING 28-BIT INTERNAL ACCUMULATOR SIGN 1 addresses. An example of an ITS implemented with two LF2301s is shown in Figure 1. In this system the following components are used: two LF2301s, a multiplier-accumulator (MAC), interpolation coefficient RAM, and source/target image RAM. Maximum image size is 4096 x 4096 pixels. Data word size is determined by the word size of the external RAM. A typical ITS performs image transformations as follows: a. The LF2301s generate sequential pixel addresses (left to right, top to bottom) which fill the rectangle in the target image RAM defined by (UMIN,VMIN) and (UMAX +1, VMAX). It is important to note that the U value of the last pixel address on each line of the target RAM is UMAX + 1. b. The LF2301s calculate the address of the corresponding pixel in the source image RAM for each target pixel address generated. c. If interpolation is needed, the external MAC sums the products of the source pixels and the interpolation coefficients. Control signals for the MAC and address signals for the interpolation coefficient RAM are provided by the LF2301s. d. The new pixel value is written into the target image RAM. The LF2301s generate source pixel addresses according to the following general second order equations: x = Au2 + Bu + Cuv + Dv2 + Ev + F y = Gu2 + Hu + Kuv + Lv2 + Mv + N where (x,y) and (u,v) are the source and target coordinates respectively. A through N are user-defined parameters. The actual second order equations used are shown in Figure 3. 12 12 X11-0/T11-0 4 12 7 4 CA7-4 CA3-0 WALK COUNTER 4 FIGURE 3. ADDRESS TRANSFORMATION EQUATIONS x = x0 + dx m + du dx n + d 2 x mn + d 2 x m2- m + d 2 x du2 2 dv 2 dv dudv n2- n 2 + FOV * CAX(w) + FOV * m * CAX(ker) y = y0 + dy m + du dy n + d 2 y mn + d 2 y m2- m + d 2 y du2 2 dv 2 dv dudv n2- n 2 + FOV * CAY(w) + FOV * m * CAY(ker) u = UMIN + m v = VMIN + n NOTE: m2- m APPROXIMATES THE EXPONENTIAL CHARACTERISTIC OF m2. 2 Video Imaging Products 2-5 08/16/2000-LDS.2301-H LF2301 DEVICES INCORPORATED Image Resampling Sequencer FIGURE 4. LDR CONTROL FOR PARAMETER UPDATE P11-0 12 Transformation Parameter Register Loading The LF2301 allows Transformation Parameters to be updated on-the-fly. The loading of these registers is double-buffered (see Figure 4). Any or all of the first level registers can be loaded using P11-0, B3-0, and WEN without affecting the parameters currently in use. LDR simultaneously updates all Transformation Parameter Registers. If Autoload (ALR) is active, these registers will be updated automatically at the beginning of each new image. Note that NOOP does not affect the loading of the Transformation Parameter Registers. TRANSFORMATION PARAMETER REGISTERS C15 C14 C13 C2 C1 C0 PRELOAD REGISTERS B3-0 4 WEN LDR CLK TABLE 4. ADDR 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 MSB 2 11 PARAMETER REGISTER FORMATS (ROW OR COLUMN MODE) FORMAT 2 10 DECODE LSB 2 4 ROW XMIN XMAX x0 (LS) Controls, x0 (MS) dx/du (LS) Controls, dx/du (MS) dx/dv (LS) Kernel, dx/dv (MS) d2x/dudv (LS) d x/dudv (MS) d x/du (LS) d x/du (MS) d2x/dv2 (LS) d2x/dv2 (MS) UMIN UMAX 2 2 2 2 2 COLUMN YMIN YMAX y0 (LS) Controls, y0 (LS) dy/du (LS) Controls, dy/du (MS) dy/dv (LS) Kernel, dy/dv (MS) d2y/dudv (LS) d2y/dudv (MS) d2y/du2 (LS) d2y/du2 (MS) d2y/dv2 (LS) d2y/dv2 (MS) VMIN VMAX 2 9 2 8 2 7 2 6 2 5 2 3 2 2 2 1 2 0 211 26 ALR 2-1 TM 2-1 K3 2-9 -2 2 -2 3 -9 3 210 25 AIN 2-2 F2 2-2 K2 2-10 2 2 2 2 -10 2 29 24 PIPE 2-3 F1 2-3 K1 2-11 2 2 2 1 -11 1 28 23 R/C 2-4 F0 2-4 K0 2-12 2 2 2 0 -12 0 27 22 M1 2-5 -27 2-5 -2 2 2 2 7 26 21 M0 2-6 26 2-6 2 2 2 2 6 25 20 -2 12 24 2-1 2 11 23 2-2 2 10 22 2-3 2 9 21 2-4 2 8 20 2-5 27 2-12 20 2-12 2 2 2 2 0 2-7 25 2-7 2 2 2 2 5 2-8 24 2-8 2 2 2 2 4 2-9 23 2-9 2 2 2 2 3 2-10 22 2-10 2 2 2 2 2 2-11 21 2-11 2 2 2 2 1 2-13 -1 -13 -1 2-14 -2 -14 -2 2-15 -3 -15 -3 2-16 -4 -16 -4 2-17 -5 -17 -5 2-18 -6 -18 -6 2-19 -7 -19 -7 2-20 -8 -20 -8 2-9 -23 211 2 11 2-10 22 210 2 10 2-11 21 29 2 9 2-12 20 28 2 8 2-13 2-1 27 2 7 2-14 2-2 26 2 6 2-15 2-3 25 2 5 2-16 2-4 24 2 4 2-17 2-5 23 2 3 2-18 2-6 22 2 2 2-19 2-7 21 2 1 2-20 2-8 20 2 0 Video Imaging Products 2-6 08/16/2000-LDS.2301-H LF2301 DEVICES INCORPORATED Image Resampling Sequencer completed was the last for that line). At the end of the first spiral walk, pixel (7,5) is addressed. Since the first pixel of the next spiral walk should be (7,6), dx/du is selected to be 0 and dy/du is selected to be 1. After the last pixel of the last spiral walk on the first line has been selected, the first pixel address of the second line is determined by adding dx/dv to x0 and by adding dy/dv to y0. Since the first pixel of the first spiral walk on the second line should be (6,7), dx/dv is selected to be 0 and dy/dv is selected to be 1. Second order differential terms are not used in this filter and are therefore set to 0. UMIN and VMIN are both selected to be 6. UMAX and VMAX are both selected to be 7. Table 5 shows the values loaded into all Parameter Registers. Table 6 shows the ITS outputs for the 3 x 3 static filter. Static Filter Static filtering at real-time video rates can be performed as shown in Figure 5. This mode is selected by loading M1-0 with "00" for a clockwise spiral walk. A counterclockwise spiral walk could be selected by loading M1-0 with "10." In this example, a static filter with a kernel size of 3 x 3 pixels is desired. Loading K3-0 with "0010" selects a kernel size of 3 x 3. The first pixel selected is determined by x0 and y0. In this example, the first pixel is (6,6). In this case, the LF2301s should address consecutive pixels during each spiral walk. For this to occur, FOV must be set to 1 (F2-0 loaded with "001"). After the last pixel of a spiral walk has been selected, the next pixel address is determined by adding dx/du to the current X address and by adding dy/du to the current Y address (unless the kernel just FIGURE 5. 3 x 3 STATIC FILTER 5 4 6 7 8 9 5 1 2 6 7 8 1 = 1st pixel of 1st spiral walk, 2 = 1st pixel of 2nd spiral walk, etc. TABLE 5. PARAMETER REGISTERS ADDR Row (HEX) Column (HEX) 0000 000 000 0001 FFF FFF 0010 0C0 0C0 0011 000 100 0100 000 000 0101 100 101 0110 000 000 0111 200 201 1000 000 000 1001 000 000 1010 000 000 1011 000 000 1100 000 000 1101 000 000 1110 006 006 1111 007 007 Video Imaging Products 2-7 08/16/2000-LDS.2301-H LF2301 DEVICES INCORPORATED Image Resampling Sequencer TABLE 6. ITS OUTPUTS FOR 3 x 3 STATIC FILTER Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 x 6 6 6 6 7 7 6 5 5 5 6 7 7 8 8 7 6 6 6 7 8 8 9 9 8 7 7 7 8 9 6 7 7 6 5 5 5 6 7 7 8 8 7 6 6 6 7 8 8 9 9 8 7 7 7 8 9 6 y 6 6 6 6 6 7 7 7 6 5 5 5 6 6 7 7 7 6 5 5 5 6 6 7 7 7 6 5 5 5 7 7 8 8 8 7 6 6 6 7 7 8 8 8 7 6 6 6 7 7 8 8 8 7 6 6 6 6 CAx (HEX) 00 00 00 00 01 02 03 04 05 06 07 08 00 01 02 03 04 05 06 07 08 00 01 02 03 04 05 06 07 08 00 01 02 03 04 05 06 07 08 00 01 02 03 04 05 06 07 08 00 01 02 03 04 05 06 07 08 00 CAy (HEX) 00 00 00 00 01 02 03 04 05 06 07 08 00 01 02 03 04 05 06 07 08 00 01 02 03 04 05 06 07 08 00 01 02 03 04 05 06 07 08 00 01 02 03 04 05 06 07 08 00 01 02 03 04 05 06 07 08 00 u x x x x x x x x x x x x 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 8 8 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 8 v x x x x x x x x x x x x 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 INIT 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACC 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 UWRI 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 ENDx 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 ENDy 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 DONE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 Video Imaging Products 2-8 08/16/2000-LDS.2301-H LF2301 DEVICES INCORPORATED Image Resampling Sequencer spiral walk on the second line should be (-0.5,0.866), dx/dv is selected to be -0.5 and dy/dv is selected to be 0.866. Second order differential terms are not used in this transform and are therefore set to 0. It is important to note that the integer portion of the address generated in the LF2301 is used as the X or Y pixel address. The fractional portion (sub-pixel portion) is used as the coefficient RAM address. UMIN and VMIN are both selected to be 0. UMAX and VMAX are both selected to be 2. Table 7 shows the values loaded into all Parameter Registers. Table 8 shows the ITS outputs for this example. Image Rotation & Bilinear Interpolation Figure 8 shows an example of rotating an image 30 and using bilinear interpolation. This mode is selected by loading M1-0 with "00" for a clockwise spiral walk. A counterclockwise spiral walk could be selected by loading M1-0 with "10." Bilinear interpolation requires a kernel size of 2 x 2 pixels. Loading K3-0 with "0001" selects a kernel size of 2 x 2. The first pixel selected is determined by x0 and y0. In this example, the first pixel is (0,0). In this case, the LF2301s should address consecutive pixels during each spiral walk. For this to occur, FOV must be set to 1 (F2-0 loaded with "001"). After the last pixel of a spiral walk has been selected, the next pixel address is determined by adding dx/du to the current X address and by adding dy/du to the current Y address (unless the kernel just completed was the last for that line). At the end of the first spiral walk, pixel (0,1) is addressed. Since the next calculated pixel should be (0.866,0.5), dx/du is selected to be 0.866 and dy/du is selected to be 0.5. However, after adding dx/du and dy/du to the X and Y addresses respectively, the generated address is (0.866,1.5). The Y address is off by a value of 1. This is due to the fact that the last pixel address of a spiral walk is used to calculate the first pixel address of the next spiral walk. In order for the LF2301s to generate the correct result, dy/du must be modified by subtracting a 1 from it. The correct value of dy/du is -0.5. Figure 6 shows how the unmodified differential terms were calculated. After the last pixel of the last spiral walk on the first line has been selected, the first pixel address of the second line is determined by adding dx/dv to x0 and by adding dy/dv to y0. Since the first calculated pixel of the first FIGURE 8. 30 IMAGE ROTATION -1 0 5 0 1,2 1 2 3 1 3 4 2 3 4 1 = 1st pixel of 1st spiral walk, 2 = 1st pixel of 2nd spiral walk, etc. source image pixels calculated pixels FIGURE 6. DIFFERENTIAL TERMS dx = cos 30 = 0.866 du dy = sin 30 = 0.5 du dx = -sin 30 = -0.5 dv dy = cos 30 = 0.866 dv TABLE 7. PARAMETER REGISTERS ADDR Row (HEX) Column (HEX) 0000 000 000 0001 FFF FFF 0010 000 000 0011 000 100 0100 DDB 800 0101 100 1FF 0110 800 DDB 0111 1FF 100 1000 000 000 1001 000 000 1010 000 000 1011 000 000 1100 000 000 1101 000 000 1110 000 000 1111 002 002 FIGURE 7. 30 IMAGE ROTATION dx dv dx du len dy dv x gth 30 =1 dy du u v y source image pixels calculated pixels Video Imaging Products 2-9 08/16/2000-LDS.2301-H LF2301 DEVICES INCORPORATED Image Resampling Sequencer TABLE 8. ITS OUTPUTS FOR 30 IMAGE ROTATION WITH BILINEAR INTERPOLATION Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 x 0 0 0 0 1 1 0 0 1 1 0 1 2 2 1 2 3 3 2 -1 0 0 -1 0 1 1 0 1 2 2 1 2 3 3 2 -1 0 0 -1 -1 0 0 -1 0 1 1 0 1 2 2 1 0 1 1 0 y 0 0 0 0 0 1 1 0 0 1 1 1 1 2 2 1 1 2 2 0 0 1 1 1 1 2 2 1 1 2 2 2 2 3 3 1 1 2 2 2 2 3 3 2 2 3 3 3 3 4 4 0 0 1 1 CAx (HEX) 00 00 00 00 01 02 03 D0 D1 D2 D3 B0 B1 B2 B3 90 91 92 93 80 81 82 83 50 51 52 53 30 31 32 33 10 11 12 13 00 01 02 03 D0 D1 D2 D3 B0 B1 B2 B3 90 91 92 93 00 01 02 03 CAy (HEX) 00 00 00 00 01 02 03 80 81 82 83 00 01 02 03 80 81 82 83 D0 D1 D2 D3 50 51 52 53 D0 D1 D2 D3 50 51 52 53 B0 B1 B2 B3 30 31 32 33 B0 B1 B2 B3 30 31 32 33 00 01 02 03 u x x x x x x x 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 v x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 INIT 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACC 0 0 0 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 UWRI 1 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 ENDx 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 ENDy 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 DONE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 Video Imaging Products 2-10 08/16/2000-LDS.2301-H LF2301 DEVICES INCORPORATED Image Resampling Sequencer FIGURE 9. PASS 1 OF TWO-PASS 0 -1 1 2 3 Pass 1 of Two-Pass Operation Pass 1 of the two-pass operation performs horizontal filtering on an image as shown in Figure 9. This mode is selected by loading M1-0 with "01." In this example, a horizontal filter with a kernel size of 3 pixels is desired. Loading K3-0 with "0010" selects a kernel size of 3. The first pixel selected is determined by x0 and y0. In this example, the first pixel is (0,0). In this case, the LF2301s should address consecutive pixels during each pixel walk. For this to occur, FOV must be set to 1 (F2-0 loaded with "001"). After the last pixel of a pixel walk has been selected, the next pixel address is determined by adding dx/du to the current X address and by adding dy/ du to the current Y address (unless the kernel just completed was the last for that line). At the end of the first pixel walk, pixel (2,0) is addressed. Since the first pixel of the next pixel walk should be (1,0), dx/du is selected to be -1 and dy/du is selected to be 0. After the last pixel of the last pixel walk on the first line has been selected, the first TABLE 9. PARAMETER REGISTERS ADDR Row (HEX) Column (HEX) 0000 000 000 0001 FFF FFF 0010 000 000 0011 040 140 0100 000 000 0101 1FF 000 0110 000 000 0111 200 201 1000 000 000 1001 000 000 1010 000 000 1011 000 000 1100 000 000 1101 000 000 1110 005 005 1111 006 006 UMIN and VMIN are both selected to be 5. UMAX and VMAX are both selected to be 6. Table 9 shows the values loaded into all Parameter Registers. Table 10 shows the ITS outputs for the Pass 1 of a Two-Pass operation. 1 2 3 4 0 4 5 6 1 7 2 3 1 = 1st pixel of 1st walk, 2 = 1st pixel of 2nd walk, etc. pixel address of the second line is determined by adding dx/dv to x0 and by adding dy/dv to y0. Since the first pixel of the first pixel walk on the second line should be (0,1), dx/dv is selected to be 0 and dy/dv is selected to be 1. Second order differential terms are not used in this filter and are therefore set to 0. TABLE 10. ITS OUTPUTS FOR PASS 1 OF TWO-PASS Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 x 0 0 0 0 1 2 1 2 3 2 3 4 0 1 2 1 2 3 2 3 4 0 1 2 y 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 CAx (HEX) 00 00 00 00 01 02 00 01 02 00 01 02 00 01 02 00 01 02 00 01 02 00 01 02 CAy (HEX) 00 00 00 00 01 02 00 01 02 00 01 02 00 01 02 00 01 02 00 01 02 00 01 02 u x x x x x x 5 5 5 6 6 6 7 7 7 5 5 5 6 6 6 7 7 7 v x x x x x x 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 INIT 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACC 0 0 0 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 UWRI 1 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 ENDx 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 ENDy 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 DONE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 Video Imaging Products 2-11 08/16/2000-LDS.2301-H LF2301 DEVICES INCORPORATED Image Resampling Sequencer FIGURE 10. PASS 2 OF TWO-PASS -1 0 0 1 Pass 2 of Two-Pass Operation Pass 2 of the two-pass operation performs vertical filtering on an image as shown in Figure 10. This mode is selected by loading M1-0 with "11." In this example, a vertical filter with a kernel size of 3 pixels is desired. Loading K3-0 with "0010" selects a kernel size of 3. The first pixel selected is determined by x0 and y0. In this example, the first pixel is (0,0). In this case, the LF2301s should address consecutive pixels during each pixel walk. For this to occur, FOV must be set to 1 (F2-0 loaded with "001"). After the last pixel of a pixel walk has been selected, the next pixel address is determined by adding dx/du to the current X address and by adding dy/du to the current Y address (unless the kernel just completed was the last for that line). At the end of the first pixel walk, pixel (0,2) is addressed. Since the first pixel of the next pixel walk should be (1,0), dx/du is selected to be 1 and dy/du is selected to be -2. After the last pixel of the last pixel walk on the first line has been TABLE 11. PARAMETER REGISTERS ADDR Row (HEX) Column (HEX) 0000 000 000 0001 FFF FFF 0010 000 000 0011 0C0 1C0 0100 000 000 0101 101 1FE 0110 000 000 0111 200 201 1000 000 000 1001 000 000 1010 000 000 1011 000 000 1100 000 000 1101 000 000 1110 005 005 1111 006 006 UMIN and VMIN are both selected to be 5. UMAX and VMAX are both selected to be 6. Table 11 shows the values loaded into all Parameter Registers. Table 12 shows the ITS outputs for the Pass 2 of a Two-Pass operation. 1 2 2 3 3 1 4 5 2 3 4 1 = 1st pixel of 1st walk, 2 = 1st pixel of 2nd walk, etc. selected, the first pixel address of the second line is determined by adding dx/dv to x0 and by adding dy/dv to y0. Since the first pixel of the first pixel walk on the second line should be (0,1), dx/dv is selected to be 0 and dy/dv is selected to be 1. Second order differential terms are not used in this filter and are therefore set to 0. TABLE 12. ITS OUTPUTS FOR PASS 2 OF TWO-PASS Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 x 0 0 0 0 0 0 1 1 1 2 2 2 0 0 0 1 1 1 2 2 2 0 0 0 y 0 0 0 0 1 2 0 1 2 0 1 2 1 2 3 1 2 3 1 2 3 0 1 2 CAx (HEX) 00 00 00 00 01 02 00 01 02 00 01 02 00 01 02 00 01 02 00 01 02 00 01 02 CAy (HEX) 00 00 00 00 01 02 00 01 02 00 01 02 00 01 02 00 01 02 00 01 02 00 01 02 u x x x x x x 5 5 5 6 6 6 7 7 7 5 5 5 6 6 6 7 7 7 v x x x x x x 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 INIT 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACC 0 0 0 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 UWRI 1 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 ENDx 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 ENDy 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 DONE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 Video Imaging Products 2-12 08/16/2000-LDS.2301-H LF2301 DEVICES INCORPORATED Image Resampling Sequencer MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8) Storage temperature ........................................................................................................... -65C to +150C Operating ambient temperature ........................................................................................... -55C to +125C VCC supply voltage with respect to ground ............................................................................ -0.5 V to +7.0 V Input signal with respect to ground ............................................................................... -0.5 V to VCC + 0.5 V Signal applied to high impedance output ...................................................................... -0.5 V to VCC + 0.5 V Output current into low outputs ............................................................................................................. 25 mA Latchup current ............................................................................................................................... > 400 mA OPERATING CONDITIONS To meet specified electrical and switching characteristics Mode Active Operation, Commercial Active Operation, Military Temperature Range (Ambient) 0C to +70C -55C to +125C Supply Voltage 4.75 V VCC 5.25 V 4.50 V VCC 5.50 V ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4) Symbol VOH VOL VIH VIL IIX IOZ ICC1 ICC2 CIN COUT Parameter Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Current Output Leakage Current VCC Current, Dynamic VCC Current, Quiescent Input Capacitance Output Capacitance (Note 3) Test Condition VCC = Min., IOH = -2.0 mA VCC = Min., IOL = 4.0 mA Min 2.4 Typ Max Unit V 0.4 2.0 0.0 VCC 0.8 10 10 75 5 10 10 V V V A A mA mA pF pF Ground VIN VCC (Note 12) Ground VOUT VCC (Note 12) (Notes 5, 6) (Note 7) TA = 25C, f = 1 MHz TA = 25C, f = 1 MHz Video Imaging Products 2-13 08/16/2000-LDS.2301-H 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 *DISCONTINUED SPEED GRADE Symbol Symbol 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4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4 Min 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 543210987654321 6543210987654321 6543210987654321 6 Min DEVICES INCORPORATED MILITARY OPERATING RANGE (-55C to +125C) Notes 9, 10 (ns) COMMERCIAL OPERATING RANGE (0C to +70C) Notes 9, 10 (ns) SWITCHING CHARACTERISTICS tENA tDE tD tHI tH tS tPW tCYC tENA tDE tD tHI tH tS tPW tCYC tDIS tDIS Parameter Parameter Three-State Output Disable Delay (Note 11) Three-State Output Enable Delay (Note 11) Output Delay, END Output Delay Input Hold Time, INTER Input Hold Time Input Setup Time Clock Pulse Width Cycle Time Three-State Output Disable Delay (Note 11) Three-State Output Enable Delay (Note 11) Output Delay, END Output Delay Input Hold Time, INTER Input Hold Time Input Setup Time Clock Pulse Width Cycle Time 2-14 66 66 10 20 10 20 30 30 2 2 66* 66* Image Resampling Sequencer Max Max 20 35 35 20 35 35 45 45 Video Imaging Products Min Min 55 55 10 18 10 18 25 25 2 2 LF2301- 55* LF2301- 55 Max Max 18 27 27 18 27 27 37 37 Min Min 30 25 12 10 10 10 08/16/2000-LDS.2301-H 0 0 6 5 LF2301 30* 25 Max Max 18 18 20 18 15 15 20 18 LF2301 DEVICES INCORPORATED Image Resampling Sequencer SWITCHING WAVEFORMS: DATA INPUTS (PARAMETER STORAGE) tCYC tPW CLK tS P11-0 tH tPW B3-0 WEN LDR SWITCHING WAVEFORMS: DATA OUTPUTS AND CONTROL LINES tCYC tPW CLK tS NOOP tS OETA tD X11-0, CA7-0 tDIS HIGH IMPEDANCE tPW tH tH tENA tDIS U11-0 tDIS UWRI CZERO, ACC, DONE tDE END tS INTER tHI HIGH IMPEDANCE tENA HIGH IMPEDANCE tENA Video Imaging Products 2-15 08/16/2000-LDS.2301-H LF2301 DEVICES INCORPORATED Image Resampling Sequencer NOTES 9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except tDIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max 2. The products described by this spec- respectively. Alternatively, a diode ification include internal circuitry de- bridge with upper and lower current signed to protect the chip from damagsources of IOH and IOL respectively, ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be cumulations of static charge. Neverthe- used. Parasitic capacitance is 30 pF less, conventional precautions should minimum, and may be distributed. be observed during storage, handling, and use of these circuits in order to This device has high-speed outputs caavoid exposure to excessive electrical pable of large instantaneous current stress values. pulses and fast turn-on/turn-off times. As a result, care must be exercised in the 3. This device provides hard clamping of testing of this device. The following transient undershoot and overshoot. In- measures are recommended: put levels below ground or above VCC will be clamped beginning at -0.6 V and a. A 0.1 F ceramic capacitor should be VCC + 0.6 V. The device can withstand installed between VCC and Ground indefinite operation with inputs in the leads as close to the Device Under Test range of -0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors tion will not be adversely affected, how- should be installed between device VCC ever, input current levels will be well in and the tester common, and device ground and tester common. excess of 100 mA. 4. Actual test conditions may vary from b. Ground and VCC supply planes those designated but operation is guar- must be brought directly to the DUT anteed as specified. socket or contactor fingers. 5. Supply current for a given applica- c. Input voltages should be adjusted to tion can be accurately approximated by: compensate for inductive ground and VCC noise to maintain required DUT inNCV2 F put levels relative to the DUT ground pin. 4 where 10. Each parameter is shown as a minimum or maximum value. Input requirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the external system 6. Tested with no output load at must supply at least that much time to meet the worst-case requirements of all 15 MHz clock rate. parts. Responses from the internal cir7. Tested with all inputs within 0.1 V of cuitry are specified from the point of view VCC or Ground, no load. of the device. Output delay, for example, 8. These parameters are guaranteed is specified as a maximum since worstcase operation of any device always probut not 100% tested. vides data within that time. N = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency 1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability. 11. For the tENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the 200mV level from the measured steady-state output voltage with 10mA loads. The balancing voltage, VTH, is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current. FIGURE A. OUTPUT LOADING CIRCUIT DUT S1 IOL CL IOH VTH FIGURE B. THRESHOLD LEVELS tENA OE Z 0 1.5 V 1.5 V 1.5 V tDIS 3.5V Vth VOL* 0.2 V 0 1 Z Z 1.5 V VOH* 0.2 V Z 1 0V Vth VOL* Measured VOL with IOH = -10mA and IOL = 10mA VOH* Measured VOH with IOH = -10mA and IOL = 10mA Video Imaging Products 2-16 08/16/2000-LDS.2301-H LF2301 DEVICES INCORPORATED Image Resampling Sequencer ORDERING INFORMATION 68-pin GND XO CA7 CA6 CA5 CA4 CA3 CA2 GND VCC CA1 CA0 CZERO ACC UWRI U11 U10 X1 X2 X3 X4 X5 X6 X7 X8 GND X9 X10 X11 P11 P10 P9 P8 P7 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 Top View 53 52 51 50 49 48 47 46 45 26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 GND U9 U8 U7 U6 U5 U4 U3 GND U2 U1 U0 DONE END INTER OETA INIT Speed 0C to +70C -- COMMERCIAL SCREENING 55 ns 25 ns LF2301JC55 LF2301JC25 P6 P5 P4 P3 P2 P1 P0 CLK GND VCC NOOP LDR B0 B1 B2 B3 WEN Plastic J-Lead Chip Carrier (J2) Video Imaging Products 2-17 08/16/2000-LDS.2301-H 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-- COMMERCIAL SCREENING ORDERING INFORMATION 68-pin G H D C K E B A F L J OETA INIT GND U10 UWRI CZERO CA1 GND CA3 END INTER U9 U7 U5 U3 U2 U0 DONE 1 WEN GND U11 ACC U1 U8 U6 U4 2 B2 B3 3 Ceramic Pin Grid Array (G1) Discontinued Package (i.e., Component Side Pinout) CA0 VCC B1 B0 NOOP GND 4 2-18 Through Package LDR VCC 5 Top View CA2 6 CLK CA4 P0 7 CA6 CA5 P2 P1 8 Image Resampling Sequencer CA7 X0 P4 P3 9 GND GND X10 P11 10 X7 X1 X3 X5 P9 P6 P5 Video Imaging Products X11 P10 11 P7 X2 X4 X6 X8 X9 P8 08/16/2000-LDS.2301-H LF2301 |
Price & Availability of LF2301
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