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ISL59444
Data Sheet September 21, 2005 FN7451.1
1GHz, 4 x 1 Multiplexing Amplifier with Synchronous Controls
The ISL59444 is a single-output 4:1 MUX-amp. The MUX-amp has a fixed gain of 1 and a 1GHz bandwidth. The ISL59444 is ideal for professional video switching, HDTV, computer display routing, and other high performance applications. The device contains logic inputs for channel selection (S0, S1), latch control signals (LE1, LE2), and a three-state output control (HIZ) for individual selection of MUX amps that share a common video output line. All logic inputs have pull-downs to ground and may be left floating.
TABLE 1. TRUTH TABLE LE1/LE2 0 0 0 0 X HIZ 0 0 0 0 1 S1 0 0 1 1 X S0 0 1 0 1 X OUT IN0 IN1 IN2 IN3 HiZ
Features
* 1GHz (-3dB) Bandwidth (VOUT = 200mVP-P) * 220MHz (-3dB) Bandwidth (VOUT = 2VP-P) * Slew Rate (RL = 500, VOUT = 4V) . . . . . . . . . . . .1515V/s * Slew Rate (RL = 500, VOUT = 5V) . . . . . . . . . . . . 1155V/s * High Speed Three-State Output (HIZ) * Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
* HDTV/DTV Analog Inputs * Video Projectors * Computer Monitors * Set-top Boxes * Security Video * Broadcast Video Equipment * RGB Video Distribution Systems
Ordering Information
PART NUMBER ISL59444IB ISL59444IB-T7 ISL59444IB-T13 ISL59444IBZ (Note) ISL59444IBZ-T13 (Note) ISL59444IBZ-T7 (Note)
SO16 (0.150")
* RF Switching and Routing Pinout ISL59444 (16 LD SO)
TOP VIEW
IN0 1 NIC 2 IN1 3 GND 4 IN2 5 NIC 6 16 V+ 15 S0 14 S1 13 HIZ 12 OUT 11 LE2 10 LE1 9 V-
PART TAPE & MARKING PACKAGE REEL 59444IB 59444IB 59444IB 16 Ld SO 16 Ld SO 16 Ld SO 7" 13" 7" 13"
PKG. DWG. # MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027
59444IBZ 16 Ld SO (Pb-free) 59444IBZ 16 Ld SO (Pb-free) 59444IBZ 16 Ld SO (Pb-free)
IN3 7 NIC 8
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Functional Diagram
EN0 EN1 S0 S1 HIZ DECODE EN2 DL Q C DL Q C DL Q C DL Q C DL Q C DL Q C DL Q C DL Q C IN0 IN1 IN2 IN3 OUT
Timing Diagram
LE1 LE2 S0, S1, HIZ OUT CHX CHX CHY CHZ CHY CHX CHX CHZ CHZ
EN3 LE1 LE2 100k
100k
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2005. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL59444
Absolute Maximum Ratings (TA = 25C)
Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.5V, V+ +0.5V Supply Turn-on Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/s Digital & Analog Input Current (Note 1) . . . . . . . . . . . . . . . . . . 50mA Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7). . . . . .3kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Operating Junction Temperature . . . . . . . . . . . . . . .-40C to +125C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER GENERAL IS
V+ = +5V, V- = -5V, GND = 0V, TA = 25C, RL = 500 to GND, VHIZ = 0.8V, Unless Otherwise Specified DESCRIPTION CONDITIONS MIN TYP MAX UNIT
Supply Current (VOUT = 0V)
No load, VHIZ = 0.8V No load, VHIZ = 2.0V
14.5 12.5 3.2
18 16 3.44
20 18
mA mA V
VOUT IOUT VOS Ib Rout
Positive and Negative Output Swing Output Current Output Offset Voltage Input Bias Current Output Resistance
VIN = 3.5V, RL = 500 RL = 10 to GND
80
-2
120
9 -2.5 1.4 0.2 10
180
20 -1
mA mV A M M
VIN = 0V HIZ = logic high, (DC), AV = 1 HIZ = logic low, (DC), AV = 1
-5
RIN ACL or AV ITRI LOGIC VH VL IIH IIL tLE AC GENERAL -3dB BW
Input Resistance Voltage Gain Output Current in Three-state
VIN = 3.5V VIN = 1.5V, RL = 500 VOUT = 0V 0.999 -35
1.001 6
1.003 +35
V/V A
Input High Voltage (Logic Inputs) Input Low Voltage (Logic Inputs) Input High Current (Logic Inputs) Input Low Current (Logic Inputs) LE1, LE2 Minimum Pulse Width
2 0.8 50 -10 4 150 5 -
V V A A ns
-3dB Bandwidth
VOUT = 200mVP-P, CL = 1.6pF VOUT = 2VP-P, CL = 23.6pF, RS = 25
1.0 230 80 50 0.01 0.02
GHz MHz MHz MHz %
0.1dB BW
0.1dB Bandwidth
VOUT = 200mVP-P, CL = 1.6pF VOUT = 2VP-P, CL = 23.6pF, RS = 25
dG dP
Differential Gain Error Differential Phase Error
NTSC-7, RL = 150 NTSC-7, RL = 150
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FN7451.1 September 21, 2005
ISL59444
Electrical Specifications
PARAMETER +SR Slew Rate V+ = +5V, V- = -5V, GND = 0V, TA = 25C, RL = 500 to GND, VHIZ = 0.8V, Unless Otherwise Specified (Continued) DESCRIPTION CONDITIONS 25% to 75%, VOUT = 5V, RL = 500, CL = 23.6pF, RS = 25 25% to 75%, VOUT = 5V, RL = 500, CL = 23.6pF, RS = 25 DC, PSRR V+ and V- combined V = 4.5V to 5.5V f = 10MHz, Ch-Ch X-Talk and Off Isolation, CL = 1.6pF -50 MIN TYP 1515 MAX UNIT V/s
-SR
Slew Rate
1155
V/s
PSRR ISO
Power Supply Rejection Ratio Channel Isolation
-57 75
dB dB
SWITCHING CHARACTERISTICS VGLITCH Channel-to-Channel Switching Glitch HIZ Switching Glitch tSW-L-H tSW-H-L Channel Switching Time Low to High Channel Switching Time High to Low VIN = 0V, CL = 23.6pF, RS = 25 VIN = 0V, CL = 23.6pF, RS = 25 1.2V logic threshold to 10% movement of analog output 1.2V logic threshold to 10% movement of analog output 38 175 32 29 mVP-P mVP-P ns ns
TRANSIENT RESPONSE tr, tf Rise & Fall Time, 10% to 90% VOUT = 200mVP-P, CL = 1.6pF VOUT = 2VP-P, CL = 23.6pF, RS = 25 tS tPLH 0.1% Settling Time Propagation Delay - Low to High, 10% to 10% VOUT = 2VP-P, CL = 23.6pF, RS = 25 VOUT = 200mVP-P, CL = 1.6pF VOUT = 2VP-P, CL = 23.6pF, RS = 25 VOUT = 200mVP-P, CL = 1.6pF VOUT = 2VP-P, CL = 23.6pF, RS = 25 VOUT = 200mVP-P, CL = 1.6pF VOUT = 2VP-P, CL = 23.6pF, RS = 25 0.68 1.4 6.8 0.5 0.85 0.54 0.88 8.3 15.7 ns ns ns ns ns ns ns % %
tPHL
Propagation Delay- High to Low, 10% to 10%
OS
Overshoot
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FN7451.1 September 21, 2005
ISL59444 Typical Performance Curves VS = 5V, RL = 500 to GND, TA = 25C, unless otherwise specified.
5 4 3 NORMALIZED GAIN (dB) 2 1 0 -1 -2 -3 -4 CL INCLUDES 1.6pF BOARD CAPACITANCE 0.01 0.1 1 1.5 CL = 5.5pF CL = 9.7pF CL = 7.2pF VOUT = 200mVP-P NORMALIZED GAIN (dB) 5 4 3 2 1 0 -1 -2 -3 -4 -5 0.001 0.01 0.1 1 1.5 RL = 150 RL = 75 RL = 1k RL = 500 VOUT = 200mVP-P CL = 1.6pF
CL = 1.6pF
-5 0.001
FREQUENCY (GHz)
FREQUENCY (MHz)
FIGURE 1. SMALL SIGNAL GAIN vs FREQUENCY vs CL
FIGURE 2. SMALL SIGNAL GAIN vs FREQUENCY vs RL
5 4 NORMALIZED GAIN (dB) 3 2 1 0 -1 -2 -3 -4 CL INCLUDES 1.6pF BOARD CAPACITANCE 0.01 CL = 28.6pF 0.1 1 1.5 CL = 16.6pF CL = 23.6pF CL = 11.6pF VOUT = 2VP-P RS = 25 NORMALIZED GAIN (dB)
5 4 3 2 1 0 -1 -2 -3 -4 -5 0.001 0.01 RL = 500 RL = 1k 0.1 1 1.5 RL = 150 RL = 75 VOUT = 2VP-P CL = 23.6pF RS = 25
-5 0.001
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 3. LARGE SIGNAL GAIN vs FREQUENCY vs CL
FIGURE 4. LARGE SIGNAL GAIN vs FREQUENCY vs RL
0.5 0.4 0.3 NORMALIZED GAIN (dB) 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 CL INCLUDES 1.6pF BOARD CAPACITANCE 0.01 CL = 1.6pF CL = 7.2pF CL = 5.5pF VOUT = 200mVP-P CL = 9.7pF
0.5 0.4 NORMALIZED GAIN (dB) 0.3 0.2 0.1 0 -0.1 -0.2 RL = 150 -0.3 -0.4 1 1.5 -0.5 0.001 RL = 75 0.01 0.1 1 1.5 RL = 1k RL = 500 VOUT = 200mVP-P CL = 1.6pF
-0.5 0.001
0.1
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 5. SMALL SIGNAL 0.1dB GAIN vs FREQUENCY vs CL
FIGURE 6. SMALL SIGNAL 0.1dB GAIN vs FREQUENCY vs RL
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FN7451.1 September 21, 2005
ISL59444 Typical Performance Curves VS = 5V, RL = 500 to GND, TA = 25C, unless otherwise specified.
0.2 0.1 NORMALIZED GAIN (dB) CL = 11.6pF NORMALIZED GAIN (dB) 0 -0.1 -0.2 -0.3 CL = 16.6pF -0.4 -0.5 -0.6 -0.7 CL INCLUDES 1.6pF BOARD CAPACITANCE 0.01 CL = 28.6pF VOUT = 2VP-P RS = 25 CL = 23.6pF 5 4 3 2 1 0 RL = 75 -1 -2 -3 -4 1 1.5 -5 0.001 0.01 0.1 1 1.5 VOUT = 2VP-P CL = 23.6pF RS = 25 RL = 150
(Continued)
RL = 500 RL = 1k
-0.8 0.001
0.1
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 7. LARGE SIGNAL 0.1dB GAIN vs FREQUENCY vs CL
FIGURE 8. LARGE SIGNAL 0.1dB GAIN vs FREQUENCY vs RL
-10
20 10 0 -10 PSRR (dB) (dB) -20 -30 -40 -50 -60 -70 -80 0.3 1 10 FREQUENCY (MHz) PSRR (V-) PSRR (V+) VIN = 200mVP-P CL = 23.6pF RS = 25
-20 -30 -40 -50 -60 -70 -80 -90 -100 -110 0.001
VIN = 1VP-P CL = 23.6pF RS = 25
CROSSTALK
OFF ISOLATION
100
1000
0.01
0.1
1
3
6 10
100
500
FREQUENCY (MHz)
FIGURE 9. PSRR CHANNELS
100 VOUT = 100mVP-P INPUT VOLTAGE NOISE (nV/Hz)
FIGURE 10. CROSSTALK AND OFF ISOLATION
60
RF = 500
50
OUTPUT RESISTANCE ()
10
40
30
1
20
10 0.1 0.1 0 0.1
1
10 FREQUENCY (MHz)
100
1000
1
10
100
FREQUENCY (kHz)
FIGURE 11. ROUT vs FREQUENCY
FIGURE 12. INPUT NOISE vs FREQUENCY
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FN7451.1 September 21, 2005
ISL59444 Typical Performance Curves VS = 5V, RL = 500 to GND, TA = 25C, unless otherwise specified.
(Continued)
S0, S1 1V/DIV 1V/DIV
S0, S1
0 20mV/DIV 500mV/DIV 0 VOUT
0 VOUT 0
20ns/DIV
20ns/DIV
FIGURE 13. CHANNEL TO CHANNEL SWITCHING GLITCH VIN = 0V, RS = 25, CL = 23.6pF
FIGURE 14. CHANNEL TO CHANNEL TRANSIENT RESPONSE VIN = 1V, RS = 25, CL = 23.6pF
HIZ 1V/DIV 1V/DIV
HIZ
0 100mV/DIV 500mV/DIV
0
0 VOUT
VOUT 0
20ns/DIV
20ns/DIV
FIGURE 15. HIZ SWITCHING GLITCH VIN = 0V, RS = 25, CL = 23.6pF
FIGURE 16. HIZ TRANSIENT RESPONSE VIN = 1V, RS = 25, CL = 23.6pF
160 120 OUTPUT VOLTAGE (mV) 80 40 0 -40 -80 -120 -160 TIME (4ns/DIV) CL = 1.6pF RL = 500 OUTPUT VOLTAGE (V)
2.4 2 1.6 1.2 0.8 0.4 0 -0.4 -0.8 CL = 23.6pF RS = 25 RL = 500 TIME (4ns/DIV)
FIGURE 17. SMALL SIGNAL TRANSIENT RESPONSE
FIGURE 18. LARGE SIGNAL TRANSIENT RESPONSE
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FN7451.1 September 21, 2005
ISL59444 Typical Performance Curves VS = 5V, RL = 500 to GND, TA = 25C, unless otherwise specified.
1.4 POWER DISSIPATION (W) 1.2 1 0.8 0.6 0.4 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C)
(Continued)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.250W POWER DISSIPATION (W)
SO 16
1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
JA
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD
909mW
(0 .1 =8 50 0 " C /W )
JA =
SO 16 11 0
15 0" ) C /W
(0 .
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (C)
FIGURE 19. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 20. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
Pin Descriptions
PIN NUMBER 1 2, 6, 8 3 4 5 7 9 10 PIN NAME IN0 NIC IN1 GND IN2 IN3 VLE1 Circuit 1 Circuit 4 Circuit 1 Circuit 1 Circuit 4 Circuit 2 EQUIVALENT CIRCUIT Circuit 1 Input for channel 0 Not Internally Connected; it is recommended this pin be tied to ground to minimize crosstalk. Input for channel 1 Ground pin Input for channel 2 Input for channel 3 Negative Power Supply Synchronized channel switching: When LE1 is low, the master control latch loads the next switching address. The Mux Amp is configured for this address when LE2 goes low. Synchronized operation results when LE2 is the inverse of LE1. Channel selection is asynchronous (changes with any control signal change) if both LE1 and LE2 are both low. Synchronized channel switching: When LE2 is low, the newly selected channel, stored in the master latch via LE1 is selected. Synchronized operation results when LE2 is the inverse of LE1. Channel selection is asynchronous (changes with any control signal change) if both LE1 and LE2 are both low. Output Output disable (active high); there are internal pull-down resistors, so the device will be active with no connection; "HI" puts the output in high impedance state. Channel selection pin MSB (binary logic code) Channel selection pin LSB (binary logic code) Positive power supply DESCRIPTION
11
LE2
Circuit 2
12 13 14 15 16
OUT HIZ S1 S0 V+
Circuit 3 Circuit 2 Circuit 2 Circuit 2 Circuit 4
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FN7451.1 September 21, 2005
ISL59444 Pin Descriptions (Continued)
PIN NUMBER PIN NAME EQUIVALENT CIRCUIT
V+
DESCRIPTION
V+ 21k + GND.
IN
1.2V
LOGICPIN 33k V-
V-
CIRCUIT 1
V+ V+ OUT GND VV-
CIRCUIT 2
CAPACITIVELY COUPLED ESD CLAMP
CIRCUIT 3
CIRCUIT 4
AC Test Circuits
ISL59444 VIN 50 or 75 CL 2pF RL 500 VIN 50 or 75 CL 2pF ISL59444 RS 475 50 or 75 TEST EQUIPMENT 50 or 75
FIGURE 21A. TEST CIRCUIT WITH OPTIMAL OUTPUT LOAD
FIGURE 21B. TEST CIRCUIT FOR MEASURING WITH A 50 OR 75 INPUT TERMINATED EQUIPMENT
ISL59444 VIN 50 or 75 CL 2pF RS 50 or 75
TEST EQUIPMENT 50 or 75
FIGURE 21C. BACKLOADED TEST CIRCUIT FOR VIDEO CABLE APPLICATION. BANDWIDTH AND LINEARITY FOR RL LESS THAN 500 WILL BE DEGRADED.
Figure 21A illustrates the optimum output load for testing AC performance. Figure 21B illustrates the optimum output load when connecting to input terminated equipment. Figure 21C illustrates back loaded test circuit for video cable.
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FN7451.1 September 21, 2005
ISL59444 Application Circuits
*CL = CT + COUT VIN 50 + CT 1.6pF COUT 0pF VOUT RL = 500
*CL: TOTAL LOAD CAPACITANCE CT: TRACE CAPACITANCE COUT: OUTPUT CAPACITANCE
FIGURE 22A. SMALL SIGNAL 200mVP-P APPLICATION CIRCUIT
VIN 50 + 1.6pF CT
RS 25 COUT 22pF
VOUT RL = 500
CL = CT + COUT
FIGURE 22B. LARGE SIGNAL 1VP-P APPLICATION CIRCUIT
Application Information
General
The ISL59444 is a 4:1 mux that is ideal as a matrix element in high performance switchers and routers. The ISL59444 is optimized to drive a 2pF in parallel with a 500 load. The capacitance can be split between the PCB capacitance an and external load capacitance. Their low input capacitance and high input resistance provide excellent 50 or 75 terminations.
Ground Connections
For the best isolation and crosstalk rejection, the GND pin and NIC pins must connect to the GND plane. The NIC pins are placed on both sides of the input pins. These pins are not internally connected to the die. It is recommended this pin be tied to ground to minimize crosstalk.
Control Signals
S0, S1, HIZ - These pins are, TTL/CMOS compatible control inputs. The S0, S1 pins select which one of the inputs connect to the output. The HIZ pin is used to three-state the output amplifiers. For control signal rise and fall times less than 10ns the use of termination resistors close to the part will minimize transients coupled to the output.
Capacitance at the Output
The output amplifier is optimized for capacitance to ground (CL) directly on the output pin. Increased capacitance causes higher peaking with an increase in bandwidth. The optimum range for most applications is ~1.0pF to ~6pF. The optimum value can be achieved through a combination of PC board trace capacitance (CT) and an external capacitor (COUT). A good method to maintain control over the output pin capacitance is to minimize the trace length (CT) to the next component, and include a discrete surface mount capacitor (COUT) directly at the output pin. For large signal applications where overshoot is important the circuit in Figure 22B should be used. The series resistor (RS) and capacitor (CL) form a low pass network that limits system bandwidth and reduces overshoot. The component values shown result in a typical pulse response shown in Figure 18.
HIZ State
An internal pull-down resistor connected to the HIZ pin ensures the device will be active with no connection to the HIZ pin. The HIZ state is established within approximately 30ns by placing a logic high (>2V) on the HIZ pin. If the HIZ state is selected, the output is a high impedance 1.4M. Use this state to control the logic when more than one mux shares a common output. In the HIZ state the output is three-stated, and maintains its high Z even in the presence of high slew rates. The supply current during this state is basically the same as the active state.
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FN7451.1 September 21, 2005
ISL59444
Latch State
The latched control signals allow for synchronized channel switching. When LE1 is low the master control latch loads the next switching address (S0, S1), while the closed (assuming LE2 is the inverse of LE1) slave control latch maintains the current state. LE2 switching low closes the master latch (with previous assumption), loads the now open slave latch, and switches the crosspoint to the newly selected channel. Channel selection is asynchronous (changes with any control signal change) if both LE1 and LE2 are low.
PC Board Layout
The frequency response of this circuit depends greatly on the care taken in designing the PC board. The following are recommendations to achieve optimum high frequency performance from your PC board. * The use of low inductance components such as chip resistors and chip capacitors is strongly recommended. * Minimize signal trace lengths. Trace inductance and capacitance can easily limit circuit performance. Avoid sharp corners, use rounded corners when possible. Vias in the signal lines add inductance at high frequency and should be avoided. PCB traces greater than 1" begin to exhibit transmission line characteristics with signal rise/fall times of 1ns or less. High frequency performance may be degraded for traces greater than one inch, unless strip lines are used. * Match channel-channel analog I/O trace lengths and layout symmetry. This will minimize propagation delay mismatches. * Maximize use of AC de-coupled PCB layers. All signal I/O lines should be routed over continuous ground planes (i.e. no split planes or PCB gaps under these lines). Avoid vias in the signal I/O lines. * Use proper value and location of termination resistors. Termination resistors should be as close to the device as possible. * When testing use good quality connectors and cables, matching cable types and keeping cable lengths to a minimum. * Minimum of 2 power supply de-coupling capacitors are recommended (1000pF, 0.01F) as close to the devices as possible. Avoid vias between the cap and the device because vias add unwanted inductance. Larger caps can be farther away. When vias are required in a layout, they should be routed as far away from the device as possible. * The NIC pins are placed on both sides of the input pins. These pins are not internally connected to the die. It is recommended these pins be tied to ground to minimize crosstalk.
Power-Up Considerations
The ESD protection circuits use internal diodes from all pins the V+ and V- supplies. In addition, a dv/dt triggered clamp is connected between the V+ and V- pins, as shown in the Equivalent Circuits 1 through 4 section of the Pin Description table. The dv/dt triggered clamp imposes a maximum supply turn-on slew rate of 1V/s. Damaging currents can flow for power supply rates-of-rise in excess of 1V/s, such as during hot plugging. Under these conditions, additional methods should be employed to ensure the rate of rise is not exceeded. Consideration must be given to the order in which power is applied to the V+ and V- pins, as well as analog and logic input pins. Schottky diodes (Motorola MBR0550T or equivalent) connected from V+ to ground and V- to ground (Figure 23) will shunt damaging currents away from the internal V+ and V- ESD diodes in the event that the V+ supply is applied to the device before the V- supply. If positive voltages are applied to the logic or analog video input pins before V+ is applied, current will flow through the internal ESD diodes to the V+ pin. The presence of large decoupling capacitors and the loading effect of other circuits connected to V+, can result in damaging currents through the ESD diodes and other active circuits within the device. Therefore, adequate current limiting on the digital and analog inputs is needed to prevent damage during the time the voltages on these inputs are more positive than V+.
Limiting the Output Current
No output short circuit current limit exists on these parts. All applications need to limit the output current to less than 50mA. Adequate thermal heat sinking of the parts is also required.
V+ SUPPLY LOGIC POWER GND SIGNAL DE-COUPLING CAPS V- SUPPLY SCHOTTKY PROTECTION S0 GND IN0 IN1 VVVV+ VV+
V+
V+ LOGIC CONTROL V+ OUT V-
EXTERNAL CIRCUITS
FIGURE 23. SCHOTTKY PROTECTION CIRCUIT
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FN7451.1 September 21, 2005
ISL59444 SO Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 11
FN7451.1 September 21, 2005

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