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TC94A23F
Toshiba CMOS Digital Integrated Circuit Silicon Monolithic
TC94A23F
Single-chip CD Processor with Built-in Controller
TC94A23F is a single-chip CD processor for digital servo. It incorporates a 4-bit microcontroller. The controller features an LCD/LED driver, 4-channel 6-bit AD converter, 2/3-line serial interface, buzzer, interrupt function, and 8-bit timer/counter. The CPU can select one of three crystal oscillator operating clocks (16.9344 MHz, 4.5 MHz, and 75 kHz), facilitating interface with the CD processor. The CD processor incorporates sync separation protection and interpolation, EFM decoder, error correction, digital equalizer for servo, and servo controller. The CD processor also incorporates a 1-bit DA converter. In combination with RF amp TA2153FN or TA2109F, TC94A23F can very simply configure an Weight: 1.6 g (typ.) adjustment-free CD player. Thus, the IC is suitable for CD systems for automobiles and radio-cassette players.
Features
* * * Single-chip CD processor with built-in CMOS LCE/LED driver and 4-bit microcontroller Operating voltage: At CD on: VDD = 4.5 to 5.5 V (typ. 5.0 V) Current dissipation: At CD off: VDD = 3.0 to 5.5 V (only CPU on) At CD on: IDD = 50 mA (typ.) At CD off: IDD = 2 mA (with 4.5 MHz crystal oscillator, only CPU on) At CD off: IDD = 0.3 mA (with 75 kHz crystal oscillator, only CPU on) * * * Operating temperature range: Ta = -40~85C Package: QFP100-P-1420-0.65A (0.65-mm pitch, 2.7-mm thick) One-time PROM version: TC94AP09F
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TC94A23F
4-bit Microcontroller
* * * * * * * * * Program memory (ROM): 16-bit 8k-step Data memory (RAM): 4-bit 512-word Instruction execution time: 1.89/1.78/40 ms (all one-word instructions) Crystal oscillator frequency: 16.9344 MHz/4.5 MHz/75 kHz Stack level: 8 AD converter: 6-bit 4-channel LCD driver: 1/4 duty, 1/2 or 1/3 bias method, 72 segments max LED driver: 4-digit 14-segment (max), also used as LCD driver switched by software I/O port: CMOS I/O port: 16 N-channel open drain I/O port: 4 (max) Output-only port: 4 (max), also used as CD processor pins Input-only port: 4 Timer/counter: 8 bit (INTR, instruction cycle, 100/1 kHz selectable as timer clock) 10, 100, or 500 Hz: internal port 2 Hz: Flip-flop port Serial interface: Supports 2/3-line method (data length: 4 or 8 bits) Buzzer: Four types: 0.75, 1, 1.5, and 3 kHz Four modes: Continuous, Single-Shot, 10 Hz Intermittent, and 10 Hz Intermittent at 1 Hz Interval) Interrupt: 1 external, 3 internal (CD sub-sync, serial interface, 8-bit timer) Back-up mode: three types Clock Stop (crystal oscillator off) Hardware Wait (crystal oscillator on but CPU in operation) Software Wait (CPU in intermittent operation) Reset function: Power-on reset, built-in supply voltage detector (detection voltage = 2.5 V typ.)
*
* * * *
*
CD Processor
* * * Reliable sync pattern detection, sync signal protection and interpolation Built-in EFM decoder and sub code decoder High-correction capability using cross interleave read Solomon code (CIRC) logical equation C1 correction: dual C2 correction: quadruple Supports variable speeds. Jitter absorption capability of 6 frames Built-in 16 KB RAM Built-in digital output circuit Built-in L/R independent digital attenuators Bilingual audio output (Note) Sub code Q data are read-timing free and can be output in sync with audio data. (Note) Built-in data slice and analog PLL (adjustment-free VCO used) circuit Auto adjustment of loop gain, offset, and balance at focus servo and tracking servo RF gain auto adjustment circuit Built-in digital equalizer for phase compensation Supports different pickups using built-in digital equalizer coefficient RAM. Built-in focus and tracking servo control circuit Search control supports all modes and realizes high-speed, stable search. Lens kick and feed kick use speed control method. Built-in AFC circuit and APC circuit for disc motor CLV servo. Built-in defect/shock detector Built-in 8 times oversampling digital filter and 1-bit DA converter. Output pins for sub code Q data and audio data are also used as LCD driver pins. The function of the pins can be switched by program.
* * * * * * * * * * * * * * * * * *
Note:
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TC94A23F
Pin Connections
SLCO PVREF 2VREF RFGC VCOF SBAD RFRP TEBC RFCT
XVDD
AVDD
LPFO * A
VSS
RFI
XO
XI
M 80 DVSR * M RO * DVRR * R DVDD * M DVRL * R LO * DVSL * M TESTM IN2/(VPP)
RST
M
* 3
* 3 75
* 3
* R
* 3
* 3
* 3 70
* 3
* R
* A
* A
* A 65
* A
* A
* A
* A
* A 60
* A
* 3
* A
* A
* 3 55
* A
* R
51 50 3 * TMAX 3 * PDO R * P2VREF M * VSS
81
CD processor input/output
85 45
LPFN * A
XVSS
VREF
DMO
FMO
VDD
SEL
RFZI
FOO
TEZI
TRO
TEI
FEI
AVSS
M*V DD * SBOK * SBSY * DOUT M * OT22 (COFS)
M Controller test input M M M M M OSC M M M M M M M 100 LCD driver/LED driver output port (LCD: 4 18 = 72 segments max, LED: 18 segments) 1 M S1 (OT5) M S2 (OT6) M S3 (OT7) M S4 (OT8) 5 M S5 (OT9) M S6 (OT10) M S7 (OT11) M S8 (OT12) M S9 (OT13) 10 M S10 (OT14/ZDET) M S11 (OT15/CLCK) M S12 (OT16/DATA) M S13 (OT17/SFSY) M S14 (OT18/LRCK) 15 M P8-0 (S15/BCK) M P8-1 (S16/AOUT) M P8-2 (OT17/MBOV) M P8-3 (OT18/IPF) M MVDD Power supply to controller 20 M MVSS M P1-0 M P1-1 M P1-2 M P1-3 I/O ports (16) 25 M P3-0 M P3-1 (ADin1) M P3-2 (ADin2) M P3-3 (ADin3) M P4-0 (ADin4/BUZR) 30 M P4-1 (SI2) 95 Power supply to controller 90 Reset input Hold input Interrupt input CD test input TC94A23F (QPF100 pin)
M * OT21 (SPDA) 40 M * OT20 (SPCK) M * OT19 ( HSO ) M M M 35 M M M M 31 M CD function pins switched TESTC IN1 (BCKin) P2-3 (DATAin) P2-2 (LRCKin) P2-1 ( HSO in) P2-0 (EMPHin) P4-3 (SCK/SCL) P4-2 (SI0/SI1/SDA)
HOLD
INTR MXO MXI MVSS MVDD COM1 (OT1) COM2 (OT2) COM3 (OT3) COM4 (OT4)
CD function pins switched together
Note:
Symbols used for the pins above indicate the following pin functions.
* M 3 A R M : CD processor-dedicated pin : Power supply pin : CD processor tri-state output pin : CD processor analog input/output pin : Reference input pin : Controller-dedicated pin
Note:
When the CD is off, the power supply pins for the controller (MVDD) and the power pins supply for the CD oscillator (XVDD) are on and the CD processor-dedicated power supply pins (indicated by asterisk *) are off.
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Block Diagram
2VREF RFGC SBAD TEBC RFRP
AVDD
AVSS VREF
VREF
DMO
TRO
SEL
XVSS XI XO XVDD X'tal OSC
Clock gene. PWM CD clock VREF DA Data slicer RFI SLCO
ZDET DVSR RO 1 bit DAC DVRR DVDD DVRL LO DVSL Sub code decoder LPF SERVO control VREF AD
RFCI
FMO
RFZI
FOO
TEZI
TEI
FEI
PLL TMAX
TMAX PDO
P2VREF VCOF ROM RAM Digital equalizer Automatic adjustment circuit CLV servo Synchronous guarantee EFM decode VCO PVREF LPFO
LPFN SBOK Address VDD VSS P2-0~P2-3 IN1 CD Reset Audio out Digital out 16 k SRAM Correction circuit SBSY
DOUT
MXO X'tal OSC MXI P1-3 Port1 P1-0 Timer Data Reg (16 bit) SBSY Interrupt INTR Cont. Serial Interface P4-3 (SCK/SCL) P4-2 (SI0/SI1/SDA) Port4 P4-1 (SI2) P4-0 (ADin4/BUZR) Program Counter Instruction Decoder F/F BUZR Reset Stack Reg. (8Level) Power on Reset Port3 P3-1 (ADin1) P3-0 LCD Driver/Output Port Port8 Bias ZDET, CLCK, DATA, SFSY, LRCK, BCK, MBOV, IPF Port2 ROM (16 8192 Step) RAM (4 512 word) ALU G-Reg. R/W Buf. CPU clock SBSY CLCK, DATA, SFSY, LRCK, BCK, MBOV, IPF OT19-22 MPX Micon interface Reset
OT22 (COFS) OT21 (SPDA) OT20 (SPCK) OT19 ( HSO )
HOLD
TESTM TESTC
IN1 (BCKin) IN2
P2-0 (EMPHin) P2-1 ( HSO in) P2-2 (LRCKin) P2-3 (DATAin)
AD Conv. P3-3 (ADin3) P3-2 (ADin2)
RST
MVDD MVSS
P8-1 (S16/AOUT)
P8-0 (S15/BCK)
S10 (OT14/ZDET)
S11 (OT15/CLCK)
S12 (OT16/DATA)
S13 (OT17/SFSY)
4
S14 (OT18/LRCK)
P8-2 (S17/MBOV)
P8-3 (S18/IPF)
COM1 (OT1)
COM2 (OT2)
COM3 (OT3)
COM4 (OT4)
S1 (OT5)
S2 (OT6)
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Pin Function
Pin Number Symbol Pin Name Function and Operation Common signal output pins for the LCD panel. 97 COM1/OT1 Those pins configure matrix with S1 to S18 and display up to 72 segments. The LCD can be driven by the 1/2 or 1/3 bias method. When the 1/2 bias method is set, three levels, MVDD, 1/2MVDD, and GND, are output at 2-ms intervals at a 62.5 Hz cycle. When the 1/3 bias method is set, four levels, MVDD, 1/3MVDD, 2/3MVDD, and GND, are LCD common output output at 1-ms intervals at a 125 Hz cycle /output port (when either the 4.5 MHz or 75 kHz crystal oscillator is used). After system reset or clock stop execution is released, the non-selected waveform (bias voltage) is output. The DISP OFF bit is set to 0 and the common signal is output. These pins can be switched to an output port (Note 1) or LED driver pins by program. They are usually used for digit output to drive the LEDs. Remarks
MVDD
MVDD Bias voltage
98
COM2/OT2
99
COM3/OT3
100
COM4/OT4
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Pin Number Symbol Pin Name Function and Operation Segment signal output pins for the LCD panel. Those pins configure a matrix with COM1 to COM4 and display up to 72 segments. 1~9 S1/OT4 ~ S9/OT13 When the 1/2 bias method is set, two levels, LCD segment output MV DD and GND, are output. When the 1/3 /output port bias method is set four levels, MVDD, 1/3MVDD, 2/3MVDD, and GND, are output. The S1 to S14 pins can be switched to an output port (Note 1) by program. Port 8 and S15 to S18 pins can be switched pin by pin to an I/O port and segment output pins. When the pins are set to an I/O port, output is N-channel open drain. The S10 to S14 and P8-0 to P8-3 pins can be switched to CD signal input/output pins by program. Setting the CD10 bit to 1 switches the pins to the LRCK, BCK, and AOUT pins as the CD pins in batches. The other pins can be individually switched according to the S14/S15/S16 segment data. LCD segment output CLCK: Inputs/outputs sub code P to W data reading clock. /output port /CD signal DATA: Outputs sub code P to W data. SFSY: Outputs frame sync signal for playback. LRCK: Outputs channel clock (44.1 kHz). When L channel, outputs Low. When R channel, outputs High. The polarity can be inverted by command. BCK: Outputs bit clock (1.4112 MHz). MVDD Input instruction MVDD MVDD Bias voltage Remarks
10
S10/OT14 /ZDET
11
S11/OT15 /CLCK
12
S12/OT16 /DATA
MVDD
MVDD
13
S13/OT17 /SFSY
14
S14/OT18 /LRCK
AOUT: Outputs audio data. P8-0/S15 /BCK MBOV: Outputs buffer-memory-overflow signal. When buffer memory overflows, outputs H. IPF: 16 P8-1/S16 /AOUT Outputs interpolation pointing flag. If AOUT output is C2 error detection/correction, outputs High to indicate correction is impossible.
15
Bias voltage
17
P8-2/S17 /MBOV
I/O port ZDET: Outputs 1-bit DAC zero detection flag. /LCD segment output Pins set as an output port are used for /CD signal segment output for the LED driver. The output port can increment OT1 to OT18 by instruction, facilitating access to data in external RAM and ROM. (Note 1) After a system reset, pins also used as output ports are set to LCD output; pins also used as I/O ports are set to I/O port input.
18
P8-3/S18 /IPF
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Pin Number Symbol Pin Name Function and Operation Remarks
MVDD 4-bit CMOS I/O port. Input/output can be set for each bit by program. 21~24 P1-0~P1-3 I/O port 1 The pins can be set to be pulled-up or pulled-down by program. Thus, they can be used as key input pins. When the pins are set to I/O port input, Clock Stop mode and Wait mode can be released, according to the change in input to the pins. RIN1
MVDD
MVDD
5-bit CMOS I/O port. Input/output can be set for each bit by program. 25 P3-0 I/O port 3 P3-1 and P4-0 pins are also used as built-in 6-bit 4-channel A/D converter analog input pins. The built-in A/D converter uses successive approximation. The conversion time is 6 instruction cycles (280 ms) when the 75 kHz crystal oscillator is used; 198 ms when the 4.5 MHz crystal oscillator is used; 180 ms when the 16.9344 MHz crystal oscillator is used. A/D analog input can be set for each pin by program. The internal power supply (MVDD) is used as the reference voltage. The P4-0 pin is also used as the buzzer output pin. One of four frequencies: 0.75, 1, 1.5, and 3 kHz, can be selected for buzzer output. The buzzer is output at the selected frequency in one of four modes: Continuous, single-shot, 10 Hz intermittent, and 10 Hz intermittent at 1 Hz interval. Settings for the A/D converter and buzzer, and their control can be performed by program. 33 P2-0/EMPHin MVDD 34 P2-1/ HSO in I/O port 2 /1-bit DAC input 35 P2-2/LRCKin I/O port 2 is a 4-bit CMOS I/O port. IN1 and IN2 are a 2-bit general-purpose input port. Input/output can be set for each bit of I/O port 2 by program. I/O port 2 and the IN1 pins can be switched to 1-bit DAC input pins by the CD command to support shock-proofing. In this case, the I/O port must be set to input. General-purpose input port/1-bit DAC input (VPP input) 89 IN2/ (VPP) With the OTP version, the IN2 pin is also used as the program power supply pin. MVDD Input instruction
MVDD
26~28
P3-1/ADin1 ~ P3-3/ADin3
I/O port 3 /A/D analog voltage input
To A/D converter
29
P4-0/ADin4 /BUZR
I/O port 4 /A/D analog voltage input/buzzer output
36
P2-3/DATAin
37
IN1/BCKin
MVDD
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TC94A23F
Pin Number Symbol Pin Name Function and Operation 3-bit CMOS I/O port. Input/output can be set for each bit by program. Remarks
30
P4-1/S12
I/O port 4/serial data These pins are also used as serial interface input (SIO) circuit input/output pins. SIO is a serial interface supporting 2-line and 3-line methods. Starting from the MSB or LSB, 4 or 8-bit serial data are output to the SO/SDA pin, or data on the SI1 and SI2 pins are input to the device at the clock edge on the SCK/SCL pin. As the serial operating clock (SCK/SCL), an internal (450/225/150/75 kHz) or external clock can be selected. Rising or falling shift can also be selected. The clock and data output can be N-channel open drain. These selections facilitate controlling the LSI and communications between the controllers. When SIO interrupts are enabled, an interrupt is generated as soon as execution of the SIO completes, and the program jumps to address 4. This is effective for performing serial communications at high speed. All SIO inputs incorporate a Schmidt circuit. SIO and its control can be set by program. MVDD
31
P4-2 /SI0/SI1/SDA
/serial data input/output
Input instruction + SI0ON
32
P4-3 /SCK/SCL
/serial clock input/output
38
TESTC Test mode control input
Input pins for controlling Test mode. When the pins are at High level, the device is in Test mode; at Low level, in normal operation. Normally, set the pins to Low level or NC (pull-down resistors are incorporated). RIN2
MVDD
88
TESTM
4-bit general-purpose output port. After system reset, the pins are set to a Low-level output port. The pins can be switched to CD control output pins by program. Setting OT19 to OT22 to 0 switches all four pins to CD control output pins. Setting OT19 to OT22 and CDIO to 1 enables the pins to be switched as follows according to the segment data contents of the S15 and S16 pins: Output port/CD control signal output
HSO : Outputs playback speed mode. Normal speed: High Double speed: Low
MVDD
OT19/ HSO OT20/SPCK 39~42 OT21/SPDA OT22/COFS
SPCK: Outputs clock for reading processor status signal (176.4 kHz). APCK: Outputs clock for reading processor status signal. SPDA: Outputs processor status signal. COFS: Outputs frame clock for correction (7.35 kHz).
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Pin Number Symbol Pin Name Function and Operation Remarks
43
DOUT
Digital output in. Sub code block sync output pin.
VDD
44
SBSY
When sub code sync is detected, outputs High at the S1 position. Sub code Q data CRCC result output pin.
45
SBOK When the result is OK, outputs High. Power supply pins for CD digital block. Normally, 5 V is applied. When CD is not used (CD off), the power supply can be set to off except to the controller, enabling only the controller to operate. At this time, 1 must be set in the CDoff bit. If pins from 11 to 18 and 39 to 42 are set as CD control signal input/output pins, setting the CDoff bit to 1 switches all the pins to an output port. 2VREF pin for PLL block 3/4
46, 75
VDD
VDD
47, 76
VSS
MVSS
48
P2VREF
P2VREF
49
PDO
Outputs phase error signal between the EFM CD processor control and PLCK signals. input/output
PVREF
TMAX detection result output pin. Selected by command bit TMPS. 50 TMAX Longer than the specified cycle: Outputs P2VREF. Shorter than the specified cycle: Outputs Low level (VSS). Within the specified cycle: at high impedance
P2VREF
51
LPFN
Inverted input pin for low-pass filter amp. PVREF
AVDD LPFN LPFO
52
LPFO
Output pin for low-pass filter amp.
53
PVREF
VREF pin for PLL block PVREF VCO VCOF
54 55
VCOF AVSS
VCO filter pin Ground pin for analog block
3/4
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Pin Number Symbol Pin Name Function and Operation Remarks
56
SLCO
DAC output pin for generating data slice level RFI
Zin1 VREF AVDD
57
RFI
RF signal input pin
SLCO
DAC
58
AVDD
Power supply pin for analog block
3/4
59
RFCT
RFRP signal center level input pin RFZI
AVDD
60
RFZI
RFRP zero-cross signal input pin
RFCT 1 kW typ. 32 kW typ.
61
RFRP
RF ripple signal input pin RFRP CD processor control Focus error signal input pin input/output
AVDD
62
FEI
FEI SBAD TEI
63
SBAD
Sub beam addition signal input pin Tracking error input pin.
64
TEI The pin is read at tracking servo on.
AVDD TEZI 65 TEZI Tracking error/zero-cross signal input pin VREF Zin2 1 kW typ. 32 kW typ.
66
FOO
Focus equalizer output pin Rout3
AVDD
2VREF~ AVSS
67
TRO
Tracking equalizer output pin 3/4
68
VREF
Analog reference voltage power supply pin
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Pin Number Symbol Pin Name Function and Operation Control signal output pin for adjusting RF amplitude. 69 RFGC Outputs three-level PWM signal (PWM carrier = 88.2 kHz). Tracking balance control signal output pin. 70 TEBC Outputs three-level PWM signal (PWM carrier = 88.2 kHz). Focus equalizer output pin. 71 FMO Outputs three-level PWM signal (PWM carrier = 88.2 kHz). Disc equalizer output pin. 72 DMO CD processor control Outputs three-level PWM signal input/output (PWM carrier = 88.2 kHz for DSP block). Analog reference voltage power supply pin (2 VREF) 3/4 Rout3 P2VREF Remarks
VREF
73
2VREF
VDD APC circuit on/off signal output pin. 74 SEL At laser on, high impedance at UHS = High; H level output at UHS = High.
Power supply pins for CD crystal oscillator. 77 XVSS To control the CD processor power supply and the controller power supply individually, connect the MVDD and MVSS pins to the power supply lines used by the VDD and VSS pins. CD crystal oscillator input/output pins. Connect a 16.9344 MHz crystal oscillator. The clock is used as the CD system clock and controller system clock. 78 XI After system reset, this clock is supplied as CD processor crystal the controller system clock and starts the CPU. oscillator pins The crystal oscillator can be halted by program. If the 4.5 MHz or 75 kHz oscillator is selected as the controller system clock, the oscillator is halted by program when the CD processor is off. During execution of the CKSTP instruction, oscillation halts. (Note) When switching the controller system clock from the controller oscillator to the CD crystal oscillator, make sure that the CD crystal oscillator is in stable state. XI Rout1 XO RfXT1 XVDD 3/4
80
XVDD
79
XO
XVSS
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Pin Number 81 82 83 84 85 86 Symbol Pin Name Function and Operation Remarks
DVSR RO DVRR DVDD DVRL LO
R-channel D/A converter block ground pin DVDD R-channel data forward rotation output pin R-channel reference voltage pin CD processor control D/A converter block power supply pin input/output RO/LO L-channel reference voltage pin L-channel data forward rotation output pin DVSL/DVSR VSS DVDD DVRR/DVRL
87
DVSL
L-channel D/A converter block ground pin Device system reset signal input pin. While the RST is at Low level, reset is applied. When the RST is at High level, the CD block is in operation, and the controller program starts from address 0. Normally, when 2.7 V or higher voltage is supplied to the MVDD when at 0 V, system reset is applied (power-on reset). Fix the pin to High level. Input pin used to request or release hold state. Normally, the pin is used for inputting the CD mode selection signal or battery detection signal. Halt states are Clock Stop mode (crystal oscillator stops oscillation) and Wait mode (CPU stops). The modes are entered using the CKSTP and WAIT instructions. By program, Clock Stop mode can be entered by detection of Low level on the HOLD pin or by forced execution. Clock Stop mode can be released by detection of High level on the HOLD pin or change in the HOLD pin input. Executing the CKSTP instruction stops the clock generator and the CPU, entering memory backup state. During memory backup state, current dissipation becomes low (1 mA or below). The display output and CMOS output port automatically become Low level. The N-channel open drain output becomes off. Regardless of the HOLD pin input state, Wait mode is executed and current dissipation becomes low. Crystal oscillator only on or CPU operation suspended can be programmed. When the crystal oscillator only is on, all displays are at Low level. The other pins are in Hold state. When CPU operation is suspended, all states are held except that the CPU is suspended. Wait mode is released by a change of the HOLD pin input. (Note) To use Backup mode, turn off the VDD pin (power supply for CD), and enter Backup mode. MVDD
90
RST
Reset input
MVDD
91
HOLD
Hold mode control input
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Pin Number Symbol Pin Name Function and Operation External interrupt input pin. When interrupts are enabled and a pulse of 1.11 to 3.33 ms or more (13.3 to 40 ms when the 75 kHz clock is used) is input to this pin, an interrupt is generated and the program jumps to address 1. Input logic and rising/falling edge can be individually selected for interrupt inputs. The internal 8-bit timer clock can be selected for interrupt inputs. Interrupts can be generated (address 3) by pulse count or the count value. Interrupt inputs are Schmidt inputs. The pin can be used as an input port for inputs such as remote control signals. Crystal oscillator pins for the controller. The oscillator clock is used as a time base for the clock function as well as the system clock for the controller. After system reset, the CPU starts operation using the 16.9344 MHz CD oscillator (connected to the XI and XO pins). The oscillator is switched to the controller oscillator by program. Either a 4.5 MHz reference oscillator or a 75 kHz oscillator is connected to the MXO and MXI pins. The oscillators are switched by a bit used to select a frequency of 4.5 MHz or 75 kHz. The oscillators incorporate a feedback resistor. Crystal oscillator pins Switching frequencies automatically switches the feedback resistor of the crystal oscillator. for controller 75 kHz: Rout2 = 2 KW, RfXT2 = 10 MW typ. 4.5 MHz: Rout2 = 2 KW, RfXT2 = 1 MW typ. If the operating clock is the CD crystal oscillator, fix the MXI pin to GND. 94 MXI During execution of the CKSTP instruction, oscillation halts. Selection and control of crystal oscillators are done by program. (Note) When the 75 kHz crystal oscillator is used, externally add/connect a 100 kW output resistor. MXO Remarks
92
INTR
External interrupt input
93
MXO
Rout2 RfXT2 MVDD
MXI
Power supply pins for the controller block. Normally, VDD = 4.5 to 5.5 V. In backup state (when executing the CKSTP instruction), current dissipation becomes low (1 mA or below), dropping the power supply voltage to 2.0 V. If 2.7 V or more is applied to these pins when at 0 V, a system reset is applied to the device and the program starts from address 0 (power-on reset). MVDD
19, 96
MVDD
Power supply pins for controller block The CD processor incorporates a power supply detector, which detects the power supply voltage of 2.5 V. (Note) 20, 95 MVSS
At power-on reset operation, allow 10 to 100 ms while the device power supply voltage rises. MVSS
When not using the power supply detector function, set the test port pins (TEST#0 to 3) to all 1s so that the CD processor enters Halt state. Setting to Halt state reduces current dissipation by 150 mA (typ.).
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Maximum Ratings (Ta = 25C, VDD = MVDD = DVDD = AVDD, MVDD = XVDD)
Characteristic Power supply voltage (VDD power supply pin) Input voltage (MVDD power supply pin) Power dissipation Operating temperature Storage temperature VIN2 PD Topr Tstg -0.3~MVDD + 0.3 1400 -40~85 -65~150 mW C C Symbol VDD MVDD VIN1 Rating -0.3~6.0 (MVDD > VDD) = -0.3~VDD + 0.3 V Unit V
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Electrical characteristics
(unless otherwise specified, Ta = 25C, VDD = MVDD = XVDD = DVDD = AVDD = 5 V, 2VREF = P2VREF = 4.2 V, VREF = PVREF = 2.1 V) VDD (power supply pins for CD processor block: VDD, XVDD, DVDD, AVDD)
Characteristic Operating power supply voltage range Symbol VDD IDD XIDD Crystal oscillator standby current Crystal oscillator frequency XSTBY fXT Test Circuit 3/4 3/4 3/4 3/4 3/4 Test Condition MVDD = XVDD > VDD = DVDD = AVDD = (VDD, DVDD, AVDD) operating at 16.9344 MHz (XVDD) 16.9344 MHz crystal oscillator connected (XVDD) 16.9344 MHz crystal oscillator off Ci = Co = 15 pF (Note 1)* * Min 4.5 3/4 3/4 3/4 3/4 Typ. ~ 50 2.0 0.01 16.9344 Max 5.5 60 mA 3/4 3/4 3/4 mA MHz Unit V
Operating power supply current
MVDD (power supply pins for CPU block: MVDD, XVDD) (Note 2)
Characteristic Symbol MVDD1 Operating power supply voltage range MVDD2 MVDD3 Memory hold voltage range MVHD MIDD1 MIDD2 Operating power supply current (Note 3) MIDD3 MIDD4 MIDD5 MIDD6 Memory hold current MIHD fMXT1 Crystal oscillator frequency fMXT2 Crystal oscillator start time tst 3/4 3/4 3/4 Test Circuit Test Condition CPU and CD in operation MVDD = XVDD > VDD = DVDD = AVDD = CPU in operation (CD off, 4.5 MHz /16.9344 MHz crystal oscillator used) CPU in operation (CD off, 75 kHz crystal oscillator used) Crystal oscillator stopped (executing CKSTP instruction) Min 4.5 4.5 3.0 2.0 3/4 Typ. ~ ~ ~ ~ 3.0 1.4 0.3 1.5 0.25 0.1 0.1 4.5 75 3/4 Max 5.5 5.5 V 5.5 5.5 5.0 2.5 1.0 mA Unit
* * * *
XI = 16.9344 MHz crystal oscillator connected CPU in operation MXI = 4.5 MHz crystal oscillator connected MXI = 75 kHz crystal oscillator connected XI = 16.9344 MHz crystal oscillator connected Standby mode MXI = 4.5 MHz crystal (crystal oscillator oscillator connected only in operation) MXI = 75 kHz crystal oscillator connected Crystal oscillator stopped (executing CKSTP instruction) 4.5 MHz crystal oscillator set 75 kHz crystal oscillator set, MVDD = 2.7~5.5 V Crystal oscillator fmxt = 75 kHz (Note 1)* (Note 1)*
3/4 3/4 3/4 3/4 3/4
3/4 3/4 3/4 3/4
3/4 3/4 3/4 3/4 3/4
3/4 3/4 3/4 3/4
3/4 3/4 3/4
1.0 3/4 3/4 1.0 mA MHz kHz s
Note 1: Design and set constants according to the crystal oscillator to be connected. Note 2: The power supply/memory hold current is the value obtained by summing the XVDD and MVDD pin currents. Note 3: The values are those when the power supply detector function is operating. Setting the function reduces current dissipation by 150 mA (typ.). (Except in Standby mode) An asterisk (*) indicates the values are guaranteed when VDD = MVDD = XVDD = DVDD = AVDD = 4.5 to 5.5 V, and Ta = -40 to 85C.
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LCD common output/output port (COM1/OT1 to COM4/OT4)
Characteristic High level Output current Low level 1/2 level Bias voltage 1/3 level 2/3 level Symbol IOH1 IOH2 IOL1 IOL5 VBS2 VBS1 VBS3 Test Circuit 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Test Condition VOH = 4.5 V (LCD output) VOH = 4.5 V (OT output) VOL = 0.5 V (LCD output) VOL = 0.5 V (OT output) No load (LCD output, 1/2 bias method set) No load (LCD output, 1/3 bias method set) 3.13 3.33 3.53 Min -200 -15 200 4.0 2.3 1.47 Typ. -600 -30 600 10 2.5 1.67 Max 3/4 3/4 3/4 3/4 2.7 1.87 V Unit mA mA mA mA
Segment output, output ports, I/O ports, and CD function output
(S1/OT4 to S9/OT13, S10/OT14/ZDET to S14/OT18/LRCK, P8-0/S14/BCK to P8-3/S18/IPF, OT19)
Characteristic Symbol IOH1 High level Output current Low level Input leakage current High level Input voltage Low level 1/3 level Bias voltage 1/2 level VIL VBS1 VBS3 3/4 3/4 3/4 (P8-0~P8-3, CLCK) IOH4 IOL1 IOL5 ILI VIH Test Circuit 3/4 3/4 3/4 3/4 3/4 3/4 Test Condition VOH = 4.5 V (LCD output) VOH = 4.5 V (OT output, CD output, excluding P8-0 to P8-3 pins) VOL = 0.5 V (LCD output) VOL = 0.5 V (OT output, CD output) VIH = 5.0 V, VIL = 0 V (P8-0~P8-3) (P8-0~P8-3, CLCK) Min -200 -1.5 200 4.0 3/4 MVDD 0.8 0 1.47 No load (LCD output, 1/3 bias method set) 3.13 3.33 3.53 Typ. -600 -4.0 600 10 3/4 ~ ~ 1.67 Max 3/4 3/4 3/4 3/4 1.0 MVDD V MVDD 0.2 1.87 V Unit mA mA mA mA mA
I/O port (P1-0~P4-3)
Characteristic High level Output current Low level Symbol IOH3 IOL3 IOL5 Input leakage current High level Input voltage Low level Input pull-up/down resistance VIL RIN1 3/4 3/4 3/4 (P1-0 to P1-3 pins) pull-down/up set ILI VIH Test Circuit 3/4 3/4 3/4 3/4 3/4 VOH = 4.5 V VOL = 0.5 V (excluding P4-1, P4-2, P4-3 pins) VOL = 0.5 V (P4-1, P4-2, P4-3 pins) VIH = 5.0 V, VIL = 0 V 3/4 Test Condition Min -0.8 1.0 4.0 3/4 MVDD 0.8 0 25 Typ. -2.0 3.0 10 3/4 ~ ~ 50 Max 3/4 3/4 3/4 1.0 MVDD V MVDD 0.2 120 kW mA mA Unit
HOLD , INTR input port, RST RST input, 1-bit DAC data input (EMPHin/ HSO in/LRCKin/DATAin/BCKin) Input port (IN1/IN2)
Characteristic Input leakage current High level Input voltage Low level VIL 3/4 3/4 Symbol ILI VIH Test Circuit 3/4 3/4 Test Condition VIH = 5.0 V, VIL = 0 V 3/4 Min 3/4 MVDD 0.8 0 Typ. 3/4 ~ ~ Max 1.0 MVDD V MVDD 0.2 Unit mA
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A/D converter (ADin1 to ADin4)
Characteristic Analog input voltage range Resolution Total conversion error Analog input leakage Symbol VAD VRES 3/4 ILI Test Circuit 3/4 3/4 3/4 3/4 ADin1~ADin4 3/4 3/4 VIH = 5.0 V, VIL = 0 V (ADin1~ADin4) Test Condition Min 0 3/4 3/4 3/4 Typ. ~ 6 0.5 3/4 Max MVDD 3/4 1.0 1.0 Unit V bit LSB mA
DOUT, SBSY, SBOK, SEL, OT19/ HSO , OT20/SPCK, OT21/SPDA, OT22/COFS output
Characteristic High level Output current Low level Symbol IOH4 IOL4 Test Circuit 3/4 3/4 VOH = 4.5 V VOL = 0.5 V Test Condition Min -1.5 1.5 Typ. -4.0 4.0 Max 3/4 3/4 Unit mA
PDO, TMAX, RFGC, TEBC, FMO, DMO, TRO, FOO output
Characteristic Output current Output resistance VREF output voltage High level Low level Symbol IOH6 IOL4 Rout3 Voref Test Circuit 3/4 3/4 3/4 3/4 Test Condition VOH = 3.8 V, P2VREF = 4.2 V (PDO, TMAX) VOL = 0.5 V, P2VREF = 4.2 V (PDO, TMAX) (RFGC, TEBC, FMO, DMO, TRO, FOO) (RFGC, TEBC, FMO, DMO, PDD) VREF = PVREF = 2.1 V Min 3/4 3/4 3/4 3/4 Typ. -2.0 6.0 3.3 2.1 Max 3/4 3/4 3/4 3/4 Unit mA kW V
Transfer delay time (AOUT, SPDA, DATA, SBSY, SBOK)
Characteristic Transfer delay time High level Low level Symbol tpLH tpHL Test Circuit 3/4 3/4 Test Condition 3/4 3/4 Min 3/4 3/4 Typ. 10 10 Max 3/4 3/4 Unit ns
1-bit DA converter
Characteristic Total harmony distortion S/N ratio Dynamic range Crosstalk Analog output level Symbol THD + N S/N DR CT DACout Test Circuit 3/4 3/4 3/4 3/4 3/4 Test Condition 1 kHz sine wave, full-scale input 3/4 1 kHz sine wave, based on -60dB input 1 kHz sine wave, full-scale input 1 kHz sine wave, full-scale input Min 3/4 90 85 3/4 1200 Typ. -85 98 90 -90 1250 Max -78 3/4 3/4 -85 1300 mVrms dB Unit
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Others
Characteristic Input pull-down resistance XI amp feedback resistance XO output resistance MXI amp feedback resistance MXO output resistance Symbol RIN2 RfXT1 Rout1 RfXT2 Rout2 Test Circuit 3/4 3/4 3/4 3/4 3/4 3/4 Test Condition (TESTC, TESTM) (XI-XO) (XO) When 4.5 MHz crystal set, (MXI-MXO) When 75 kHz crystal set, (MXI-MXO) (MXO) Min 3/4 1.0 3/4 0.5 3/4 3/4 3/4 Zin1 3/4 Set resistance by (RFI) CD command 3/4 3/4 3/4 Zin2 3/4 (TEZI) 3/4 Typ. 10 2.0 0.5 1.0 10 2.0 10 5.0 2.5 1.25 10 Max 3/4 4.0 3/4 2.5 3/4 3/4 3/4 3/4 3/4 3/4 3/4 kW MW kW Unit kW MW kW
Input resistance
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Package Dimensions
Weight: 1.6 g (typ.)
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RESTRICTIONS ON PRODUCT USE
000707EBA
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
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2002-02-06

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