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SRAM
Austin Semiconductor, Inc. 256K x 4 SRAM
SRAM MEMORY ARRAY
AVAILABLE AS MILITARY SPECIFICATIONS
*MIL-STD-883
MT5C1005
PIN ASSIGNMENT (Top View)
28-Pin DIP (C) (400 MIL)
A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 CE\ OE\ Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vcc A6 A5 A4 A3 A2 A1 A0 NC DQ4 DQ3 DQ2 DQ1 WE\
32-Pin LCC (EC) 32-Pin SOJ (DCJ)
A7 A8 A9 A12 A10 A11 A13 NC A14 A15 A16 A17 NC CE\ OE\ Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Vcc A6 A5 A2 A4 A3 A1 NC NC A0 NC DQ4 DQ3 DQ2 DQ1 WE\
FEATURES
High Speed: 20, 25, 35, and 45 Battery Backup: 2V data retention Low power standby High-performance, low-power CMOS double-metal process * Single +5V (+10%) Power Supply * Easy memory expansion with CE\ and OE\ options. * All inputs and outputs are TTL compatible
A7 A8 A9 A12 A10 A11 A13 NC A14 A15 A16 A17 NC CE\ OE\ Vss
* * * *
32-Pin Flat Pack (F)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Vcc A6 A5 A2 A4 A3 A1 NC NC A0 NC DQ4 DQ3 DQ2 DQ1 WE\
32-Pin LCC (ECW)
A9 A8 A7 NC Vcc A6 A5 4 3 2 1 31 32 30
A10 A11 A12 A13 A14 A15 A16 A17 CE\ 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 A2 A4 A3 A1 A0 NC NC NC DQ4
OPTIONS
* Timing 20ns access 25ns access 35ns access 45ns access 55ns access 70ns access
MARKING
-20 -25 -35 -45 -55* -70*
14 15 16 17 18 19 20 DQ3 DQ2 DQ1 WE\ Vss OE\ NC
* Package(s) Ceramic DIP (400 mil) C Ceramic Quad LCC (contact factory) ECW Ceramic LCC EC Ceramic Flatpack F Ceramic SOJ DCJ * Operating Temperature Ranges Industrial (-40oC to +85oC) IT Military (-55oC to +125oC) XT * 2V data retention/low power L
No. 109 No. 206 No. 207 No. 303 No. 501
GENERAL DESCRIPTION
The Austin Semiconductor SRAM family employs high-speed, low power CMOS designs fabricated using doublelayer metal, double-layer polysilicon technology. For flexibility in high-speed memory applications, ASI offers chip enable (CE\) and output enable (OE\) capability. These enhancements can place the outputs in High-Z for additional flexibility in system design. Writing to these devices is accomplished when write enable (WE\) and CE\ inputs are both LOW. Reading is accomplished when WE\ remains HIGH while CE\ and OE\ go LOW. The devices offer a reduced power standby mode when disabled. This allows system designs to achieve low standby power requirements. All devices operation from a single +5V power supply and all inputs and outputs are fully TTL compatible.
*Electrical characteristics identical to those provided for the 45ns access devices.
For more products and information please visit our web site at www.austinsemiconductor.com
MT5C1005 Rev. 3.1 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
SRAM
Austin Semiconductor, Inc. FUNCTIONAL BLOCK DIAGRAM
VCC GND
MT5C1005
A A A
ROW DECODER
A A A A A A A
DQ4
262,144 x 4-BIT MEMORY ARRAY
I/O CONTROL
DQ1
CE\ COLUMN DECODER OE\ WE\ A A A A A A A A POWER DOWN
TRUTH TABLE
MODE STANDBY READ READ WRITE OE\ X L H X CE\ H L L L WE\ X H H L DQ HIGH-Z Q HIGH-Z D POWER STANDBY ACTIVE ACTIVE ACTIVE
MT5C1005 Rev. 3.1 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
SRAM
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS* Supply Voltage Range (Vcc)................................-.5V to +7.0V Storage Temperature......................................-65C to +150C Voltage on any Pin Relative to Vss................-.5V to Vcc+.5V Max Junction Temperature............................................+175C Lead Temperature (soldering 10 seconds)..................+260oC Power Dissipation ...............................................................1 W
MT5C1005
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55oC < TC < 125oC; VCC = 5V +10%)
DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage 0VPARAMETER Power Supply Current: Operating Power Supply Current: Standby
CONDITIONS WE\, CE\ < VIL; VCC = MAX Output Open CE\ > VIH; All Other Inputs < VIL or > VIH, VCC = MAX CE\ > VCC -0.2V; VCC = MAX VIL < VSS +0.2V VIH > VCC -0.2V; f = 0 Hz*
SYM Icc
-20 180
MAX -25 -35 180 180
-45 180
UNITS NOTES mA 3
ISBT2
25
25
25
25
mA
ISBC
16
16
16
16
mA
* "L" version only.
CAPACITANCE
PARAMETER Input Capacitance Output Capacitance (DQ1-DQ4) CONDITIONS VIN = 0V, TA = 25C, f = 1MHz VCC = 5V CO 14 pF 4 SYM CI MAX 12 UNITS pF NOTES 4
MT5C1005 Rev. 3.1 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
SRAM
Austin Semiconductor, Inc.
MT5C1005
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 5) (-55oC < TC < 125oC; VCC = 5V +10%)
DESCRIPTION READ CYCLE READ cycle time Address access time Chip Enable access time Output hold from address change Chip Enable to output in Low-Z Chip disable to output in High-Z Chip Enable to power-up time Chip disable to power-down time Output Enable access time Output Enable to output in Low-Z Output disable to output in High-Z WRITE CYCLE WRITE cycle time Chip Enable to end of write Address valid to end of write Address setup time Address hold from end of write WRITE pulse width Data setup time Data hold time Write disable to output in Low-Z Write Enable to output in High-Z -20 -25 -35 -45 SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES tRC tAA tACE tOH tLZCE tHZCE tPU tPD tAOE tLZOE tHZOE tWC tCW tAW tAS tAH tWP tDS tDH tLZWE tHZWE 20 20 20 3 3 10 0 20 8 0 8 20 15 15 0 0 15 12 0 3 0 25 20 20 0 0 20 15 0 3 0 0 10 35 30 30 0 0 30 20 0 3 0 0 25 10 0 20 45 35 35 0 0 35 25 0 3 0 3 3 12 0 35 20 0 25 25 25 25 3 3 20 0 45 25 35 35 35 3 3 25 45 45 45 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
4, 6, 7 4, 6, 7 4 4 4, 6, 7 4, 6, 7
8
10
15
20
4, 6, 7 4, 6, 7
MT5C1005 Rev. 3.1 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
SRAM
Austin Semiconductor, Inc.
AC TEST CONDITIONS
Input pulse levels ................................... Vss to 3.0V Input rise and fall times ....................................... 5ns Input timing reference levels ............................. 1.5V Output reference levels ..................................... 1.5V Output load .............................. See Figures 1 and 2
MT5C1005
167 Q 30pF VTH = 1.73V Q
167 5pF VTH = 1.73V
Fig. 1 Output Load Equivalent
Fig. 2 Output Load Equivalent
NOTES
1. 2. 3. All voltages referenced to VSS (GND). -3V for pulse width < 20ns ICC is dependent on output loading and cycle rates. The specified value applies with the outputs unloaded, and f = 1 Hz. t RC (MIN) 4. This parameter is guaranteed but not tested. 5. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. 6. Minimum of 5pF for tEHQZ, tOHQZ, tELQX, tOLQX, and tWHQX.
7.
At any given temperature and voltage condition, t HZCE is less than tLZCE, and tHZWE is less than t LZWE and tHZOE is less than tLZOE. 8. WE\ is HIGH for READ cycle. 9. Device is continuously selected. Chip enables and output enables are held in their active state. 10. Address valid prior to, or coincident with, latest occurring chip enable. 11. tRC = Read Cycle Time. 12. Chip enable (CE\) and write enable (WE\) can initiate and terminate a WRITE cycle.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION VCC for Retention Data CE\ > (VCC-0.2V) and VIN > (VCC-0.2V) or < 0.2V CONDITIONS SYM VDR MIN 2 MAX UNITS NOTES V
Data Retention Current
VCC = 2V
ICCDR
5
mA
Chip Deselect to Data Retention Time Operation Recovery Time
tCDR tR
0 tRC
--
ns ns
4 4, 11
LOW Vcc DATA RETENTION WAVEFORM
VCC
t
DATA RETENTION MODE 4.5V CDR VDR VDR > 2V 4.5V
t
R
MT5C1005 Rev. 3.1 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
4321 4321 4321 4321
321 321 321 321
CE\
VIH VIL
4216 3326 32 87 421154321 332154321 87 421154321 321154321 87 3326 4876
987654321 4321 321 987654321 4321 987654321 987654321 321
DON'T CARE UNDEFINED
SRAM
Austin Semiconductor, Inc.
MT5C1005
READ CYCLE NO. 1
ttRC RC
ADDRESS
VALID
8, 9
ttAA AA t OH tOH
DQ
PREVIOUS DATA VALID DATA VALID
READ CYCLE NO. 2 7, 8, 10
ttRC RC
CE\
ttAOE AOE
tLZOE OE\
tLZOE
HZOE tHZOE
t
ttLZCE LZCE tACE tACE
DQ
DATA VALID
tHZCE tHZCE
t PU tPU
Icc
ttPD PD
MT5C1005 Rev. 3.1 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
6
4321 4321 4321
4321 1 4321 4321 432
DON'T CARE
UNDEFINED
SRAM
Austin Semiconductor, Inc.
WRITE CYCLE NO. 1 12 (Chip Enabled Controlled)
WC tWC
MT5C1005
t
ADDRESS
tAW tAW tAS tAS
CE\ WE\
tCW tCW t WP tWP1 tDS tDS
AH tAH
t
D Q
DATA VAILD
HIGH Z
WRITE CYCLE NO. 2 7, 12 (Write Enabled Controlled)
tWC tWC
ADDRESS
tAW tAW tCW tCW t AH tAH
CE\
tAS t AS WE\
t WP tWP1 tDS t DH tDH
D Q
HIGH-Z
DATA VALID
NOTE: Output enable (OE\) is inactive (HIGH).
MT5C1005 Rev. 3.1 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
7
321098765432109876543211 1 2 32109876543210987654321 1 32109876543210987654321
098765432121098765432109876543210987654321 098765432121098765432109876543210987654321
t DH tDH
5 3 21 44321 4321 1 4321 432
54321 54321 54321
2109876543210987654321 1 2109876543210987654321 1 116543210987654321 27 1 1 27 176543210987654321 21654321098765432
DON'T CARE
UNDEFINED
SRAM
Austin Semiconductor, Inc. MECHANICAL DEFINITIONS*
ASI Case #109 (Package Designator C)
MT5C1005
D
A Q Pin 1 b b1 E L
e
c E1
SYMBOL A b b1 c D E E1 e L Q
ASI PACKAGE SPECIFICATIONS MIN MAX 0.090 0.110 0.016 0.020 0.040 0.060 0.008 0.012 1.386 1.414 0.385 0.405 0.390 0.410 0.090 0.110 0.125 0.175 0.040 0.060
*All measurements are in inches.
MT5C1005 Rev. 3.1 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
8
SRAM
Austin Semiconductor, Inc. MECHANICAL DEFINITIONS*
ASI Case #206 (Package Designator ECW)
E1
MT5C1005
L1
A
e D D1
b2 E b b1 L
SYMBOL A b b1 b2 D D1 E E1 e L L1
ASI PACKAGE SPECIFICATIONS MIN MAX 0.077 0.093 0.022 0.028 0.004 0.014 0.054 0.066 0.742 0.758 0.395 0.405 0.442 0.458 0.295 0.305 0.045 0.055 0.045 0.055 0.077 0.093
*All measurements are in inches.
MT5C1005 Rev. 3.1 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
9
SRAM
Austin Semiconductor, Inc. MECHANICAL DEFINITIONS*
ASI Case #207 (Package Designator EC)
MT5C1005
A
L1
D
L e b1
b
E
b2
SYMBOL A b b1 b2 D E e L L1
ASI PACKAGE SPECIFICATIONS MIN MAX 0.080 0.100 0.022 0.028 0.004 0.014 0.054 0.066 0.815 0.835 0.392 0.408 0.045 0.055 0.070 0.080 0.090 0.110
*All measurements are in inches.
MT5C1005 Rev. 3.1 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
10
SRAM
Austin Semiconductor, Inc. MECHANICAL DEFINITIONS*
ASI Case #303 (Package Designator F)
MT5C1005
L
E
Pin 1 Index e 32 1
b D1
D
17
16
Bottom View Top View
c Q E2 A
SYMBOL A b c D D1 E E2 e L Q
ASI PACKAGE SPECIFICATIONS MIN MAX --0.125 0.015 0.019 0.004 0.006 0.812 0.828 0.745 0.755 0.405 0.415 0.324 0.336 0.045 0.055 0.290 0.310 0.027 0.033
*All measurements are in inches.
MT5C1005 Rev. 3.1 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
11
SRAM
Austin Semiconductor, Inc. MECHANICAL DEFINITIONS*
ASI Case #501 (Package Designator DCJ)
MT5C1005
A
e
D D1
R b
E2 E1
E A2
SYMBOL A A2 b D D1 E e E1 E2 R
ASI PACKAGE SPECIFICATIONS MIN MAX 0.135 0.153 0.026 0.036 0.015 0.019 0.812 0.828 0.740 0.755 0.405 0.415 0.045 0.055 0.435 0.445 0.360 0.380 0.030 0.040
*All measurements are in inches.
MT5C1005 Rev. 3.1 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
12
SRAM
Austin Semiconductor, Inc. ORDERING INFORMATION
EXAMPLE: MT5C1005C-20L/IT
Device Number MT5C1005 MT5C1005 MT5C1005 MT5C1005 MT5C1005 MT5C1005 Package Speed Options** Process Type ns C C C C C C -20 -25 -35 -40 -55 -70 L L L L L L /* /* /* /* /* /*
MT5C1005
EXAMPLE: MT5C1005EC-45/XT
Device Number MT5C1005 MT5C1005 MT5C1005 MT5C1005 MT5C1005 MT5C1005 Package Speed Options** Process Type ns EC -20 L /* ECW EC -25 L /* ECW EC -35 L /* ECW EC -40 L /* ECW EC -55 L /* ECW EC -70 L /* ECW
EXAMPLE: MT5C1005F-25L/883C
Device Package Speed Options** Process Number Type ns MT5C1005 F -20 L /* MT5C1005 F -25 L /* MT5C1005 F -35 L /* MT5C1005 F -40 L /* MT5C1005 F -55 L /* MT5C1005 F -70 L /*
EXAMPLE: MT5C1005DCJ-70/XT
Device Package Speed Options** Process Number Type ns MT5C1005 DCJ -20 L /* MT5C1005 DCJ -25 L /* MT5C1005 DCJ -35 L /* MT5C1005 DCJ -40 L /* MT5C1005 DCJ -55 L /* MT5C1005 DCJ -70 L /*
*AVAILABLE PROCESSES IT = Industrial Temperature Range XT = Extended Temperature Range 883C = Full Military Processing ** OPTIONS L = 2V Data Retention/Low Power
-40oC to +85oC -55oC to +125oC -55oC to +125oC
MT5C1005 Rev. 3.1 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
13

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