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K4D26323QG-GC
128M GDDR SDRAM
128Mbit GDDR SDRAM
Revision 1.2 March 2005
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Rev 1.2(Mar. 2005)
K4D26323QG-GC
Revision History
Revision 1.2 (March 04, 2005)
* Removed K4D26323QG-GC22 from the datasheet
128M GDDR SDRAM
Revision 1.1 (November 26, 2004)
* Removed -GC20 from the spec. * Changed AC spec format * Changed DC spec measurement condition from VDD(typ) to VDD(max)
Revision 1.0 (June 23, 2004)
* Changed tDQSCK/tAC of -GC22/25 from 0.55tCK to 0.45tCK * Changed tDQSCK/tAC of -GC20 from 0.55tCK to 0.35tCK
Revision 0.4 (June 04, 2004) - Preliminary
* Removed K4D26323QG-GC40 from the spec * Changed VDD&VDDQ of -GC20/22 from 1.8V+0.1V to 2.0V+0.1V * Changed AC characteristics table on page 15~ 16 from number of clock-based to ns-based. Also key parameters are changed as below
- Changed tRFC/tWR_A/tDAL of -GC20 from 23tCK/6tCK to 25tCK/7tCK/14tCK - Changed tRFC/tWR_A/tDAL of -GC22 from 22tCK/6tCK to 23tCK/7tCK/14tCK - Changed tRC/tRFC/tRP/tWR_A/tDAL of -GC25 from 17tCK/19tCK/5tCK/5tCK/10tCK to 18tCK/20tCK/6tCK/6tCK/12tCK - Changed tRC/tRFC/tRP/tRCD/tRP/tWR_A/tDAL of -GC2A from 15tCK/17tCK/5tCK/5tCK/10tCK to 16tCK/18tCK/6tCK/6tCK/12tCK - Changed tRC/tRFC/tRAS/tRP/tWR_A/tDAL of -GC33 from 13tCK/15tCK/9tCK/4tCK/4tCK to 15tCK/17tCK/10tCK/5tCK/5tCK/10tCK
* Added DC target spec
Revision 0.3 (April 22, 2004)
* Changed tCK(max) of K4D26323QG-GC22 from 10ns to 5ns * Changed tWR of K4D26323QG-GC20 from 6tCK to 7tCK * Changed tWR of K4D26323QG-GC22 from 6tCK to 7tCK * Changed tWR of K4D26323QG-GC25 from 5tCK to 6tCK * Changed tWR of K4D26323QG-GC33 from 4tCK to 5tCK * Changed tWR of K4D26323QG-GC40 from 3tCK to 4tCK
Revision 0.2 (April 20, 2004)
* Changed tCK(max) of K4D26323QG-GC20 from 10ns to 5ns
Revision 0.1 (April 16, 2004)
* Typo corrected
Revision 0.0 (February 2, 2004) - Target Spec
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Rev 1.2(Mar. 2005)
K4D26323QG-GC
128M GDDR SDRAM
1M x 32Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL FEATURES
* 1.8V 0.1V power supply for device operation * 1.8V 0.1V power supply for I/O interface * SSTL_18 compatible inputs/outputs * 4 banks operation * MRS cycle with address key programs -. Read latency 3, 4, 5 and 6 (clock) -. Burst length (2, 4 and 8) -. Burst type (sequential & interleave) * All inputs except data & DM are sampled at the positive going edge of the system clock * Differential clock input * No Wrtie-Interrupted by Read Function * 4 DQS's ( 1DQS / Byte ) * Data I/O transactions on both edges of Data strobe * DLL aligns DQ and DQS transitions with Clock transition * Edge aligned data & data strobe output * Center aligned data & data strobe input * DM for write masking only * Auto & Self refresh * 32ms refresh period (4K cycle) * 144-Ball FBGA * Maximum clock frequency up to 500MHz * Maximum data rate up to 1.0Gbps/pin
ORDERING INFORMATION
Part NO. K4D26323QG-GC25 K4D26323QG-GC2A K4D26323QG-GC33 Max Freq. 400MHz 350MHz 300MHz Max Data Rate 800Mbps/pin 700Mbps/pin 600Mbps/pin SSTL_18 144-Ball FBGA Interface Package
* K4D26323QG-VC is the Lead Free package part number.
GENERAL DESCRIPTION
FOR 1M x 32Bit x 4 Bank DDR SDRAM
The K4D26323QG is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x1,048,576 words by 32 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 3.6GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.
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Rev 1.2(Mar. 2005)
K4D26323QG-GC
PIN CONFIGURATION (Top View)
2
B C D E F G H J K L M N
DQS0 DQ4 DQ6 DQ7 DQ17 DQ19 DQS2 DQ21 DQ22 CAS RAS CS
128M GDDR SDRAM
3
DM0 VDDQ DQ5 VDDQ DQ16 DQ18 DM2 DQ20 DQ23 WE NC NC
4
VSSQ NC VSSQ VDD VDDQ VDDQ NC VDDQ VDDQ VDD NC BA0
5
DQ3 VDDQ VSSQ VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSS BA1 A0
6
DQ2 DQ1 VSSQ VSSQ
7
DQ0 VDDQ VDD VSS
8
DQ31 VDDQ VDD VSS
9
DQ29 DQ30 VSSQ VSSQ
10
DQ28 VDDQ VSSQ VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSS RFU2 A7
11
VSSQ NC VSSQ VDD VDDQ VDDQ NC VDDQ VDDQ VDD CK A8/AP
12
DM3 VDDQ DQ26 VDDQ DQ15 DQ13 DM1 DQ11 DQ9 NC CK CKE
13
DQS3 DQ27 DQ25 DQ24 DQ14 DQ12 DQS1 DQ10 DQ8 NC MCL VREF
VSS VSS Thermal Thermal VSS VSS Thermal Thermal VSS VSS Thermal Thermal VSS VSS Thermal Thermal VSS A10 A2 A1 VSS VDD A11 A3
VSS VSS Thermal Thermal VSS VSS Thermal Thermal VSS VSS Thermal Thermal VSS VSS Thermal Thermal VSS VDD A9 A4 VSS RFU1 A5 A6
NOTE: 1. RFU1 is reserved for A12 2. RFU2 is reserved for BA2 3. VSS Thermal balls are optional
PIN DESCRIPTION
CK,CK CKE CS RAS CAS WE DQS DM RFU Differential Clock Input Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Data Strobe Data Mask Reserved for Future Use BA0, BA1 A0 ~A11 DQ0 ~ DQ31 VDD VSS VDDQ VSSQ NC MCL Bank Select Address Address Input Data Input/Output Power Ground Power for DQ's Ground for DQ's No Connection Must Connect Low
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Rev 1.2(Mar. 2005)
K4D26323QG-GC
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol CK, CK*1 Input Type
128M GDDR SDRAM
Function The differential system clock Input. All of the inputs are sampled on the rising edge of the clock except DQ's and DM's that are sampled on both edges of the DQS. Activates the CK signal when high and deactivates the CK signal when low. By deactivating the clock, CKE low indicates the Power down mode or Self refresh mode. CS enables the command decoder when low and disabled the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Latches row addresses on the positive going edge of the CK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Data input and output are synchronized with both edge of DQS. DQS0 for DQ0 ~ DQ7, DQS1 for DQ8 ~ DQ15, DQS2 for DQ16 ~ DQ23, DQS3 for DQ24 ~ DQ31. Data In mask. Data In is masked by DM Latency=0 when DM is high in burst write. DM0 for DQ0 ~ DQ7, DM1 for DQ8 ~ DQ15, DM2 for DQ16 ~ DQ23, DM3 for DQ24 ~ DQ31. Data inputs/Outputs are multiplexed on the same pins. Selects which bank is to be active. Row/Column addresses are multiplexed on the same pins. Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA7. Column address CA8 is used for auto precharge. Power and ground for the input buffers and core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. Reference voltage for inputs, used for SSTL interface. This pin is recommended to be left "No connection" on the device Must connect low
CKE
Input
CS
Input
RAS CAS WE
Input Input Input
DQS0 ~ DQS3
Input/Output
DM0 ~ DM3 DQ0 ~ DQ31 BA0, BA1 A0 ~ A11 VDD/VSS VDDQ/VSSQ VREF NC/RFU MCL
Input Input/Output Input Input Power Supply Power Supply Power Supply No connection/ Reserved for future use Must Connect Low
*1 : The timing reference point for the differential clocking is the cross point of CK and CK. For any applications using the single ended clocking, apply VREF to CK pin.
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Rev 1.2(Mar. 2005)
K4D26323QG-GC
BLOCK DIAGRAM (1Mbit x 32I/O x 4 Bank)
128M GDDR SDRAM
32
Intput Buffer I/O Control LWE LDMi
CK, CK Bank Select
Data Input Register Serial to parallel
64
1Mx32 Output Buffer 2-bit prefetch Sense AMP Refresh Counter Row Buffer Row Decoder 1Mx32 1Mx32 1Mx32
64 32
x32
DQi
Address Register
CK,CK ADDR
Column Decoder LCBR LRAS Col. Buffer
Latency & Burst Length Strobe Gen. Data Strobe
(DQS0~DQS3)
Programming Register LCKE LRAS LCBR LWE LCAS LWCBR
DLL
CK,CK
LDMi
Timing Register
CK,CK
CKE
CS
RAS
CAS
WE
DMi
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Rev 1.2(Mar. 2005)
K4D26323QG-GC
FUNCTIONAL DESCRIPTION
* Power-Up Sequence
128M GDDR SDRAM
DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply VDD before VDDQ . - Apply VDDQ before VREF & VTT 2. Start clock and maintain stable condition for minimum 200us. 3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high . 4. Issue precharge command for all banks of the device. 5. Issue a EMRS command to enable DLL. Minimum 20 clcok cycles are required prior to MRS command. *1 6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL. *1,2 7. Issue precharge command for all banks of the device. 8. Issue at least 2 or more auto-refresh commands. 9. Issue a mode register set command with A8 to low to initialize the mode register. *1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL. *2 Sequence of 6&7 is regardless of the order
Power up & Initialization Sequence
~
~
~
~
~
~
CK,CK
tRP
~
20 Clock min.
4 Clock min.
tRP
tRFC
tRFC
4 Clock min.
Mode
Register Set
~
~
~
~
~
~
~
precharge ALL Banks
EMRS
MRS DLL Reset
precharge ALL Banks
1st Auto Refresh
2nd Auto Refresh
~
Command
~
Any Command
Inputs must be stable for 200us
200 Clock min.
* When the operating frequency is changed, DLL reset should be required again. After DLL reset again, the minimum 200 cycles of clock input is needed to lock the DLL.
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Rev 1.2(Mar. 2005)
K4D26323QG-GC
MODE REGISTER SET(MRS)
128M GDDR SDRAM
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of address pins A0 ~ A11 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the mode register. Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test mode. A8 is used for DLL reset. A7,A8, BA0 and BA1 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies. BA1 RFU BA0 0 A11 A10 RFU A9 A8 DLL A7 TM A6 A5 A4 A3 BT A2 A1 A0 Address Bus
CAS Latency
Burst Length
Mode Register
DLL A8 0 1 DLL Reset No Yes
Test Mode A7 0 1 mode Normal Test
Burst Type A3 0 1 Type Sequential Interleave Burst Length
CAS Latency BA0 0 1 An ~ A0 MRS EMRS A6 0 0 0 0 * RFU(Reserved for future use) should stay "0" during MRS cycle. 1 1 1 1 MRS Cycle A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 Latency Reserved Reserved Reserved 3 4 5 6 7
A2 0 0 0 0 1 1 1 1
A1 0 0 1 1 0 0 1 1
A0 0 1 0 1 0 1 0 1
Burst Type Sequential Reserved 2 4 8 Reserved Reserved Reserved Reserved Interleave Reserved 2 4 8 Reserved Reserved Reserved Reserved
~~
0 CK, CK Command
NOP
1
2
6
10
11
12
Precharge All Banks
~~
NOP
NOP
MRS
NOP
Any Command
NOP
NOP
tRP
tMRD=4 tCK
*1 : MRS can be issued only at all banks precharge state. *2 : Minimum tRP is required to issue MRS command. -8-
Rev 1.2(Mar. 2005)
K4D26323QG-GC
EXTENDED MODE REGISTER SET(EMRS)
128M GDDR SDRAM
The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore the extened mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0, A2 ~ A5, A7 ~ A11 and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. A1 and A6 are used for setting driver strength to normal, weak or matched impedance. Two clock cycles are required to complete the write operation in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address pins except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes.
BA1 RFU
BA0 1
A11
A10
A9 RFU
A8
A7
A6 D.I.C
A5
A4 RFU
A3
A2
A1 D.I.C
A0 DLL
Address Bus Extended Mode Register
BA0 0 1
An ~ A0 MRS EMRS
A6 0 0 1 1
A1 0 1 0 1
Output Driver Impedence Control Full Weak N/A Matched 100% 60% Do not use 30%
A0 0 1
DLL Enable Enable Disable
*1 : RFU(Reserved for future use) should stay "0" during EMRS cycle.
Figure 7. Extended Mode Register set
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Rev 1.2(Mar. 2005)
K4D26323QG-GC
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD VDDQ TSTG PD IOS
128M GDDR SDRAM
Value -0.5 ~ 3.6 -1.0 ~ 3.6 -0.5 ~ 3.6 -55 ~ +150 3.3 50
Unit V V V C W mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS(SSTL In/Out)
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 65C)
Parameter
Device Supply voltage Output Supply voltage Reference voltage Termination voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Output leakage current
Symbol
VDD VDDQ VREF Vtt VIH(DC) VIL(DC) VOH VOL IIL IOL
Min
1.7 1.7 0.49*VDDQ VREF-0.04 VREF+0.15 -0.30 Vtt+0.76 -5 -5
Typ
1.8 1.8 VREF -
Max
1.9 1.9 0.51*VDDQ VREF+0.04 VDDQ+0.30 VREF-0.15 Vtt-0.76 5 5
Unit
V V V V V V V V uA uA
Note
1,8 1,8 2 3 4 5 IOH=-15.2mA, 7 IOL=+15.2mA, 7 6 6
Note : 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VREF is expected to equal 0.50*VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to peak noise on the VREF may not exceed + 2% of the DC value. 3. Vtt of the transmitting device must track VREF of the receiving device. 4. VIH(max.)= VDDQ +1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 5. VIL(mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 6. For any pin under test input of 0V < VIN < VDD is acceptable. For all other pins that are not under test VIN=0V. 7. Output logic high voltage and low voltage is depend on output channel condition. 8. For K4D26323QG-G(V)C22, VDD&VDDQ=2.0V+0.1V
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Rev 1.2(Mar. 2005)
K4D26323QG-GC
DC CHARACTERISTICS
Recommended operating conditions Unless Otherwise Noted, TA=0 to 65C)
128M GDDR SDRAM
Version Parameter Operating Current (One Bank Active) Precharge Standby Current in Power-down mode Precharge Standby Current in Non Power-down mode Active Standby Current power-down mode Active Standby Current in Non Power-down mode Operating Current ( Burst Mode) Refresh Current Self Refresh Current Operating Current (4Bank interleaving) Symbol Test Condition -25 ICC1 ICC2P ICC2N ICC3P ICC3N ICC4 ICC5 ICC6 ICC7 Burst Lenth=2 tRC tRC(min) -2A 230 10 60 60 190 440 240 8 570 520 460 -33 220 10 50 50 170 410 225 mA mA mA mA mA mA mA mA mA 1 Unit Note
IOL=0mA, tCC= tCC(min)
CKE VIL(max), tCC= tCC(min) CKE VIH(min), CS VIH(min),
260 10 65 65 210 475 265
tCC= tCC(min)
CKE VIL(max), tCC= tCC(min) CKE VIH(min), CS VIH(min),
tCC= tCC(min)
IOL=0mA ,tCC= tCC(min), Page Burst, All Banks activated.
tRC tRFC(min)
CKE 0.2V Burst Length=4 tRC tRC(min)
IOL=0mA, tCC= tCC(min)
Note : 1. Measured with output open 2. Refresh period is 32ms 3. Current meassured at VDD(max)
AC INPUT OPERATING CONDITIONS
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 65C)
Parameter
Input High (Logic 1) Voltage ;DQ Input Low (Logic 0) Voltage; DQ Clock Input Differential Voltage; CK and CK Clock Input Crossing Point Voltage; CK and CK
Symbol
VIH VIL VID VIX
Min
VREF+0.35 0.7 0.5*VDDQ-0.2
Typ
-
Max
VREF-0.35 VDDQ+0.6 0.5*VDDQ+0.2
Unit
V V V V
Note
1 2
Note : 1. VID is the magnitude of the difference between the input level on CK and the input level on CK 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same
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Rev 1.2(Mar. 2005)
K4D26323QG-GC
AC OPERATING TEST CONDITIONS (TA= 0 to 65C)
Parameter Input reference voltage for CK(for single ended) CK and CK signal maximum peak swing CK signal minimum slew rate Input Levels(VIH/VIL) Input timing measurement reference level Output timing measurement reference level Output load condition Value 0.50*VDDQ 1.5 1.0 VREF+0.4/VREF-0.4 VREF Vtt See Fig.1
128M GDDR SDRAM
Unit V V V/ns V V V Note 1
Note 1 : In case of differential clocks(CK and CK ), input reference voltage for clock is a CK and CK's crossing point.
Vtt=0.5*VDDQ
RT=50 Output Z0=50
VREF =0.5*VDDQ
CLOAD=30pF
(Fig. 1) Output Load Circuit
CAPACITANCE (TA= 25C, f=1MHz)
Parameter
Input capacitance( CK, CK ) Input capacitance(A0~A11, BA0~BA1) Input capacitance ( CKE, CS, RAS,CAS, WE ) Data & DQS input/output capacitance(DQ0~DQ31) Input capacitance(DM0 ~ DM3)
Symbol
CIN1 CIN2 CIN3 COUT CIN4
Min
1.0 1.0 1.0 1.0 1.0
Max
5.0 4.0 4.0 6.5 6.5
Unit
pF pF pF pF pF
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitance added to power line at board. Parameter Decoupling Capacitance between VDD and VSS Decoupling Capacitance between VDDQ and VSSQ Symbol CDC1 CDC2 Value 0.1 + 0.01 0.1 + 0.01 Unit uF uF
Note : 1. VDD and VDDQ pins are separated each other. All VDD pins are connected in chip. All VDDQ pins are connected in chip. 2. VSS and VSSQ pins are separated each other All VSS pins are connected in chip. All VSSQ pins are connected in chip.
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Rev 1.2(Mar. 2005)
K4D26323QG-GC
AC CHARACTERISTICS (I)
Parameter CL=3 CL=4 CL=5 CL=6 Symbol -25 Min 2.5 0.45 0.45 -0.45 -0.45 0.9 0.4 0.85 0 0.35 0.4 0.45 0.45 0.6 0.6 0.3 0.3 tCLmin or tCHmin tHPtQHS Max Min 2.86 0.45 0.45 -0.55 -0.55 0.9 0.4 0.85 0 0.35 0.4 0.45 0.45 0.8 0.8 0.35 0.35 tCLmin or tCHmin tHPtQHS -2A Max
128M GDDR SDRAM
-33 Min 3.3 0.45 0.45 -0.55 -0.55 0.9 0.4 0.85 0 0.35 0.4 0.45 0.45 0.8 0.8 0.35 0.35 tCLmin or tCHmin tHPtQHS Max
Unit ns ns ns ns tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK ns ns ns ns ns ns ns
Note
CK cycle time
tCK
10.0
10.0
10.0
CK high level width CK low level width DQS out access time from CK Output access time from CK Data strobe edge to Dout edge Read preamble Read postamble CK to valid DQS-in DQS-In setup time DQS-in hold time DQS write postamble DQS-In high level width DQS-In low level width Address and Control input setup Address and Control input hold DQ and DM setup time to DQS DQ and DM hold time to DQS Clock half period Data Hold skew factor Data output hold time from DQS
tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPREH tWPST tDQSH tDQSL tIS tIH tDS tDH tHP tQHS tQH
0.55 0.55 0.45 0.45 0.28 1.1 0.6 1.15 0.6 0.55 0.55 0.4 -
0.55 0.55 0.55 0.55 0.35 1.1 0.6 1.15 0.6 0.55 0.55 0.4 -
0.55 0.55 0.55 0.55 0.35 1.1 0.6 1.15 0.6 0.55 0.55 0.4 -
1
1
1
Simplified Timing @ BL=2, CL=4
tCH tCK tCL
0 CK, CK
1
2
3
4
5
6
7
8
CS
tDQSCK
tIS tIH tDQSS tDQSH tDQSL
DQS
tRPRE
tRPST
tWPREH tWPRES
tDS tDH
tDQSQ tAC
DQ
Qa1
Qa2
Db0
Db1
DM
COMMAND READA
WRITEB
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Rev 1.2(Mar. 2005)
K4D26323QG-GC
128M GDDR SDRAM
Note 1 : - The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case output vaild window even then the clock duty cycle applied to the device is better than 45/55% - A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle variation and replaces tDV - tQHmin = tHP-X where . tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL) . X=A frequency dependent timing allowance account for tDQSQmax
tQH Timing (CL4, BL2)
tHP 0 CK, CK 1 2 3 4 5
CS DQS tDQSQ(max) tQH tDQSQ(max) DQ
Qa0 Qa1
COMMAND
READA
Power Down Timing
CK, CK
tIS
CKE
3tCK tIS
Command
VALID
NOP
NOP
NOP
NOP
NOP
NOP
VALID
Enter Power Down mode (Read or Write operation must not be in progress)
Exit Powr Down mode
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Rev 1.2(Mar. 2005)
K4D26323QG-GC
AC CHARACTERISTICS (II)
Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay for Read RAS to CAS delay for Write Row precharge time Last data in to Row precharge @Normal Precharge Last data in to Row precharge @Auto Precharge Auto precharge write recovery + Precharge Row active to Row active Last data in to Read command Col. address to Col. address Mode register set cycle time Exit self refresh to read command Power down exit time Refresh interval time Symbol tRC tRFC tRAS tRCDRD tRCDWR tRP tWR tWR_A tDAL tRRD tCDLR tCCD tMRD tXSR tPDEX tREF -25 Min 45 50 28.6 15 10 15 15 6 30 4 2 1 4 200 3tCK+ tIS 7.8 Max 100K Min 45.8 51.5 28.6 16.5 11.4 16.5 16.5 6 33 4 2 1 3 200 3tCK+ tIS 7.8 -2A Max 100K -
128M GDDR SDRAM
-33 Min 49.5 56.1 33 16.5 11.4 16.5 16.5 5 33 3 2 1 3 200 3tCK+ tIS 7.8 Max 100K -
Unit ns ns ns ns ns ns ns tCK ns tCK tCK tCK tCK tCK ns us
Note 2,5 5 5 5 4,5 5 1,5 1,3 3,5 1
Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM 2. The number of clock of tRP is restricted by the number of clock of tRAS and tRP 3. The number of clock of tWR_A is fixed. It can't be changed by tCK. tWR_A is related with CL. It is equal to CL+1tCK. 4. tRCDWR is equal to tRCDRD-2tCK and the number of clock can not be lower than 2tCK. 5. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer unconditionally.
- 15 -
Rev 1.2(Mar. 2005)
K4D26323QG-GC
AC CHARACTERISTICS (III)
128M GDDR SDRAM
(Unit : Number of Clock)
K4D26323QG-GC25 Frequency Cas Latency 400MHz ( 2.5ns ) 5 350MHz ( 2.86ns ) 5 300MHz ( 3.3ns ) 4
tRC 18 16 15
tRFC 20 18 17
tRAS 12 10 10
tRCDRD tRCDWR 6 4 6 4 5 3
tRP 6 6 5
tRRD 4 4 3
tDAL 12 12 10
Unit
tCK tCK tCK
K4D26323QG-GC2A Frequency Cas Latency 350MHz ( 2.86ns ) 5 300MHz ( 3.3ns ) 4
tRC 16 15
tRFC 18 17
tRAS 10 10
tRCDRD tRCDWR 6 4 5 3
tRP 6 5
tRRD 4 3
tDAL 12 10
Unit
tCK tCK
K4D26323QG-GC33 Frequency Cas Latency 300MHz ( 3.3ns ) 4
tRC 15
tRFC 17
tRAS 10
tRCDRD tRCDWR 5 3
tRP 5
tRRD 3
tDAL 10
Unit
tCK
- 16 -
Rev 1.2(Mar. 2005)
K4D26323QG-GC
Simplified Timing(2) @ BL=4
0
CK, CK
128M GDDR SDRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
BA[1:0] BAa
BAa
BAa
BAa
BAb
BAa
BAb
A8/AP Ra
Ra
Ca
Ra
Rb
ADDR (A0~A7, Ra A9,A10)
Ra
Rb
Ca
Cb
WE
DQS
DQ
Da0 Da1 Da2 Da3
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
DM
COMMAND
ACTIVEA
WRITEA
PRECH
ACTIVEA
ACTIVEB WRITEA
WRITEB
tRCD tRAS tRC tRP tRRD
Normal Write Burst (@ BL=4)
Multi Bank Interleaving Write Burst (@ BL=4)
- 17 -
Rev 1.2(Mar. 2005)
K4D26323QG-GC
PACKAGE DIMENSIONS (144-Ball FBGA)
A1 INDEX MARK
128M GDDR SDRAM
12.0
12.0

0.8x11=8.8
0.10 Max A1 INDEX MARK
0.8
B C D E F G H J K L M N 13 12 11 10 9 8 7 6 5 4 3 2
0.8
0.8x11=8.8
0.45 0.05
0.40
0.35 0.05 1.40 Max
0.40

Unit : mm
- 18 -
Rev 1.2(Mar. 2005)

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