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MTV512M
Preliminary
8051 Embedded Monitor Controller 64K Flash Type
GENERAL DESCRIPTIONS The MTV512M micro-controller is an 8051 CPU core embedded device especially tailored for flat panel display applications. It includes an 8051 CPU core, 768-byte SRAM, 4 channels of 6-bit ADC, 3 external counters/timers, 6 channels of PWM DAC, VESA DDC interface, and a 64K-byte internal program Flash-ROM memory in 44-pin PLCC package. FEATURES * 8051 core, 12MHz operating frequency with single/double CPU clock option * 0.35um process; 3.3V power supply * * * * 768-byte RAM; 64K-byte program Flash memory Maximum 6 channels of PWM DAC Compliant with VESA DDC1/2B/2Bi/2B+ standard Dual slave IIC addresses; two H/W auto transfer DDC1/DDC2x data for both D-sub and DVI interfaces Watchdog timer with programmable interval Support external counters/timers, 1 & 2 Single/double frequency clock output Two external interrupts, INT1 is shared with Slave IIC interrupt source. Maximum 4 channels of 6-bit ADC Flash-ROM code protection selection 44-pin PLCC package
* * * * * * *
BLOCK DIAGRAM
P1.0-7 P3.0-2 P3.4
P0.0-7 P2.0-3 RD WR ALE INT1
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P0.0-7 P2.0-7 RD WR ALE INT1
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RST X1 X2 CKO
ADC
AD0-3
PWM DAC
DA0-5
P7.6-7 P6.0-7 P5.0-6
AUX I/O
DDC & IIC HSCL1 INTERFACE HSDA1
HSCL2 HSDA2
om .c 4u et he as at .d w w w
*This datasheet, which contains proprietary and trade secret information of MYSON CENTURY, INC., is confidential and subject to various privileges against unauthorized disclosure.
Myson Century, Inc. No. 2, Industry East Rd. III, Science-Based Industrial Park, Hsin-Chu, Taiwan Tel: 886-3-5784866 Fax: 886-3-5784349
sales@myson.com.tw www.myson.com.tw Rev. 0.4 August 25, 2003 page 1 of 1
www..com
8051 CORE
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XFR
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AUXRAM & DDCRAM1 & DDCRAM2
MTV512M
Preliminary
PIN CONNECTION
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MTV512M
Preliminary
PIN CONFIGURATION & DESCRIPTION A "CMOS output pin" means it can sink and drive at least 4mA current. It is not recommended to use such pin as input function. An "open drain pin" means it can sink at least 4mA current. It can be used as input or output function and needs an external pull up resistor. An "8051 standard pin" is a pseudo open drain pin. It can sink at least 4mA current when output is at low level, and drives at least 4mA current for 160nS when output transits from low to high, then keeps driving at 120A to maintain the pin at high level. It can be used as input or output function. It needs an external pull up resistor when driving heavy load device. There is an internal pull-up resistance on each CMOS PAD and an internal pull-down resistance on each input PAD. It is recommended to add a pull high resistance on each open drain pin.
Default Direction Default Output Value Internal Pull Up/Down -
Name NC
Pin No. 1
Direction -
DA0/P5.0
2
I/O
O
1(DA0)
' (1
O 1(DA2) O 1(DA3) O 1(DA4) O 1(P5.5) I Z(P5.6) I Z(P5.7) I 0 down I/O Z(HSCL1) I/O Z(HSDA1) -
DA1/P5.1
3
I/O
O
1(DA1)
DA2/P5.2
4
I/O
DA3/P5.3
5
I/O
1) ,
DA4/ P5.4
6
I/O
P5.5/DA5
7
I/O
P5.6/HSCL2
8
I/O
&2
P5.7/HSDA2
9
I/O
RST
10
I
HSCL1/P3.0/RXD
11
I/O
NC
12
-
HSDA1/P3.1/TXD0
13
I/O
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Pin Type Input -
Description
No connection
Open Drain PWM DAC output/General
purpose I/O (open drain)
Open Drain PWM DAC output/General
purpose I/O (open drain)
Open Drain PWM DAC output/General
purpose I/O (open drain)
Open Drain PWM DAC output/General
purpose I/O (open drain)
Open Drain PWM DAC output/General
purpose I/O (open drain)
Open Drain PWM DAC output/General
purpose I/O (open drain)
Open Drain General purpose I/O/Slave IIC1 SCL2 (open drain) w/ filter Open Drain General purpose I/O/Slave IIC1 SDA2 (open drain) w/ filter
High Active RESET
Open Drain Slave IIC clock/General purpose I/O/Rxd (open drain) w/ filter
No connection
Open Drain Slave IIC data/General purpose I/O/Txd (open drain) w/ filter
page 3 of 3
MTV512M
Preliminary
Name P3.2/INT0 Pin No. 14 Direction I/O Default Direction I Default Output Value Z(P3.2) Internal Pull Up/Down Pin Type Standard 8051 Standard 8051 Standard 8051 Standard 8051 CMOS Description
General purpose I/O/External interrupt 0 (Standard 8051) General purpose I/O/External interrupt 1 (Standard 8051) General purpose I/O/T0 Ext. Counter/Timer 0 (Standard 8051) General purpose I/O/T1 Ext. Counter/Timer 1 (Standard 8051) General purpose I/O /Clock out 2 (CMOS) General purpose I/O (CMOS)
P3.3/INT1
15
I/O
I
Z(P3.3)
-
P3.4/T0
16
I/O
I
Z(P3.4)
-
P3.5/T1
17
I/O
I
Z(P3.5)
-
P7.6/CLKO2
18
I/O
I
1(P7.6)
up
P7.7
19
I/O
I
1
X2
20
O
-
-
X1
21
I
-
-
' (1
I 1(P6.0) up I 1(P6.1) up I 1(P6.2) up I 1(P6.3) up I 1 up I 1 up I 1(P6.6) up I 1 up
VSS
22
-
NC
23
-
P6.0/AD0
24
I/O
1) ,
I/O I/O I/O I/O I/O I/O I/O
P6.1/AD1
25
P6.2/AD2
26
&2
P6.3/AD3
27
P6.4
28
P6.5
29
P6.6/CLKO1
30
P6.7
31
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up CMOS Ground
Crystal Out
Crystal In
-
No connection
CMOS
General purpose I/O (CMOS) /6-bit ADC channel 0 input General purpose I/O (CMOS) /6-bit ADC channel 1 input General purpose I/O (CMOS) /6-bit ADC channel 2 input General purpose I/O (CMOS) /6-bit ADC channel 3 input General purpose I/O (CMOS)
CMOS
CMOS
CMOS
CMOS
CMOS
General purpose I/O (CMOS)
CMOS
General purpose I/O/CLKO1 (CMOS) General purpose I/O (CMOS)
CMOS
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MTV512M
Preliminary
Name VSYNC Pin No. 32 Direction I Default Direction I Default Output Value 0 Internal Pull Up/Down down Pin Type Input Description
VSYNC input
NC
33
-
-
-
-
-
No connection
NC
34
-
-
-
-
-
No connection
NC
35
-
-
-
-
-
No connection
P1.7
36
I/O
I
Z
-
P1.6
37
I/O
I
Z
-
P1.5
38
I/O
I
Z
-
P1.4
39
I/O
I
Z
-
P1.3
40
I/O
I
Z
-
P1.2
41
I/O
I
Z
-
P1.1
42
I/O
I
Z
-
1) ,
I/O I -
P1.0/ET2
43
Z(P1.0)
-
VCC
44
-
-
Standard 8051 or CMOS Standard 8051 or CMOS Standard 8051 or CMOS Standard 8051 or CMOS Standard 8051 or CMOS Standard 8051 or CMOS Standard 8051 or CMOS Standard 8051 or CMOS -
General purpose I/O (Standard 8051/CMOS) General purpose I/O (Standard 8051/CMOS) General purpose I/O (Standard 8051/CMOS) General purpose I/O (Standard 8051/CMOS) General purpose I/O (Standard 8051/CMOS) General purpose I/O (Standard 8051/CMOS) General purpose I/O (Standard 8051/CMOS) General purpose I/O/External Counter/Timer2 (Standard 8051/CMOS) 3.3V power
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MTV512M
Preliminary
Pin Types
4mA
10uA
120uA
2 OSC period delay 4mA Output Data Input Data
Pin
8051 Standard Pin
Input Data 4mA Output Data
Open Drain Pin
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Pin Output Data Input Data
LPF Input Data 4mA Output Data
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Input Data 10A
Pin
Pin
Inputs
4mA Pin 4mA
10A
Open Drain with Filter Pin
1) ,
CMOS
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MTV512M
Preliminary
FUNCTIONAL DESCRIPTIONS 8051 CPU Core The CPU core of MTV512M is compatible with the industry standard 8051, which includes 256 bytes RAM, Special Function Registers (SFR), two timers, five interrupt sources and a serial UART interface. The CPU core fetches its program code from the 64K bytes Flash memory in MTV512M. It uses Port0 and Port2 to access the "external special function register" (XFR) and external auxiliary RAM (AUXRAM). The CPU core can run at double rate when FclkE is set. When the operating X'tal is 12MHz, Once the bit is set, the CPU runs as if a 24MHz X'tal is applied on MTV512M, but the peripherals (IIC, DDC, Etimer, ADC, DAC) still run at the original frequency. Note: All registers listed in this document reside in 8051's external RAM area (XFR). For internal RAM memory map, please refer to 8051 spec.
i) Internal Special Function Registers (SFR)
The SFR is a group of registers that are the same as standard 8051. ii) Internal RAM
There are total 256 bytes internal RAM in MTV512M, the same as standard 8052. iii) External Special Function Registers (XFR)
The XFR is a group of registers allocated in the 8051 external RAM area F00h - FFFh. These registers are used for special functions. Programs can use "MOVX" instruction to access these registers. iv) Auxiliary RAM (AUXRAM)
There are total 256 bytes auxiliary RAM allocated in the 8051 external RAM area 800h - 8FFh. Programs can use "MOVX" instruction to access the AUXRAM. v) Dual Port RAM (DDCRAM)
There are 256 bytes Dual Port RAM allocated in the 8051 external RAM area E00h - EFFh. Programs can use "MOVX" instruction to access the RAM. The external DDC1/2 Host can access the RAM as if a 24LC0x EEPROM is connected onto the interface. Address from E00h to E7Fh is for external DDC host1 to access the DDC data. Address from E80h to EFFh is for external DDC host2.
FFh
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SFR
FFFh Accessible by direct addressing F00h
' (1
XFR
Accessible by indirect external RAM addressing (Using MOVX instruction)
Internal RAM
Accessible by indirect addressing only (Using MOV A,@Ri instruction)
80h 7Fh
Internal RAM
Accessible by direct and indirect addressing
00h
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EFFh
Memory Allocation
DDCRAM2
Accessible by indirect external RAM addressing (Using MOVX Instruction)
E80h E7Fh
DDCRAM1
Accessible by indirect external RAM addressing (Using MOVX Instruction)
8FFh E00h 8FFh
AUXRAM
Accessible by indirect external RAM addressing (Using MOVX Instruction)
800h
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MTV512M
Preliminary
Chip Configuration The Chip Configuration registers define configuration of the chip and function of the pins.
Reg name PADMOD PADMOD PADMOD PADMOD PADMOD PADMOD OPTION PADMOD PADMOD addr F50h(w) F51h(w) F52h(w) F53h(w) F54h(w) F55h(w) F56h(w) F5Eh(w) F5Fh(w) P77oe HIIC1E P57oe P67oe COP17 PWMF P56oe P66oe COP16 DIV253 CKOE2 P76oe P55E HIIC2E P55oe P65oe COP15 FclkE P54E CKOE1 P54oe P64oe COP14 DCLK P53oe P63oe COP13 ENSCL P52oe P62oe COP12 P51oe P61oe COP11 P50oe P60oe COP10 IP77E bit7 bit6 bit5 bit4 bit3 AD3E P53E bit2 AD2E P52E bit1 AD1E P51E bit0 AD0E P50E
PADMOD (w) : Pad mode control registers. (All are "0" in Chip Reset, except for HIIC1E bit) AD3E AD2E AD1E AD0E P55E P54E P53E P52E =1 =0 =1 =0 =1 =0 =1 =0 =1 =0 =1 =0 =1 =0 =1 =0 Pin "P6.3/AD3" is AD3. Pin "P6.3/AD3" is P6.3. Pin "P6.2/AD2" is AD2. Pin "P6.2/AD2" is P6.2. Pin "P6.1/AD1" is AD1.
Pin "P6.1/AD1" is P6.1. Pin "P6.0/AD0" is AD0.
Pin "P6.0/AD0" is P6.0. Pin "DA5/P5.5" is P5.5. Pin "DA5/P5.5" is DA5.
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P51E =1 =0 P50E =1 =0 HIIC1E = 1 =0 HIIC2E = 1 =0 CKOE1 = 1 =0
1) ,
Pin "DA4/P5.4" is P5.4. Pin "DA4/P5.4" is DA4. Pin "DA3/P5.3" is P5.3. Pin "DA3/P5.3" is DA3. Pin "DA2/P5.2" is P5.2. Pin "DA2/P5.2" is DA2. Pin "DA1/P5.1" is P5.1. Pin "DA1/P5.1" is DA1. Pin "DA0/P5.0" is P5.0. Pin "DA0/P5.0" is DA0. Pin "HSCL1/P3.0/Rxd" is HSCL1; Pin "HSCL1/P3.0/Rxd" is P3.0/Rxd; Pin "HSCL2/P5.6" is HSCL2. Pin "HSCL2/P5.6" is P5.6. Pin "P6.6/CLKO1" is P6.6. Pin "P6.6/CLKO1" is CLKO1. pin "HSDA1/P3.1/Txd" is HSDA1. pin "HSDA1/P3.1/Txd" is P3.1/Txd. Pin "HSDA2/P5.7" is HSDA2. Pin "HSDA2/P5.7" is P5.7.
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MTV512M
Preliminary
P57oe = 1 =0 P56oe = 1 =0 P55oe = 1 =0 P54oe = 1 =0 P53oe = 1 =0 P52oe = 1 =0 P51oe = 1 =0 P50oe = 1 =0 P67oe = 1 =0 P66oe = 1 =0 P65oe = 1 =0 P64oe = 1 =0 P63oe = 1 =0 P62oe = 1 =0 P61oe = 1 =0 P60oe = 1 =0 P5.7 is output pin. P5.7 is input pin. P5.6 is output pin. P5.6 is input pin. P5.5 is output pin. P5.5 is input pin. P5.4 is output pin. P5.4 is input pin. P5.3 is output pin. P5.3 is input pin. P5.2 is output pin. P5.2 is input pin. P5.1 is input pin. P5.0 is output pin. P5.0 is input pin. P6.7 is output pin. P6.7 is input pin. P6.6 is output pin. P6.6 is input pin.
P6.5 is output pin. P6.5 is input pin.
P6.4 is output pin. P6.4 is input pin.
P6.3 is output pin. P6.3 is input pin.
&2
COP17 = 1 =0 COP16 = 1 =0 COP15 = 1 =0 COP14 = 1 =0 COP13 = 1 =0 COP12 = 1
1) ,
P6.2 is output pin. P6.2 is input pin. P6.1 is output pin. P6.1 is input pin. P6.0 is output pin. P6.0 is input pin. Pin "P1.7" is CMOS Output. Pin "P1.7" is 8051 standard I/O. Pin "P1.6" is CMOS Output. Pin "P1.6" is 8051 standard I/O. Pin "P1.5" is CMOS Output. Pin "P1.5" is 8051 standard I/O. Pin "P1.4" is CMOS Output. Pin "P1.4" is 8051 standard I/O. Pin "P1.3" is CMOS Output. Pin "P1.3" is 8051 standard I/O. Pin "P1.2" is CMOS Output.
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P5.1 is output pin.
MTV512M
Preliminary
=0 COP11 = 1 =0 COP10 = 1 =0 P77oe = 1 =0 P76oe = 1 =0 IP77E = 1 =0 CKOE2 = 1 =0 OPTION (w) : Pin "P1.2" is 8051 standard I/O. Pin "P1.1" is CMOS Output. Pin "P1.1" is 8051 standard I/O. Pin "P1.0" is CMOS Output. Pin "P1.0" is 8051 standard I/O. P7.7 is output pin. P7.7 is input pin. P7.6 is output pin. P7.6 is input pin. Pin "P7.7 is P7.7. Available in ICE Mode only. reserved. Pin "P7.6/CLKO2" is CLKO2.
Chip option configuration (All are "0" in Chip Reset). Selects 94KHz PWM frequency. Selects 47KHz PWM frequency. =0
PWMF = 1 DIV253 = 1 =0 FclkE =1 =0 DCLK = 1 =0 ENSCL = 1
PWM pulse width is 253-step resolution. CPU is running at double rate
PWM pulse width is 256-step resolution. CPU is running at normal rate
CLKO1 & CLKO2 outputs double frequency system clock. CLKO1 & CLKO2 outputs single frequency system clock. Enable slave IIC block to hold HSCL pin low while MTV512M is unable to catch-up with the external master's speed.
I/O Ports i) Port1
ii) P3.0-2, P3.4
If these pins are not set as IIC pins, Port3 can be used as general purpose I/O, interrupt, UART and Timer pins. Behavior of Port3 is the same as standard 8051. iii) Port5, Port6 and Port7 Port5, Port6 and Port7 are used as general purpose I/O. S/W needs to set the corresponding P5(n)oe and P6(n)oe to define whether these pins are input or output.
Reg name PORT5 PORT5 PORT5 PORT5 addr F30h(r/w) F31h(r/w) F32h(r/w) F33h(r/w) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 P50 P51 P52 P53 page 10 of 10
&2
Port1 is a group of pseudo open drain pins or CMOS output pins. It can be used as general purpose I/O. Behavior of Port1 is the same as standard 8051.
1) ,
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Pin "P7.6/CLKO2" is P7.6.
MTV512M
Preliminary
PORT5 PORT5 PORT5 PORT5 PORT6 PORT6 PORT6 PORT6 PORT6 PORT6 PORT6 PORT6 PORT7 PORT7 F34h(r/w) F35h(r/w) F36h(r/w) F37h(r/w) F38h(r/w) F39h(r/w) F3Ah(r/w) F3Bh(r/w) F3Ch(r/w) F3Dh(r/w) F3Eh(r/w) P54 P55 P56 P57 P60 P61 P62 P63 P64 P65 P66
F76h(r/w) F77h(r/w)
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bit5 bit4 bit3 bit2 bit1 Pulse width of PWM DAC 0 Pulse width of PWM DAC 1 Pulse width of PWM DAC 2 Pulse width of PWM DAC 3 Pulse width of PWM DAC 4 Pulse width of PWM DAC 5
F3Fh(r/w)
P67 P76 P77
PORT5 (r/w) : PORT6 (r/w) :
Port 5 data input/output value. Port 6 data input/output value.
PWM DAC
Each output pulse width of PWM DAC converter is controlled by an 8-bit register in XFR. The frequency of PWM clock is 47KHz or 94KHz, selected by PWMF. And the total duty cycle step of these DAC outputs is 253 or 256, selected by DIV253. If DIV253=1, writing FDH/FEH/FFH to DAC register generates stable high output. If DIV253=0, the output pulses low at least once even if the DAC register's content is FFH. Writing 00H to DAC register generates stable low output.
Reg name DA0 DA1 DA2 DA3 DA4 DA5 addr
1) ,
bit7 bit6
' (1
bit0
F20h(r/w) F21h(r/w) F22h(r/w) F23h(r/w) F24h(r/w) F25h(r/w)
DA0-5 (r/w) : The output pulse width control for DA0-5. * All of PWM DAC converters are centered with value 80h after power on.
DDC & IIC Interface i) DDC1/DDC2x Mode, DDCRAM1/DDCRAM2 and SlaveA1/SlaveA2 Block The MTV512M supports VESA DDC for both D-sub and DVI interfaces through HSCL1/HSDA1 and HSCL2/HSDA2 pins. The HSCL1/HSDA1 pins access DDCRAM1 by SlaveA1, and the HSCL2/HSDA2 pins access DDCRAM2 by SlaveA2. The MTV512M enters DDC1 mode for both DDC channels after Reset. In this mode, VSYNC is used as data clock. The HSCL1/HSCL2 pin should remain at high. The data output to the HSDA1/HSDA2 pin is taken from a shift register in MTV512M. The shift register automatically fetches EDID
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MTV512M
Preliminary
data from the lower 128 bytes of the Dual Port RAM (DDCRAM1/DDCRAM2), then sends it in 9-bit packet formats inclusive of a null bit (=1) as packet separator. S/W may enable/disable the DDC1 function by setting/clearing the DDC1en control bit. The MTV512M switches to DDC2x mode when it detects a high to low transition on the HSCL1/HSCL2 pin. In this mode, the SlaveA1/SlaveA2 IIC block automatically transmits/receives data to/from the IIC Master. The transmitted/received data is taken-from/saved-to the DDCRAM1/DDCRAM2. In simple words, MTV512M can behave as two 24LC0x EEPROMs. The only thing S/W needs to do is to write the EDID data to DDCRAM1/DDCRAM2. These slave addresses of SlaveA1/SlaveA2 block can be chosen by S/W as 5-bit, 6-bit or 7-bit. For example, if S/W chooses 5-bit slave address as 10100b, the SlaveA1 IIC block then responds to slave address 10100xxb. The SlaveA1/SlaveA2 can be enabled/disabled by setting/clearing the EnslvA1/EnslvA2 bit. The DDCRAM1/DDCRAM2 can/cannot be written by the IIC Master by setting/clearing the EN128w bit. The MTV512M returns to DDC1 mode if HSCL1 is kept high for 128 VSYNC clock period. However, it locks in DDC2B mode if a valid IIC address (1010xxxb) has been detected on HSCL1/HSDA1 buses. The DDC2 flag reflects the current DDC status, S/W may clear it by writing a "0" to it.
ii) SlaveB Block
The SlaveB IIC block is connected to HSDA1 and HSCL1 pins only. This block can receive/transmit data using IIC protocols. S/W may write the SLVBADR register to determine the slave addresses. In receive mode, the block first detects IIC slave address matching the condition then issues a SlvBMI interrupt. The data from HSDA1 is shifted into shift register then written to RCBBUF register when a data byte is received. The first byte loaded is word address (slave address is dropped). This block also generates a RCBI (receives buffer full interrupt) every time when the RCBBUF is loaded. If S/W is not able to read out the RCBBUF in time, the next byte in shift register is not written to RCBBUF and the slave block returns NACK to the master. This feature guarantees the data integrity of communication. The WadrB flag can tell S/W whether the data in RCBBUF is a word address or not. In transmit mode, the block first detects IIC slave address matching the condition, then issues a SlvBMI interrupt. In the meantime, the data pre-stored in the TXBBUF is loaded into shift register, resulting in TXBBUF emptying and generates a TXBI (transmit buffer empty interrupt). S/W should write the TXBBUF a new byte for the next transfer before shift register empties. A failure of this process causes data corruption. The TXBI occurs every time when shift register reads out the data from TXBBUF. The SlvBMI is cleared by writing "0" to corresponding bit in INTFLG register. The RCBI is cleared by reading out RCBBUF. The TXBI is cleared by writing TXBBUF.
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MTV512M
Preliminary
HSCL
Slave IIC Receive Timing
HSDA
5
0: The SLVAADR=40h before the transfer 1: H/W returns an ACK and triggers SlvAM as slave address match. 2: The SlvAMI is reset by S/W writing 0 to
SlvAMI /WR_INTFLG
1
2
3: RCAIarises when a new byte loaded int the RCABUF, H/W returns an ACK in th meantime.
F0 63 C0
RCABUF
XX
4: When S/W reads RCABUF, the RCAI is reset and SCL hold condition is released 5: H/W returns a NACK because S/W has not read out the RCABUF in time, the RCABUF keeps its old value. 6: H/W can hold SCL low at byte section if S/W sets ENSCL bit.
RCAI /RD_RCABUF SCLOUT
3
3
3
4 6
4 6 6
WadrA SLVS SlvRWB
HSCL HSDA
Slave IIC Transmit Timing
5
SlvAMI /WR_INTFLG TXABUF
1
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8 9
tR tACKST tR tACKSP
0: The SLVAADR=40h and TXABUF=F0h before the transfer. 1: H/W returns an ACK and triggers SlvAMI as slave address match. 2: The SlvAMI is reset by S/W writing 0 to it. 3: TXAI arises when the shift register is loaded from the TXABUF; result in TXABUF empty. 4: When S/W writes TXABUF, the TXAI is reset and SCL hold condition is released. 5: H/W sends the old data because S/W has not updated TXABUF in time. 6: H/W can hold SCL low at byte section if S/W sets ENSCL bit.
2
F0
63
C0
TXAI /WR_TXABUF SCLOUT
3
3
3
4 6 6
4
6
SAckin SLVS SlvRWB
Figure 1. Slave IIC Timing Diagram (Transmit and Receive)
Slave Transmission Timing in Writing Mode
SCL
DATA IN
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DATA OUT
1) ,
1
Figure 2. Slave Ack Timing in Write Mode
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MTV512M
Preliminary
SCL
1
8
9
DATA OUT
tR THD;DAT
Figure 3. Slave Data Transmission Timing in Read Mode Parameter
Time interval from SCL falling** edge (under VIL) to data starting to update (10% or 90% swing) Time interval from SCL falling edge (under VIL) to slave starting to update (10% swing) Time interval from SCL falling edge (under VIL) to slave starting to update (10% swing) SDA rise time by slave IIC (10% to 90% swing) SDA fall time by slave IIC (90% to 90% swing)
Symbol tHD;DAT tACKST tACKSP tR tF
time
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TBUF THD;STA
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2 x sysclk 2 x sysclk 123.9ns 0.85ns Min 600ns 600ns 1300ns
min 2 x sysclk *
max 3 x sysclk 3 x sysclk 3 x sysclk
127.1nsns 2.79ns
*sysclk is the clock input on X1. It is 83ns for 12MHz crystal. **SCL falling means when SCL drop below VIL of IIC PAD, which is 1.0 volt in typical case.
SCL
DATA OUT
&2
Parameter
1) ,
TSU;STO
Acceptable IIC start/stop Timing
Figure 4. Acceptable IIC Start/Stop Timing
Symbol tSU;STO tHD;STA tBUF Max -
Time interval from SCL rising edge (over VIH) to SDA rising edge (10% swing) Time interval from SDA rising edge to SCL falling edge (90% swing) Bus free time between stop and start (from 90% to 90%
page 14 of 14
MTV512M
Preliminary
swing)
Reg name IICCTR IICSTUS INTFLG INTFLG INTEN DDCCTRA1 SLVA1ADR RCBBUF TXBBUF SLVBADR CTRSLVB CTRSLVB DDCCTRA2 SLVA2ADR
addr F00h (r/w) F01h (r) F03h (r) F03h (w) F04h (w) F06h (w) F07h (w) F08h (r) F08h (w) F09h (w) F0Ah (r) F0Ah (w) F86h (w) F87h (w)
bit7 DDC2A1 WadrB TXBI
bit6 DDC2A2
bit5
bit4
bit3
bit2
bit1
bit0
SlvRWB RCBI SlvBMI SlvBMI
SAckIn STOPI STOPI ESTOPI Rev1
SLVS ReStaI ReStaI EReStaI WslvA1I WslvA1I EWSlvA1I WslvA2I WslvA2I EWSlvA2I SlvA1bs1 SlvA1bs0
ETXBI DDC1en ENSlvA1
ERCBI En128W
ESlvBMI Rev0
Slave A1 IIC address Slave B IIC receive buffer
Slave B IIC transmit buffer ENSlvB
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Slave B IIC address Rev1 Slave A2 IIC address
SlvBa1
SlvBa0 SlvBbs0 SlvA2bs0
DDC1en ENSlvA2
En128W
' (1
Rev0
SlvBbs1
SlvA2bs1
IICCTR (r/w) :
IIC interface status/control register. =0
DDC2A1 = 1 DDC2A2 = 1 =0 IICSTUS (r) :
IIC interface status register.
INTFLG (w) :
&2
WadrB = 1 =0 SlvRWB = 1 SAckIn = 1 SLVS =1 SlvBMI = 1 =0 STOPI = 1 =0 ReStaI = 1
Interrupt flag. An interrupt event will set its individual flag, and, if the corresponding interrupt enable bit is set, the 8051 INT1 source will be driven by a zero level. Software MUST clear this register while serving the interrupt routine. No action. Clears SlvBMI flag. No action. Clears STOPI flag. No action.
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1) ,
DDC2 is active for HSCL1/HSDA1 pins. MTV512M remains in DDC1 mode for HSCL1/HSDA1 pins. DDC2 is active for HSCL2/HSDA2 pins. MTV512M remains in DDC1 mode for HSCL2/HSDA2 pins. The data in RCBBUF is word address. Current transfer is slave transmit Current transfer is slave receive The external IIC host respond NACK. The slave block has detected a START, cleared when STOP detected.
MTV512M
Preliminary
=0 WslvA1I = 1 =0 WslvA2I = 1 =0 MbufI =1 =0 INTFLG (r) : TXBI RCBI Clears ReStaI flag. No action. Clears WslvA1I flag. No action. Clears WslvA2I flag. No action. Clears Master IIC bus interrupt flag (MbufI). Indicates the TXBBUF need a new data byte, cleared by writing TXBBUF. Indicates the RCBBUF has received a new data byte, cleared by reading RCBBUF. Indicates the slave IIC address B match condition. Indicates the slave IIC has detected a STOP condition for HSCL1/HSDA1 pins.
Interrupt flag. =1 =1
SlvBMI = 1 STOPI = 1 ReStaI = 1 WslvA1I = 1 WslvA2I = 1
Indicates the slave A1 IIC has detected a STOP condition of write mode. Indicates the slave A2 IIC has detected a STOP condition of write mode.
INTEN (w) :
Interrupt enable. Enables TXBBUF interrupt. Enables RCBBUF interrupt.
ETXBI = 1 ERCBI = 1 ESlvBMI = 1 ESTOPI = 1 EReStaI = 1 EWSlvA1I = 1 EWSlvA2I = 1
Enables slave address B match interrupt. Enables IIC bus STOP interrupt. Enables IIC bus repeat START interrupt.
Enables slave A1 IIC bus STOP of write mode interrupt. Enables slave A2 IIC bus STOP of write mode interrupt.
DDCCTRA1 (w) : DDC interface control register for HSCL1, HSDA1 pins. DDC1en = 1 =0 En128W = 1 Rev0 =0 Enables DDC1 data transfer in DDC1 mode. Disables DDC1 data transfer in DDC1 mode. The 128 bytes of DDCRAM1 can be written by IIC master. The 128 bytes of DDCRAM1 cannot be written by IIC master. reserved Normal operation. Normal operation.
SLVA1ADR (w) : Slave IIC block A1's enable and address. EnslvA1= 1 =0 Enables slave IIC block A1. Disables slave IIC block A1.
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&2
=1 =0 Rev1 =1 = 1,0 = 0,1 = 0,0
=0 reserved SlvA1bs1,SlvA1bs0 : Slave IIC block A1's slave address length. 5-bit slave address. 6-bit slave address. 7-bit slave address.
1) ,
' (1
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Indicates the slave IIC has detected a repeat START condition for HSCL1/HSDA1 pins.
MTV512M
Preliminary
bit6-0 : RCBBUF (r) : Slave IIC address A1 to which the slave block should respond. Slave IIC block B receives data buffer.
TXBBUF (w) : Slave IIC block B transmits data buffer. SLVBADR (w) : Slave IIC block B's enable and address. ENslvB = 1 =0 bit6-0 : Enables slave IIC block B. Disables slave IIC block B. Slave IIC address B to which the slave block should respond.
CTRSLVB (r/w) : Slave IIC block B's Control registers. SlvBbs1,SlvBbs0 : Slave IIC block B's slave address length. = 1,0 = 0,1 5-bit slave address. 6-bit slave address.
DDCCTRA2 (w) : DDC interface control register for HSCL2, HSDA2 pins. DDC1en = 1 =0 En128W = 1 =0 Rev0 Rev1 =1 =0 =1 Enables DDC1 data transfer in DDC1 mode. Disables DDC1 data transfer in DDC1 mode.
The 128 bytes of DDCRAM2 cannot be written by IIC master. reserved Normal operation.
Normal operation.
=0 reserved SlvA2bs1,SlvA2bs0 : Slave IIC block A2's slave address length.
SLVA2ADR (w) : Slave IIC block A2's enable and address. EnslvA2= 1 =0 bit6-0 :
A/D converter
The MTV512M is equipped with 4 VDD range 6-bit A/D converters. The ADC conversion range is from VSS to VDD, S/W can select the current convert channel by setting the SADC1/SADC0 bit. The refresh rate for the ADC is OSC freq./2304 (192us for 12MHz X'tal). The ADC compares the input pin voltage with internal VDD*N/64 voltage (where N = 0 - 63). The ADC output value is N when pin voltage is greater than VDD*N/64 and smaller than VDD*(N+1)/64.
Reg name ADC ADC WDT addr F10h (w) F10h (r) F18h (w) WEN WCLR bit7 ENADC bit6 bit5 bit4 bit3 SADC3 ADC convert result WDT2 WDT1 WDT0 bit2 SADC2 bit1 SADC1 bit0 SADC0
&2
1) ,
= 1,0 = 0,1 = 0,0 Enables slave IIC block A2.
5-bit slave address. 6-bit slave address. 7-bit slave address.
Disables slave IIC block A2. Slave IIC address A2 to which the slave block should respond.
' (1
The 128 bytes of DDCRAM2 can be written by IIC master.
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= 0,0 7-bit slave address. SlavBa1 : Bit1 of received Slave B IIC address. SlavBa0 : Bit0 of received Slave B IIC address.
MTV512M
Preliminary
Low Power Reset (LVR) & Watchdog Timer When the voltage level of power supply is below 2.4V (+/-0.4V) for a specific period of time, the LVR generates a chip reset signal. After the power supply is above 2.4V (+/-0.4V), LVR maintains in reset state for 144 X'tal cycle to guarantee the chip exit reset condition with a stable X'tal oscillation. The Watchdog Timer automatically generates a device reset when it is overflowed. The interval of overflow is 0.25 sec x N, when N is a number from 1 to 8, and can be programmed via register WDT (2:0). The timer function is disabled after power on reset, users can activate this function by setting WEN, and clear the timer by setting WCLR. WDT (w) : WEN WCLR Watchdog Timer control register. =1 =1 =1 =2 =3 =4 =5 =6 =7 ADC (w) : ENADC SADC0 SADC1 SADC2 SADC3 ADC (r) : Etimer ADC control. =1 =1 =1 =1 =1 Enables ADC. Selects ADC0 pin input. Selects ADC1 pin input. Selects ADC2 pin input. Selects ADC3 pin input. Enables Watchdog Timer. Clears Watchdog Timer. Overflow interval = 8 x 0.25 sec. Overflow interval = 1 x 0.25 sec. Overflow interval = 3 x 0.25 sec. Overflow interval = 4 x 0.25 sec. Overflow interval = 5 x 0.25 sec. Overflow interval = 6 x 0.25 sec. Overflow interval = 7 x 0.25 sec. Overflow interval = 2 x 0.25 sec.
WDT2: WDT0 = 0
ADC convert result.
1. Capture mode
In the capture mode, if EXEN2 = 0, Etimer is a 16-bit timer or counter. When EXEN2 = 0, Etimer counters up to FFFFh and then set TF2 upon overflow. This bit will generate an interrupt (INT1) to 8051. If EXEN2 = 1, Etimer capture the current value in THET-TLET into RCAPETH-RCAPETL, respectively when 1 0 transition at Port. 1.1. This will also generate an interrupt. 2. Auto-reload mode Etimer can be programmed to count-up or down when in auto-reload mode. This feature is selected by DCEN in SFR ETMOD. If EXEN2 = 0, Etimer counts up to 0FFFFh and then set TF2 (overflow). At this mode, the counter is reloaded the 16-bit value from RCAPETH-RCAPETL. If EXEN2 = 1, the reload function can be triggered by overflow or by 1 0 transition at Port 1.1.
ETCTR F88h (w) TF2 EXF2 EXEN2 TR2 C/T2 CP/RL2
&2
The Etimer is a 16-bit Timer/Counter which provide capture/reload functions like timer2 in 8052. The type is selected by C/T2 in the SFRETCTR. Etimer has 2 modes, capture/auto-reload (up or down counting). The modes are selected by CP/RLS in ETCTR. Etimer contains two 8-bit registers, TLET and THET. When it is used in the timer mode, THET-TLET count rate is 1/12 of the oscillator frequency. In the counter mode, the counter is incremented when 1 0 transition at Port 1.0,
1) ,
' (1
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MTV512M
Preliminary
F88h (r) F89h (w) F89h (r) F8Ah (w) F8Ah (r) F8Bh (w) F8Bh (r) F8Ch (w) F8Ch (r) F8Dh (w) F8Dh (r) F8Eh (w) TF2 EXF2 EXEN2 TR2 C/T2 CP/RL2 DCEN DCEN
ETMOD THET TLET RCAPETH RCAPETL EINT1PEN
THET THET TLET TLET RCAPETH RCAPETH RCAPETL RCAPETL EEINT1 ETE TSTP1
ETCTR (w): TF2 EXF2 EXEN2 TR2 C/T2 CP/RL2 ETCTR (r): TF2 EXF2 EXEN2 TR2 C/T2 CP/RL2
Etimer control register =0 =1 =0 =1 =0 =1 =0 =1 =0 =1 Clear Etimer overflow interrupt No actions
Clear Etimer external capture / reload interrupt Enable Port 1.1 capture / reload trigger Enable Etimer Disable Port 1.1 capture / reload trigger Disable Etimer
Etimer functions as a counter Etimer functions as a timer Set Etimer in Capture mode
=0 Set Etimer in Auto-reload mode Etimer control register
THET (w/r): Etimer high 8-bit register TLET (w/r): Etimer low 8-bit register RCAPETH(w/r): Etimer high 8-bit capture/reload register RCAPETL(w/r): Etimer high 8-bit capture/reload register EINT1PEN(w): External interrupt control ETINT1 (w): ETE (w): TSTP1 (w): =1 =0 =1 =0 =1 =0 Enable P3.3 as external interrupt1 trigger Disable P3.3 as external interrupt1 trigger Enable Etimer interrupt Disable Etimer interrupt Reserved Normal operation
&2
1) ,
= = EXF2 state TR2 state CT2 state = EXEN2 state = = = CP/RL2 state
TF2 state
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=1
No actions
MTV512M
Preliminary
VSYNC Interrupt The MTV512M checks the VSYNC input pulse and generates an interrupt at its leading edge. The VSYNC flag is set each time when MTV512M detects a VSYNC pulse. The flag is cleared by S/W writing a "0". INTFLG INTEN F48h(r/w) F49h(w) Vsync EVsync
INTFLG(w): Interrupt flag. An interrupt event will set its individual flag, and, if the corresponding interrupt enable bit is set, the INT1 source of 8051 core will be driven by a zero level. Software MUST clear this register while serving the interrupt routine. Vsync = 1 No action. = 0 Clears VSYNC interrupt flag. INTFLG(r): Interrupt flag. INTEN(w):
EVsync = 1 Enables VSYNC interrupt.
&2
1) ,
' (1
page 20 of 20
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Vsync = 1 Indicates a VSYNC interrupt. Interrupt enable.
MTV512M
Preliminary
Memory Map of XFR
Reg name IICCTR IICSTUS INTFLG INTFLG INTEN DDCCTRA1 SLVA1ADR RCBBUF TXBBUF SLVBADR CTRSLVB CTRSLVB ADC ADC WDT DA0 DA1 DA2 DA3 DA4 DA5 PORT5 PORT5 PORT5 PORT5 PORT5 PORT5 PORT5 PORT6 PORT6 addr F00h (r/w) F01h (r) F03h (r) F03h (w) F04h (w) F06h (w) F07h (w) F08h (r) F08h (w) F09h (w) F0Ah (r) F0Ah (w) F10h (w) F10h (r) F18h (w) F20h(r/w) F21h(r/w) F22h(r/w) F23h(r/w) F24h(r/w) F25h(r/w) F30h(r/w) F31h(r/w) F32h(r/w) F33h(r/w) F34h(r/w) F35h(r/w) F36h(r/w) F38h(r/w) F39h(r/w) WEN WCLR ENADC ENSlvB ETXBI DDC1en ENSlvA ERCBI En128W bit7 DDC2A1 WadrB TXBI RCBI bit6 DDC2A 2 SlvRWB SlvBMI SlvBMI ESlvBMI Rev0 SAckIn STOPI STOPI ESTOPI Rev1 Slave A IIC address Slave B IIC receives buffer SLVS ReStaI ReStaI EReStaI WSlvAI WSlvAI EWSlvA I WslvA2I WslvA2I EWSlvA 2I SlvAbs1 SlvAbs0 bit5 bit4 bit3 bit2 bit1 bit0
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Slave B IIC address SADC3 SADC2 ADC convert Result WDT2 DA10E P54E AD3E P53E AD2E P52E
Slave B IIC transmits buffer
SlvBa1
SlvBa0 SlvBbs0 SADC0
SlvBbs1 SADC1
WDT1
WDT0
1) ,
' (1
DA13E P57E DA12E P56E DA11E P55E
Pulse width of PWM DAC 0 Pulse width of PWM DAC 1 Pulse width of PWM DAC 2 Pulse width of PWM DAC 3 Pulse width of PWM DAC 4 Pulse width of PWM DAC 5 P50 P51 P52 P53 P54 P55 P56 P60 P61 P62 P63 P64 P65 P66 P67 AD1E P51E AD0E P50E
PORT6 PORT6 PORT6 PORT6 PORT6 PORT6 PADMOD PADMOD
&2
F3Ah(r/w) F3Bh(r/w) F3Ch(r/w) F3Dh(r/w) F3Eh(r/w) F3Fh(r/w) F50h(w) F51h(w)
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MTV512M
Preliminary
PADMOD PADMOD PADMOD PADMOD OPTION PADMOD PADMOD PORT7 PORT7 DDCCTRA2 SLVA2ADR F52h(w) F53h(w) F54h(w) F55h(w) F56h(w) F5Eh(w) F5Fh(w) F76h(r/w) F77h(r/w) F86h (w) F87h (w) DDC1en ENSlvA2 En128W Rev0 Rev1 Slave A2 IIC address SlvA2bs 1 P77oe HIIC1E P57oe P67oe COP17 PWMF IIICE P56oe P66oe COP16 DIV253 P76E P76oe P76 P77 SlvA2bs 0 HIIC2E P55oe P65oe COP15 FclkE CKOE P54oe P64oe COP14 DCLK P53oe P63oe COP13 ENSCL P52oe P62oe COP12 P51oe P61oe COP11 P50oe P60oe COP10 IP77E
ETCTR
F88h (w) F88h (r)
TF2 TF2
EXF2 EXF2
RCLK RCLK
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TCLK EXEN2 TR2 TCLK EXEN2 TR2 THET THET TLET TLET RCAPETH RCAPETH RCAPETL RCAPETL
C/T2 C/T2
CP/RL2 CP/RL2 DCEN DCEN
ETMOD
F89h (w) F89h (r) F8Ah (w) F8Ah (r) F8Bh (w) F8Bh (r) F8Ch (w) F8Ch (r) F8Dh (w) F8Dh (r)
EINT1PEN
F8Eh (w)
&2
1) ,
EEINT1 ETE
' (1
TSTP1
page 22 of 22
MTV512M
Preliminary
ELECTRICAL PARAMETERS Absolute Maximum Ratings at: Ta= 0 to 70 oC, VSS=0V
Name
Maximum Supply Voltage Maximum Input Voltage (HSYNC, VSYNC & open-drain pins) Maximum Input Voltage (other pins) Maximum Output Voltage Maximum Operating Temperature Maximum Storage Temperature
Symbol VDD Vin1 Vin2 Vout Topg Tstg
Range -0.3 to +3.6 -0.3 to 3.3+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 0 to +70 -25 to +125
Unit V V V V oC oC
Allowable Operating Conditions at: Ta= 0 to 70 oC, VSS=0V
Name
Supply Voltage Input "H" Voltage Input "L" Voltage Operating Freq.
Symbol VDD Vih Vil Fopg
Condition
3.3V applications 3.3V applications 3.3V applications
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Min. 3.0 Max. 3.6 0.6 x VDD -0.3 VDD +0.3 0.3 x VDD 15 Min. 2.65 2.65 2.65 Typ. 18 1.3 50 150
Unit V V V MHz
DC Characteristics
Name
1) ,
Symbol Voh1 Voh2 Voh3 Vol Idd
at: Ta=0 to 70 oC, VDD=3.3V, VSS=0V
Output "H" Voltage, open drain pin
' (1
Condition
VDD=3.3V, Ioh=0A VDD=3.3V, Ioh=-50A VDD=3.3V, Ioh=-4mA Iol=5mA Active Idle Power-Down
Max.
Unit V V V
Output "H" Voltage, 8051 I/O port pin Output "H" Voltage, CMOS output Output "L" Voltage
&2
0.45 24 4.0 80 250 15
V mA mA A Kohm pF
Power Supply Current
RST Pull-Down Resistor Pin Capacitance
Rrst Cio
VDD=3.3V
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MTV512M
Preliminary
AC Characteristics at: Ta=0 to 70 oC, VDD=3.3V, VSS=0V
Name
Crystal Frequency PWM DAC Frequency HS input pulse Width VS input pulse Width HSYNC to Hblank output jitter H+V to Vblank output delay VS pulse width in H+V signal
Symbol fXtal fDA tHIPW tVIPW tHHBJ tVVBD tVCPW
Condition
Min.
Typ. 12
Max.
Unit MHz
fXtal=12MHz fXtal=12MHz fXtal=12MHz
46.875 0.3 3
94.86 7.5
KHz uS uS
5
fXtal=12MHz FXtal=12MHz
nS uS uS
8 20
Test Mode Condition
In normal application, users should avoid the MTV512M entering its test mode or writer mode, outlined as follows: adding pull-up resistor to HSCL1/HSDA1/HSCL2/HSDA2 pins is recommended. Test Mode: RESET's falling edge & HSCL1=0 & HSDA1 & HSCL2=0 & HSDA2 = 0
&2
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MTV512M
Preliminary
PACKAGE DIMENSION 44-pin PLCC
1) ,
Dimension in Millimeters Nom Min -
Symbol A A1 A2 b c b1 D E e Gd Ge Hd He L
' (1
Dimension in Inches Min 0.020 0.145 0.016 0.026 0.007 0.648 0.648 0.590 0.590 0.680 0.680 0.090 0 Nom 0.150 0.018 0.028 0.010 0.653 0.653 0.050 (Typ) 16.00 16.00 17.80 17.80 2.80 10 0.610 0.610 0.690 0.690 0.100 0.630 0.630 0.700 0.700 0.110 10 Max 0.185 0.155 0.022 0.032 0.013 0.658 0.658 Max 4.70 0.51
&2
0.41 0.65 0.18 16.46 16.46 15.00 15.00 17.30 17.30 2.29 0
3.70
3.80
3.90
0.46 0.70 0.25 16.60 16.60 1.27 (Typ) 15.50 15.50 17.50 17.50 2.54 -
0.56 0.80 0.33 16.71 16.71
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MTV512M
Preliminary
Ordering Information Standard Configurations: Prefix MTV Part Type 512M Package Type V: PLCC
&2
1) ,
' (1
page 26 of 26
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